K4H561638D-TCC4 Samsung, K4H561638D-TCC4 Datasheet
K4H561638D-TCC4
Specifications of K4H561638D-TCC4
Related parts for K4H561638D-TCC4
K4H561638D-TCC4 Summary of contents
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DDR SDRAM 256Mb D-die (x8, x16) 256Mb D-die DDR400 SDRAM Specification Revision 1.1 DDR SDRAM Rev. 1.1 Feb. 2003 ...
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DDR SDRAM 256Mb D-die (x8, x16) 256Mb D-die Revision History Revison 0.0 (June. 2002) 1. First release Revison 0.1 (Aug. 2002) - Changed IDD3P value from 40mA to 55m - Changed IDD3N value from 60mA to 75mA Revision 1.0 (February, ...
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... Auto & Self refresh • 7.8us refresh interval(8K/64ms refresh) • Maximum burst refresh cycle : 8 • 66pin TSOP II package Ordering Information Part No. K4H560838D-TCCC K4H560838D-TCC4 K4H561638D-TCCC K4H561638D-TCC4 Operating Frequencies - CC(DDR400@CL=3) Speed @CL3 200MHz CL-tRCD-tRP *CL : CAS Latency Org. Max Freq. ...
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DDR SDRAM 256Mb D-die (x8, x16) Pin Description DDQ DDQ SSQ SSQ ...
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DDR SDRAM 256Mb D-die (x8, x16) Package Physical Demension #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10×) 66pin TSOPII / Package dimension DDR ...
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DDR SDRAM 256Mb D-die (x8, x16) / Block Diagram (8Mbx8 4Mbx16 I Banks) Bank Select CK, CK ADD LCKE LRAS LCBR CK, CK CKE 8 /16 CK, CK Data Input Register Serial to parallel 16/ 32 4Mx16/ 2Mx32 ...
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DDR SDRAM 256Mb D-die (x8, x16) Input/Output Function Description SYMBOL TYPE CK, CK Input CKE Input CS Input RAS, CAS, WE Input LDM,(UDM) Input BA0, BA1 Input 12] Input DQ I/O LDQS,(U)DQS I VDDQ Supply ...
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DDR SDRAM 256Mb D-die (x8, x16) Command Truth Table COMMAND Register Extended MRS Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & ...
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... Banks / 4M x 16Bit x 4 Banks Double Data Rate SDRAM General Description The K4H560838D / K4H561638D is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 8,388,608 / 4x 4,194,304 words by 8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin ...
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DDR SDRAM 256Mb D-die (x8, x16) DDR SDRAM Spec Items & Test Conditions Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two ...
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DDR SDRAM 256Mb D-die (x8, x16) DDR SDRAM I spec table DD Symbol - CC(DDR400@CL=3) - C4(DDR400@CL=3) - CC(DDR400@CL=3) - C4(DDR400@CL=3) IDD0 105 IDD1 130 IDD2P 4 IDD2F 30 IDD2Q 25 IDD3P 55 IDD3N 75 IDD4R 185 IDD4W 220 IDD5 ...
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DDR SDRAM 256Mb D-die (x8, x16) AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point ...
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DDR SDRAM 256Mb D-die (x8, x16) Overshoot/Undershoot specification for Data, Strobe, and Mask Pins Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal ...
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DDR SDRAM 256Mb D-die (x8, x16) AC Timing Parameters and Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Internal write ...
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DDR SDRAM 256Mb D-die (x8, x16) Parameter Data hold skew factor Auto Precharge write recovery + precharge time Exit self refresh to non-READ command Exit self refresh to READ command Component Notes 1.V is the magnitude of the difference between ...
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DDR SDRAM 256Mb D-die (x8, x16) System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR400 devices to ensure proper system perfor- mance. these characteristics are for system simulation purposes and are guaranteed by design. ...
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DDR SDRAM 256Mb D-die (x8, x16) System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1. Output Figure 1 : Pullup slew rate test load b. Pulldown slew rate is measured under ...
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DDR SDRAM 256Mb D-die (x8, x16) j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser ...