K5A3280YBC-T755 Samsung, K5A3280YBC-T755 Datasheet
K5A3280YBC-T755
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K5A3280YBC-T755 Summary of contents
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... Initial Draft The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. MCP MEMORY Draft Date ...
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... Thickness BALL CONFIGURATION 69 Ball TBGA , 0.8mm Pitch Top View (Ball Down) SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. MCP MEMORY GENERAL DESCRIPTION The K5A3x80YT(B)C featuring single 3.0V power supply is a Multi Chip Package Memory which combines 32Mbit Dual Bank Flash and 8Mbit fCMOS SRAM ...
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... K5A3x80YT(B)C ORDERING INFORMATION Samsung MCP Memory Device Type Dual Bank Boot Block NOR + fCMOS SRAM NOR Flash Density (Bank Size), (Organization 32Mbit, (8Mb, 24Mb) (x8/x16 Selectable 32Mbit, (16Mb, 16Mb) (x8/x16 Selectable) SRAM Density , Organization ...
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K5A3x80YT(B)C Table 1. Flash Memory Top Boot Block Address (K5A3280YT/K5A3380YT Block A3280 A3380 A20 A19 A18 YT YT BA70 BA69 BA68 BA67 BA66 ...
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K5A3x80YT(B)C Table 1. Flash Memory Top Boot Block Address (K5A3280YT/K5A3380YT A3280 A3380 Block A20 A19 A18 YT YT BA34 Bank1 BA33 BA32 BA31 BA30 0 1 ...
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K5A3x80YT(B)C Table 3. Flash Memory Bottom Boot Block Address (K5A3280YB/K5A3380YB Block A3280 A3380 A20 A19 A18 YB YB BA70 BA69 BA68 BA67 BA66 ...
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K5A3x80YT(B)C Table 3. Flash Memory Bottom Boot Block Address (K5A3280YB/K5A3380YB Block A3280 A3380 A20 A19 A18 YB YB BA34 BA33 BA32 BA31 BA30 ...
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K5A3x80YT(B)C Flash MEMORY COMMAND DEFINITIONS Flash memory operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain mode, a proper command with specific address and data sequences must ...
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K5A3x80YT(B)C NOTES Read Address Program Address Read Data Program Data DA : Dual Bank Address (A19 - A20 Block Address (A12 - A20 Don’ t care . ...
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K5A3x80YT(B)C Table 8. SRAM Operation Table 1. Word Mode CS1 CS2 OE WE BYTE Vcc ...
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K5A3x80YT(B)C Flash DEVICE OPERATION Byte/Word Mode If the BYTE ball is set at logical "1" , the device is in word mode, DQ0-DQ15 are active. Otherwise the BYTE F , the device is in byte mode, DQ0-DQ7 are active. DQ8-DQ14 ...
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K5A3x80YT(B)C WE A20 A0(x16)/* 2AAH/ 555H/ AAAH 555H A20 A-1(x8) DQ15 DQ0 AAH NOTE: The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 6 for device code. Write (Program/Erase) Mode Flash memory ...
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K5A3x80YT(B)C Unlock Bypass Flash memory provides the unlock bypass mode to save its program time. The mode is invoked by the unlock bypass command sequence. Unlike the standard program command sequence that contains four bus cycles, the unlock bypass program ...
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K5A3x80YT(B)C WE A20 A0(x16)/ 555H/ 2AAH/ AAAH A20 A-1(x8) DQ15-DQ0 AAH RY/BY Figure 6. Block Erase Command Sequence Erase Suspend / Resume The Erase Suspend command interrupts the Block Erase to read or program data in a block that is ...
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K5A3x80YT(B)C Read While Write Flash memory provides dual bank memory architecture that divides the memory array into two banks. The device is capable of read- ing data from one bank and writing data to the other bank simultaneously. This is ...
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K5A3x80YT(B)C Block Protect Algorithm Set up Block Group address Block Group Protect: Write 60H to Block Group address with A6=0,A1=1 A0=0 Wait 150 s Verify Block Group Protect:Write 40H to Block Group address with A6=0, Increment A1=1,A0=0 COUNT Read from ...
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K5A3x80YT(B)C Table 10. Flash Memory Block Group Address (Top Boot Block) Block Group A20 A19 A18 BGA0 BGA1 BGA2 BGA3 BGA4 BGA5 ...
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K5A3x80YT(B)C Table 11. Flash Memory Block Group Address (Bottom Boot Block) Block Group A20 A19 A18 BGA0 BGA1 BGA2 BGA3 BGA4 BGA5 ...
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K5A3x80YT(B)C Write Protect (WP) The WP/ACC ball has two useful functions. The one is that certain boot block is protected by the hardware method not to use V The other is that program operation is accelerated to reduce the program ...
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K5A3x80YT(B)C Hardware Reset Flash memory offers a reset feature by driving the RESET ball to V When the RESET ball is driven low, any operation in progress will be terminated and the internal state machine will be reset to the ...
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K5A3x80YT(B)C Table 12. Common Flash Memory Interface Code Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none ...
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K5A3x80YT(B)C Table 12. Common Flash Memory Interface Code Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock(Bits 1- Required, 1= Not Required Silcon Revision Number(Bits 7-2) Erase Suspend 0 = Not ...
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K5A3x80YT(B)C DEVICE STATUS FLAGS Flash memory has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must include bank address being excuted internal routine operation. The status is indicated ...
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K5A3x80YT(B)C DQ3 : Block Erase Timer The status of the multi-block erase operation can be detected via the DQ3 ball. DQ3 will go High the block erase time win- dow expires. In this case, the Internal ...
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K5A3x80YT(B)C Start Yes DQ7 = Data ? No No DQ5 = 1 ? Yes Yes DQ7 = Data ? No Fail Figure 10. Data Polling Algorithms NOTES: 1. All protected block groups are unprotected WP/ACC = V 2. ...
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K5A3x80YT(B)C ABSOLUTE MAXIMUM RATINGS Parameter Vcc RESET Voltage on any ball relative to Vss WP/ACC All Other Balls Temperature Under Bias Storage Temperature Operating Temperature NOTES: 1. Minimum DC voltage is -0.3V on Input/ Output balls. During transitions, this level ...
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K5A3x80YT(B)C DC CHARACTERISTICS (Continued) Parameter Symbol Automatic Sleep Mode Voltage for WP/ACC Block Temporarily Unprotect and Flash Program Acceleration (4) Voltage for Autoselect and Block Protect (4) Low Vcc Lock-out Voltage ( Operating Current I SRAM Standby ...
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K5A3x80YT(B)C Flash AC CHARACTERISTICS Write(Erase/Program)Operations Alternate WE Controlled Write Parameter Write Cycle Time (1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (1) Read (1) Output Enable Hold Time Toggle and Data ...
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K5A3x80YT(B)C Flash AC CHARACTERISTICS Write(Erase/Program)Operations Alternate CE Controlled Writes F Parameter Write Cycle Time (1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (1) Read (1) Output Enable Hold Time Toggle and ...
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K5A3x80YT(B)C Flash SWITCHING WAVEFORMS Read Operations Address HIGH-Z Outputs HIGH RY/BY Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Time CE & OE Disable Time (1) F Output Hold Time from ...
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K5A3x80YT(B)C Flash SWITCHING WAVEFORMS Hardware Reset/Read Operations Address RESET High-Z Outputs Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold Time from Address RESET ...
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K5A3x80YT(B)C Flash SWITCHING WAVEFORMS Alternate WE Controlled Program Operations t AS 555H Address OES WPH A0H DATA t DS RY/BY NOTES: 1. DQ7 is ...
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K5A3x80YT(B)C Flash SWITCHING WAVEFORMS Alternate CE Controlled Program Operations F 555H Address WE t OES A0H DATA t DS RY/BY NOTES: 1. DQ7 is the output of the complement ...
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K5A3x80YT(B)C Flash SWITCHING WAVEFORMS Word to Byte Timing Diagram for Read Operation BYTE t DQ0-DQ7 DQ8-DQ14 DQ15/A-1 Byte to Word Timing Diagram for Read Operation BYTE t DQ0-DQ7 DQ8-DQ14 DQ15/A-1 BYTE Timing Diagram for ...
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K5A3x80YT(B)C Flash SWITCHING WAVEFORMS Chip/Block Erase Operations t AS 555H Address OES WPH AAH DATA t DS RY/BY Vcc F t VCS NOTE Block ...
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K5A3x80YT(B)C Flash SWITCHING WAVEFORMS Read While Write Operations Read Command t RC DA2 Address DA1 (555H OES Valid Valid DQ Output Input (A0H) NOTE: This is an example in the ...
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K5A3x80YT(B)C Flash SWITCHING WAVEFORMS Data Polling During Internal Routine Operation OEH2 WE Data In DQ7 DQ0-DQ6 Data In NOTE: *DQ7=Vaild Data (The device has completed the internal operation). RY/BY Timing Diagram During Program/Erase Operation CE F ...
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K5A3x80YT(B)C Flash SWITCHING WAVEFORMS Toggle Bit During Internal Routine Operation Address OEH2 DQ6/DQ2 Data In RY/BY NOTE: Address for the write operation must include a bank address (A19~A20) where the data is written. ...
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K5A3x80YT(B)C Flash SWITCHING WAVEFORMS RESET Timing Diagram High RY/ RESET RY/ RESET Power-up and RESET Timing Diagram RESET Vcc F Address DATA Parameter RESET Pulse Width RESET Low to Valid Data (During ...
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K5A3x80YT(B)C Flash SWITCHING WAVEFORMS Block Group Protect & Unprotect Operations RESET Vss BGA,A6 A1,A0 Block Group Protect / Unprotect DATA 60H RY/BY NOTES: Block Group Protect (A6= Block Group ...
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K5A3x80YT(B)C SRAM AC CHARACTERISTICS Parameter List Read cycle time Address access time Chip select to output Output enable to valid output UB, LB Access Time Chip select to low-Z output Read UB, LB enable to low-Z output Output enable to ...
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K5A3x80YT(B)C SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address CS1 S CS2 S UB Data out High-Z NOTES (READ CYCLE and are defined ...
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K5A3x80YT(B)C SRAM TIMING DIAGRAMS TIMING WAVEFORM OF WRITE CYCLE(1) Address CS1 S CS2 S UB High-Z Data in Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address CS1 S CS2 S UB Data in Data ...
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K5A3x80YT(B)C TIMING WAVEFORM OF WRITE CYCLE(3) Address CS1 S CS2 S UB Data in Data out NOTES (WRITE CYCLE wri e occurs during the overlap for single byte operation or simultaneously asserting ...
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K5A3x80YT(B)C PACKAGE DIMENSION 69-Ball Tape Ball Grid Array Package (measured in millimeters) Top View 8.00 ±0.10 #A1 0.08MAX Bottom View 8.00 ±0.10 (Datum A) 0.80 x9=7. 0. (Datum ...