K6X1008C2D-BF55

Manufacturer Part NumberK6X1008C2D-BF55
DescriptionK6X1008C2D-BF55128Kx8 bit Low Power CMOS Static RAM
ManufacturerSamsung
K6X1008C2D-BF55 datasheet
 


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Page 6/10:

TIMING DIAGRAMS

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K6X1008C2D Family

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1)
Address
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2)
Address
CS
1
CS
2
OE
High-Z
Data out
NOTES (READ CYCLE)
t
t
1.
and
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
HZ
OHZ
levels.
2. At any given temperature and voltage condition,
interconnection.
,
(Address Controlled
CS1=OE=V
, CS2=WE=V
IL
t
RC
t
AA
t
OH
(WE=V
)
IH
t
RC
t
AA
t
CO1
t
CO2
t
OE
t
OLZ
t
LZ
Data Valid
t
t
(Max.) is less than
(Min.) both for a given device and from device to device
HZ
LZ
6
CMOS SRAM
)
IH
Data Valid
t
OH
t
HZ(1,2)
t
OHZ
Revision 1.0
September 2003