K6X1008C2D-BF55

Manufacturer Part NumberK6X1008C2D-BF55
DescriptionK6X1008C2D-BF55128Kx8 bit Low Power CMOS Static RAM
ManufacturerSamsung
K6X1008C2D-BF55 datasheet
 


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DATA RETENTION WAVE FORM

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K6X1008C2D Family
TIMING WAVEFORM OF WRITE CYCLE(3)
Address
CS
1
CS
2
WE
Data in
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS
CS
going high and WE going low: A write end at the earliest transition among CS
2
t
is measured from the begining of write to the end of write.
WP
2. t
is measured from the CS
going low or CS
CW
1
3. t
is measured from the address valid to the beginning of write.
AS
4. t
is measured from the end of write to the address change. t
WR
in case a write ends as CS
going to low.
2

DATA RETENTION WAVE FORM

CS
controlled
1
V
CC
4.5V
2.2V
V
DR
CS
1
GND
CS
controlled
2
V
CC
4.5V
CS
2
V
DR
0.4V
GND
(CS
Controlled)
2
t
WC
t
t
AS(3)
CW(2)
t
AW
t
CW(2)
t
WP(1)
t
DW
Data Valid
High-Z
, a high CS
and a low WE. A write begins at the latest transition among CS
1
2
going high, CS
1
going high to the end of write.
2
applied in case a write ends as CS
WR
Data Retention Mode
t
SDR
CS V
- 0.2V
CC
Data Retention Mode
t
SDR
CS
0.2V
2
8
CMOS SRAM
t
WR(4)
t
DH
High-Z
goes low,
1
going low and WE going high,
2
or WE going high t
applied
1
WR2
t
RDR
t
RDR
Revision 1.0
September 2003