K6X4016T3F-TB55

Manufacturer Part NumberK6X4016T3F-TB55
DescriptionK6X4016T3F-TB55256Kx16 bit Low Power and Low Voltage CMOS Static RAM
ManufacturerSamsung
K6X4016T3F-TB55 datasheet
 


1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
Page 8/9:

DATA RETENTION WAVE FORM

Download datasheet (100Kb)Embed
PrevNext
K6X4016T3F Family
TIMING WAVEFORM OF WRITE CYCLE(3)
Address
CS
UB, LB
WE
Data in
High-Z
Data out
NOTES (WRITE CYCLE)
1. A wri
e occurs during the overlap(t
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
t
WP
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The t
2. t
is measured from the CS going low to the end of write.
CW
3. t
is measured from the address valid to the beginning of write.
AS
4. t
is measured from the end of write to the address change. t
WR

DATA RETENTION WAVE FORM

CS controlled
V
CC
2.7V
2.2V
V
DR
CS
GND
(UB, LB Controlled)
t
WC
t
CW(2)
t
AW
t
BW
t
AS(3)
t
WP(1)
t
DW
Data Valid
is measured from the beginning of write to the end of write.
WP
is applied in case a write ends with CS or WE going high.
WR
Data Retention Mode
t
SDR
CS V
- 0.2V
CC
8
CMOS SRAM
t
WR(4)
t
DH
High-Z
t
RDR
Revision 1.0
August 2003