MC145532DW Motorola, MC145532DW Datasheet

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MC145532DW

Manufacturer Part Number
MC145532DW
Description
MC145532DWMotorola, Inc [ADPCM Transcoder]
Manufacturer
Motorola
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
ADPCM Transcoder
Conforms to G.721–1988 and T1.301–1987
Transcoder provides a low–cost, full–duplex, single–channel transcoder to
(from) a 64 kbps PCM channel from (to) either a 16 kbps, 24 kbps, 32 kbps, or
64 kbps channel.
REV 1
9/95 (Replaces NP470)
MOTOROLA
MODE
The MC145532 Adaptive Differential Pulse Code Modulation (ADPCM)
DDO
Motorola, Inc. 1995
DOE
DDC
APD
V SS
Complies with CCITT Recommendation G.721–1988
Complies with the American National Standard (T1.301–1987)
Full–Duplex, Single–Channel Operation
Mu–Law or A–Law Coding is Pin Selectable
Synchronous or Asynchronous Operation
Easily Interfaces with Any Member of Motorola’s PCM Codec–Filter
Mono–Circuit Family or Other Industry Standard Codec
Serial PCM and ADPCM Data Transfer Rate from 64 kbps to 5.12 Mbps
Power–Down Capability for Low Current Consumption
The Reset State, an Option Specified in the Standards, is Automatically
Initiated When the RESET Pin is Released
Simple Time Slot Assignment Timing for Transcoder Applications
Single 5 V Power Supply
16–Pin Package
The MC145536EVK is the Evaluation Platform for the MC145532 and Also
Includes the MC145480 5 V PCM Codec–Filter
DDI
DIE
S REG
S REG
LATCH
REG
BLOCK DIAGRAM
PROCESSOR
I/O DATA BUS
DIGITAL
SIGNAL
LATCH
REG
S REG
S REG
16
EDO
EDE
EDC
EDI
EIE
RESET
SPC
V DD
16
MC145532DW SOG Package
MC145532L
ORDERING INFORMATION
1
MC145532
RESET
MODE
1
DDO
DOE
DDC
V SS
DDI
DIE
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
CERAMIC PACKAGE
Ceramic Package
SOG PACKAGE
Order this document
DW SUFFIX
CASE 751G
CASE 620
L SUFFIX
16
15
14
13
12
10
11
9
by MC145532/D
MC145532
V DD
EDO
EOE
EDC
EDI
EIE
SPC
APD
1

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MC145532DW Summary of contents

Page 1

... SIGNAL S REG REG PROCESSOR Order this document by MC145532/D MC145532 DW SUFFIX SOG PACKAGE 16 CASE 751G 1 L SUFFIX CERAMIC PACKAGE 16 CASE 620 1 ORDERING INFORMATION MC145532DW SOG Package MC145532L Ceramic Package PIN ASSIGNMENT MODE DDO 2 15 EDO DOE 3 14 EOE DDC 4 13 ...

Page 2

... A rising edge on this pin causes power to be restored and the optional transcoder RESET state (specified in the standards forced. Valid data is available at the output pins four input enables after a rising edge on this pin. This pin has a CMOS compatible input. MOTOROLA ...

Page 3

... The determination of short frame mode is made by the MC145532 based on one falling EDC edge while EIE is high. MOTOROLA Note that only a 32 kbps encoding rate can be specified when using short frame mode on the encoder input. ENCODER INPUT — LONG FRAME Figure 2 shows the clock, enable, and data signals for the encoder input in long frame mode ...

Page 4

... V out ) Unused inputs must always be tied to an appropriate logic voltage level (e.g., either Min Max Unit 4.50 5.50 V — 0.28 W Min Max Unit 2.0 — V — 0 — V — 0 — 1.0 A — 4.6 — V — 0.4 V — 5.0 A Min Max Unit 19.990 23 MHz MOTOROLA ...

Page 5

... Enable Valid Time Enable Hold Time Data Valid Time Data Hold Time EDC EIE MSB EDI EDC t h(EIE)H EIE EDI Figure 1. Encoder Input Timing — Short Frame MOTOROLA Symbol t su(EIE)L t h(EIE)H t V(EIE) t h(EIE) t v(EDI) t h(EDI LSB MSB t v(EIE) ...

Page 6

... EIE 64 kbps EDI MSB EDC t h(EIE)L EIE EDI Figure 2. Encoder Input Timing — Long Frame MC145532 6 Symbol t h(EIE)L t v(EIE) t v(EDI) t h(EDI LSB MSB t v(EIE) t h(EDI) t v(EDI) MSB Min Max Unit 30 — — — — ns LSB MOTOROLA ...

Page 7

... EOE * LSB EDO MSB * 32 kbps transcoding rate selected for this frame at EIE EDC t h(EOE)L t v(EOE) EOE EDO Figure 3. Encoder Output Timing — Short Frame MOTOROLA ( 5 – Symbol t h(EOE)L t v(EOE) t h(EOE) t v(EDO) t z(EDO MSB @ 64 kbps transcoding rate selected for this frame at EIE ...

Page 8

... Figure 4. Encoder Output Timing — Long Frame MC145532 5 – Symbol t h(EOE)L t v(EOE) t EOE–EDO t EDC–EDO LSB MSB MSB MSB MSB t v(EOE) t EOE–EDO MSB Min Max Unit 30 — — ns — — MSB MSB MOTOROLA ...

Page 9

... Enable Hold Time from Falling DDC Data Valid Time Before Falling DDC Data Hold Time from Falling DDC DDC DIE MSB DDI DDC t h(DIE)H DIE DDI Figure 5. Decoder Input Timing — Short Frame MOTOROLA Symbol t su(DIE)L t h(DIE)H t v(DIE) t h(DIE) t v(DDI) t h(DDI MSB 1 ...

Page 10

... MSB DDI DDC DIE DDI Figure 6. Decoder Input Timing — Long Frame MC145532 10 Symbol t h(DIE) t v(DIE) t v(DDI) t h(DDI LSB MSB MSB MSB MSB t h(DIE) t v(DIE) t h(DDI) t v(DDI) MSB Min Max Unit 30 — — — — ns MOTOROLA ...

Page 11

... Delay Time from 8th DDC Low to DDO Output Disabled DDC DOE DDO MSB DDC t h(DOE)L t v(DOE) DOE DDO Figure 7. Decoder Output Timing — Short Frame MOTOROLA ( 5 – Symbol t h(DOE)L t v(DOE) t h(DOE) t v(DDO) t z(DDO LSB MSB t h(DOE) ...

Page 12

... Figure 8. Decoder Output Timing — Long Frame MC145532 5 – Symbol t h(DOE)L t v(DOE) t DOE–DDO t DDC–DDO t z(DDO MSB t v(DOE) t DOE–DDO MSB Min Max Unit 30 — — ns — — MOTOROLA ...

Page 13

... TS 4 PCM BUS OUT DDO DDO x PCM BUS IN EDI EDI ADPCM BUS OUT EDO zy EDO zx ADPCM BUS IN DDI zy DDI zx MOTOROLA MC145532 + 5 V MODE V DD DDO EDO TS 1 DOE EOE DDC EDC DDI EDI TS 3 DIE EIE RESET SPC ...

Page 14

... RDC DDC DDI TDC TDD DIE TDE RESET ADPCM OUT EDO TSm EOE 1.544 MHz EDC EDI EIE 20.48 MHz SPC APD MOTOROLA ...

Page 15

... MHz = MCLK R = BCLK R = DDC 1 = MCLK X = BCLK X = EDC 8 kHz = DOE = DIE = EOE = EIE = F SX EDI = D X ADPCM OUT = EDO DDO = D R ADPCM IN = DDI Figure 11. ADPCM Transcoder/Codec Application (A–Law) MOTOROLA MC145557 GNDA VF X I– ...

Page 16

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “ ...

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