MC68HC908AS60CFU Motorola, MC68HC908AS60CFU Datasheet

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MC68HC908AS60CFU

Manufacturer Part Number
MC68HC908AS60CFU
Description
MC68HC908AS60CFUHCMOS Microcontroller Unit
Manufacturer
Motorola
Datasheet

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MC68HC908AS60/D
REV 1
查询08M68HC08M供应商
Freescale Semiconductor, Inc.
MC68HC908AS60
Technical Data
HCMOS
Microcontroller Unit

Related parts for MC68HC908AS60CFU

MC68HC908AS60CFU Summary of contents

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Freescale Semiconductor, Inc. MC68HC908AS60/D REV 1 MC68HC908AS60 Technical Data HCMOS Microcontroller Unit ...

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... Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...

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... Section 13. Monitor ROM (MON 191 Section 14. Computer Operating Properly Section 15. Low-Voltage Inhibit (LVI) Module . . . . . . . 209 Section 16. External Interrupt Module (IRQ 215 Section 17. Serial Communications MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, (COP) Module . . . . . . . . . . . . . . . . . . . . . . 203 Interface (SCI 223 List of Sections Go to: www.freescale.com ...

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... Section 22. Timer Interface Module A (TIMA- 375 Section 23. Analog-to-Digital Converter (ADC-15 407 Section 24. Electrical Specifications 419 Section 25. Mechanical Specifications . . . . . . . . . . . . . 433 Section 26. Ordering Information . . . . . . . . . . . . . . . . . 437 Index 439 Technical Data 4 Controller-Digital (BDLC- 327 List of Sections For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power Supply Pins (V and V DD Oscillator Pins (OSC1 and OSC2 .40 External Reset Pin (RST External Interrupt Pin (IRQ Analog Power Supply Pin (V Analog Ground Pin (V ) ...

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... FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . 68 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 FLASH-1 Block Protect Register . . . . . . . . . . . . . . . . . . . . . 72 FLASH-2 Block Protect Register . . . . . . . . . . . . . . . . . . . . . 73 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Section 5. FLASH-2 Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 FLASH Charge Pump Frequency Control . . . . . . . . . . . . . . . . 81 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . 82 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . 86 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Section 6. EEPROM-1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Features ...

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... Accumulator ( 116 Index Register (H:X 116 Stack Pointer (SP 117 Program Counter (PC .118 Condition Code Register (CCR 119 Arithmetic/Logic Unit (ALU 121 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 122 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Section 9. System Integration Module (SIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 137 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . 137 Clocks in Stop Mode and Wait Mode ...

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... CGM Base Clock Output (CGMOUT 168 CGM CPU Interrupt (CGMINT 168 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . 171 PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . . 173 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table of Contents For More Information On This Product, Go to: www.freescale.com ) . . . . . . . . . . . . . . . . . . . . . . . . . . 168 MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 175 Section 11. Configuration Register (CONFIG-1) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Section 12. Break Module Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Features ...

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... STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Reset Vector Fetch 206 COPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 COPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Interrupts 207 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . .208 Section 15. Low-Voltage Inhibit (LVI) Module Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Forced Reset Operation ...

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... I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 PTE0/SCTxD (Transmit Data 241 PTE1/SCRxD (Receive Data 242 I/O Registers 242 SCI Control Register .242 SCI Control Register .245 SCI Control Register .248 SCI Status Register 250 Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 18.13.1 MISO (Master In/Slave Out 280 18.13.2 MOSI (Master Out/Slave In 280 18.13.3 SPSCK (Serial Clock 280 MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, SCI Status Register 253 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Section 18. Serial Peripheral Interface (SPI) Contents ...

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... TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 299 Section 20. Input/Output (I/O) Ports Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Port 304 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Data Direction Register 304 Port 306 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Data Direction Register 307 Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Port 308 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Data Direction Register 309 Port 311 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Data Direction Register 312 Port 314 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Data Direction Register 316 Port 318 Port F Data Register ...

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... Valid Active Logic 348 Valid SOF Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Valid BREAK Symbol 349 Message Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Protocol Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 Rx and Tx Shift Registers 352 Rx and Tx Shadow Registers . . . . . . . . . . . . . . . . . . . . . . .353 Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . . . .353 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 4X Mode .353 Receiving a Message in Block Mode . . . . . . . . . . . . . . . 354 Transmitting a Message in Block Mode . . . . . . . . . . . . . 354 J1850 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 BDLC CPU Interface 357 BDLC Analog and Roundtrip Delay . . . . . . . . . . . . . . . . . .358 BDLC Control Register 1 ...

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... I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 ADC Analog Power Pin (V Voltage Reference Pin (V ADC Analog Ground Pin (V Voltage Reference Low Pin (V ADC Voltage In (ADCVIN 412 Table of Contents For More Information On This Product, Go to: www.freescale.com )/ADC DDAREF ). . . . . . . . . . . . . . . . . . .412 REFH )/ADC SSA ) . . . . . . . . . . . . . . . 412 REFL MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... BDLC Transmitter VPW Symbol Timings . . . . . . . . . . . . . . . . 431 24.15 BDLC Receiver VPW Symbol Timings . . . . . . . . . . . . . . . . . . 431 25.1 25.2 25.3 25.4 MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, I/O Registers 413 ADC Status and Control Register 413 ADC Data Register 416 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . 416 Section 24. Electrical Specifications Contents ...

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... Freescale Semiconductor, Inc. Table of Contents 26.1 26.2 26.3 Technical Data 22 Section 26. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437 Index Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Title MCU Block Diagram for the MC68HC08ASxx Emulator . . . . .36 MC68HC908AS60 (52-Pin PLCC MC68HC908AS60 (64-Pin QFP Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Memory Map Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . . 51 FLASH-1 Control Register (FLCR1 Smart Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 71 FLASH-1 Block Protect Register (FLBPR1 .72 FLASH-2 Block Protect Register (FLBPR2) ...

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... SIM I/O Register Summary 136 CGM Clock Signals .137 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 List of Figures For More Information On This Product, Go to: www.freescale.com Page MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... SCI Status Register 1 (SCS1 250 17-13 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 17-14 SCI Status Register 2 (SCS2 253 17-15 SCI Data Register (SCDR 254 17-16 SCI Baud Rate Register (SCBR 255 MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Title List of Figures Go to: www.freescale.com List of Figures ...

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... Port C I/O Circuit 310 20-11 Port D Data Register (PTD 311 20-12 Data Direction Register D (DDRD 312 20-13 Port D I/O Circuit 313 20-14 Port E Data Register (PTE 314 20-15 Data Direction Register E (DDRE 316 Technical Data 26 Title List of Figures For More Information On This Product, Go to: www.freescale.com Page MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... Types of In-Frame Response (IFR 366 21-20 BDLC State Vector Register (BSVR 370 21-21 BDLC Data Register (BDR 372 22-1 TIMA Block Diagram 377 22-2 TIMA I/O Register Summary 378 MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Title EOF and IFS Symbol Times . . . . . . . . . . . . . . . . . . . . . . .347 List of Figures Go to: www.freescale.com ...

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... SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 426 24-2 SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 24-3 BDLC Variable Pulse-Width Modulation (VPW) Technical Data 28 Title (TAMODH and TAMODL 396 and Control Registers (TACC0–TASC5 .397 Symbol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 List of Figures For More Information On This Product, Go to: www.freescale.com Page MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... Variable Definitions .163 10-2 VCO Frequency Multiplier (N) Selection 173 11-1 COP Time Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Title External Pins Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Charge Pump Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . .67 Erase Block Sizes Charge Pump Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . .81 Erase Block Sizes ...

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... Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 20-3 Port C Pin Functions 310 20-4 Port D Pin Functions 313 20-5 Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 20-6 Port F Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 20-7 Port G Pin Functions 322 Technical Data 30 Title List of Tables For More Information On This Product, Go to: www.freescale.com Page MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... Prescaler Selection .394 22-2 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 401 23-1 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415 23-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 26-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437 MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Title Control Bit Priority Encoding . . . . . . . . . . . . . . . . . . . . . . .365 List of Tables Go to: www.freescale.com List of Tables ...

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... Freescale Semiconductor, Inc. List of Tables Technical Data 32 List of Tables For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power Supply Pins (V and V DD Oscillator Pins (OSC1 and OSC2 .40 External Reset Pin (RST External Interrupt Pin (IRQ Analog Power Supply Pin (V Analog Ground Pin (V ) ...

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... No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH/EEPROM difficult for unauthorized users. Technical Data 34 High-performance M68HC08 architecture Fully upward-compatible object code with M6805, M146805, and M68HC05 Families 8 ...

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... MCU Block Diagram Figure 1-1 MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Serial communications interface module (SCI) 8-bit, 15-channel analog-to-digital converter (ADC-15) 16-bit, 6-channel timer interface module (TIMA-6) Modulo timer (TIM) SAE J1850 byte data link controller digital module (BDLC-D) System protection features: – ...

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... Freescale Semiconductor, Inc. General Description PTA PTB PTC DDRC DDRA DDRB Technical Data 36 PTD PTE DDRD DDRE General Description For More Information On This Product, Go to: www.freescale.com PTF PTG PTH DDRF DDRG DDRH BDTxD BDRxD MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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... PTF3/TACH5 14 BDRxD 15 BDTxD 16 PTE0/TxD 17 PTE1/RxD 18 PTE2/TACH0 19 PTE3/TACH1 20 Figure 1-2. MC68HC908AS60 (52-Pin PLCC) MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, shows the MC68HC908AS60 pin assignments for the 52-pin General Description Go to: www.freescale.com General Description Pin Assignments PTD3/ATD11 46 PTD2/ATD10 45 PTD1/ATD9 44 PTD0/ATD8 43 PTB7/ATD7 ...

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... MC68HC908AS60 64-pin Section 20. Input/Output (I/O) General Description For More Information On This Product, Go to: www.freescale.com PTH0 48 PTD3/ATD11 47 PTD2/ATD10 REFL V 44 DDAREF PTD1/ATD9 43 PTD0/ATD8 42 PTB7/ATD7 41 PTB6/ATD6 40 PTB5/ATD5 39 PTB4/ATD4 38 PTB3/ATD3 37 PTB2/ATD2 36 PTB1/ATD1 35 PTB0/ATD0 34 PTA7 33 Ports. MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 39

... See Section 18. Serial Peripheral Interface NOTE: V must be grounded for proper MCU operation. SS MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, and are the power supply and ground pins. The MCU operates SS 1-4 ...

Page 40

... SSA digital ground pin. The analog sections consist of a clock generator (ADC-15). General Description For More Information On This Product, Go to: www.freescale.com (CGM). Section 9. System Section 16. External Section 10. Clock Generator and Section 23. MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 41

... See MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Section 20. Input/Output (I/O) Section 23. Analog-to-Digital (ADC-15), and Section 20 ...

Page 42

... Section 21. Byte Data Link Controller-Digital Technical Data 42 (SCI), Section 18. Serial Peripheral Interface (TIMA-6), and Ports. and Section 20. Input/Output (I/O) General Description For More Information On This Product, Go to: www.freescale.com (SPI), Section Section 20. Input/Output Section 22. Timer Interface Ports. (BDLC-D). (BDLC-D). MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 43

... PTE5/MISO PTE4/SS PTE3/TACH1 PTE2/TACH0 PTE1/RxD PTE0/TxD PTF6 Available in 64-pin package only PTF5/TBCH1–PTF4/TBCH0 Available in 64-pin package only MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Table 1-1. External Pins Summary Function Driver Type General-purpose I/O General-purpose I/O ADC channel General-purpose I/O General-purpose I/O General-purpose I/O ADC channel/timer ...

Page 44

... Driver Type Hysteresis Reset State Dual state Yes Input Hi-Z Dual state Yes Input Hi-Z Dual state Yes Input Hi-Z Dual state Yes Input Hi-Z Dual state Yes Input Hi-Z Dual state Yes Input Hi-Z N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Input Hi-Z N/A N/A Output N/A N/A N/A N/A N/A Input Hi-Z N/A N/A Output low N/A No Input Hi-Z Output No Output low MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 45

... Freescale Semiconductor, Inc. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Table 1-2. Clock Source Summary Module ADC BDLC COP CPU EEPROM SPI SCI TIMA-6 Bus clock or PTD6/ATD14/TACLK TIM SIM CGMOUT and CGMXCLK IRQ BRK LVI CGM General Description Go to: www.freescale.com ...

Page 46

... Freescale Semiconductor, Inc. General Description Technical Data 46 General Description For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 47

... These definitions apply to the memory map representation of reserved and unimplemented locations. • • MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Section 2. Memory Map Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Input/Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 2-1, includes: 60 Kbytes of FLASH EEPROM 2048 bytes of RAM 1024 bytes of EEPROM with protect option ...

Page 48

... For More Information On This Product, Go to: www.freescale.com $0000 $003F $0040 $004A $004B $004F $0050 $044F $0450 $05FF $0600 $07FF $0800 $09FF $0A00 $0DFF $0E00 $7FFF $8000 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 49

... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, FLASH CONTROL REGISTER (FLCR1) BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) BREAK STATUS AND CONTROL REGISTER (BSCR) LVI STATUS REGISTER (LVISR) RESERVED ...

Page 50

... FLASH block protect register, FLBPR1 $FF81 — FLASH block protect register, FLBPR2 $FFFF — COP control register, COPCTL is a list of vector locations. Memory Map For More Information On This Product, Go to: www.freescale.com Figure 2-2, contain most of the MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 51

... Port E Data Register $0008 (PTE) See page 314. Port F Data Register (PTF) $0009 See page 318. Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Bit Read: PTA7 PTA6 PTA5 Write: Reset: ...

Page 52

... CPOL CPHA SPWOM SPE MODF SPTE MODFEN SPR1 WAKE ILTY PEN Reserved U = Unaffected MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit 0 PTG0 PTH0 DDRE0 0 DDRF0 0 DDRG0 0 DDRH0 0 SPTIE 0 SPR0 PTY 0 ...

Page 53

... PLL Bandwidth Control Register (PBWC) See page 171. $001E PLL Programming Register (PPG) See page 173. Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Bit Read: SCTIE TCIE SCRIE Write: ...

Page 54

... MS0A ELS0B ELS0A TOV0 MS1A ELS1B ELS1A TOV1 Reserved U = Unaffected MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit 0 COPD 0 PS0 0 Bit Bit Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8 Bit 0 CH1MAX 0 ...

Page 55

... Timer A Channel 4 Status and Control Register (TASC4) See page 397. $0033 Timer A Channel 4 Register High (TACH4H) See page 403. Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Bit Read: Bit ...

Page 56

... ADICLK BO3 BO2 BO1 NBFS TEOD TSIFR TMIFR1 Reserved U = Unaffected MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit 0 Bit 0 CH5MAX 0 Bit 8 Bit 0 ADCH0 1 AD0 BO0 1 WCM 0 TMIFR0 0 ...

Page 57

... SIM Break Status Register (SBSR) See page 151. $FE01 SIM Reset Status Register (SRSR) See page 153. Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Bit Read Write: Reset: ...

Page 58

... BLK0 HVEN MARGIN ERASE EEBP2 EEBP1 0 EELAT Reserved U = Unaffected MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit PGM 0 Bit 8 0 Bit PGM 0 EEBP0 EEPGM 0 R ...

Page 59

... FLASH-2 Block Protect Register (FLBPR2) See page 73. $FFFF COP Control Register (COPCTL) See page 207. Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Bit Read: EERA CON2 CON1 EEPRTCT EEBP3 ...

Page 60

... PLL vector (low) $FFFA IRQ1 vector (high) $FFFB IRQ1 vector (low) $FFFC SWI vector (high) $FFFD SWI vector (low) $FFFE Reset vector (high) $FFFF Reset vector (low) Memory Map For More Information On This Product, Go to: www.freescale.com Vector MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 61

... RAM locations efficiently. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Random-Access Memory (RAM) Go to: www ...

Page 62

... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU could overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data 62 Random-Access Memory (RAM) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 63

... This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Section 4. FLASH-1 Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 FLASH-1 Control Register ...

Page 64

... Technical Data 64 $8000–$FDFF $FF80–$FF81, block protect registers $FE0B, FLASH control register $FFDA–$FFFF, reserved for user-defined interrupt and reset vectors Operation). FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com 4.7 FLASH MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 65

... This read/write bit together with FDIV1 selects the factor by which the charge pump clock is divided from the system clock. See Charge Pump Frequency 1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908AS60 — Rev. 1.0 ...

Page 66

... High voltage disabled to array and charge pump off 1 = Margin read operation selected 0 = Margin read operation unselected 1 = Erase operation selected 0 = Erase operation unselected 1 = Program operation selected 0 = Program operation unselected FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com for a description of for a description of MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 67

... Ensure target portion of array is unprotected by reading the block 3. Write to any FLASH address with any data within the block 4. Set the HVEN bit. 5. Wait for a time Clear the HVEN bit. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Table 4-1. Charge Pump Clock Frequency FDIV0 Pump Clock Frequency 0 ...

Page 68

... Table 4-2. Erase Block Sizes BLK0 FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com Block Size, Addresses Cared Full array: 30 Kbytes One-half array: 16 Kbytes (A14) Eight rows: 512 bytes (A14–A9) Single row: 64 bytes (A14–A6) MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 69

... Clear the MARGIN bit. NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, 24.13 Memory Characteristics operation and enables the latching of address and data for programming. ...

Page 70

... Technical Data 70 is always required when programming any part of the Register. The block protect register itself HI FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com 4.6 FLASH Erase present HI on the IRQ pin also allows entry into MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 71

... Page Program/Margin Read Procedure Note: This algorithm is mandatory for programming the FLASH 2TS. Note: This page program algorithm assumes the page programmed are initially erased. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, CLEAR MARGIN BIT INCREMENT ATTEMPT COUNTER NO ATTEMPT COUNT EQUAL TO ...

Page 72

... Address range protected from erase or program 0 = Address range open to erase or program 1 = Address range protected from erase or program 0 = Address range open to erase or program FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com BPR3 BPR2 BPR1 MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit 0 BPR0 0 ...

Page 73

... FLASH-2 array. Address: Read: Write: Reset: BPR3 — Block Protect Register Bit 3 This bit protects the FLASH memory contents in the address range $4000–$7FFF. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, $FF81 Bit ...

Page 74

... Address range open to erase or program 1 = Address range protected from erase or program 0 = Address range open to erase or program 1 = Address range protected from erase or program 0 = Address range open to erase or program FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com on the HI MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 75

... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, FLASH-1 Memory Go to: www.freescale.com ...

Page 76

... Freescale Semiconductor, Inc. FLASH-1 Memory Technical Data 76 FLASH-1 Memory For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 77

... This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Section 5. FLASH-2 Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 FLASH Control Register ...

Page 78

... Technical Data 78 $0450–$05FF $0E00–$7FFF $FE11, FLASH-2 control register Operation. $7F40–$7F7F (Row 509) $7F80–$7FBF (Row 510) $7FC0–$7FFF (Row 511) FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com 5.7 FLASH MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 79

... BLK1 — Block Erase Control Bit This read/write bit together with BLK0 allows erasing of blocks of varying size. See available block sizes security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 80

... High voltage disabled to array and charge pump off 1 = Margin read operation selected 0 = Margin read operation unselected 1 = Erase operation selected 0 = Erase operation unselected 1 = Program operation selected 0 = Program operation unselected FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com for a description of MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 81

... Ensure target portion of array is unprotected by reading the block 3. Write to any FLASH address with any data within the block 4. Set the HVEN bit. 5. Wait for a time Clear the HVEN bit. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Table 5-1. Charge Pump Clock Frequency FDIV0 Pump Clock Frequency 0 ...

Page 82

... Table 5-2. Erase Block Sizes BLK0 FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Block Size, Addresses Cared Full array: 24 Kbytes One-half array: 16 Kbytes (A14) Eight rows: 512 bytes (A14–A9) Single row: 64 bytes (A14–A6) MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 83

... Clear the MARGIN bit. NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, 24.13 Memory Characteristics operation and enables the latching of address and data for programming. ...

Page 84

... Technical Data 84 is always required when programming any part of the Register. The block protect register itself can on the IRQ pin also allows entry into HI FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com 5.6 FLASH Erase present on HI MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 85

... Page Program/Margin Read Procedure Note: This algorithm is mandatory for programming the FLASH 2TS. Note: This page program algorithm assumes the page programmed are initially erased. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, CLEAR MARGIN BIT INCREMENT ATTEMPT COUNTER NO ATTEMPT COUNT EQUAL TO ...

Page 86

... If the memory is in either program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1, Technical Data 86 for definition of this register. Each bit, when FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com Figure 4-4. FLASH-2 Block MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 87

... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, FLASH-2 Memory Go to: www.freescale.com ...

Page 88

... Freescale Semiconductor, Inc. FLASH-2 Memory Technical Data 88 FLASH-2 Memory For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 89

... MC68HC908AS60 are physically located in two 512-byte arrays. This section details the array covering the address range $0800–$09FF. For information relating to the array covering address range $0600–$07FF, see Section 7. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Section 6. EEPROM-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 EEPROM Programming ...

Page 90

... Technical Data 90 Byte, block, or bulk erasable Non-volatile redundant array option Non-volatile block protection option Non-volatile MCU configuration bits On-chip charge pump for programming/erasing Security option EEPROM-1 For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 91

... Setting EELAT bit configures the address and data buses to latch c. To ensure proper programming sequence, the EEPGM bit cannot d. Any attempt to clear both EEPGM and EELAT bits with a single MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, notes a and b program the byte. ...

Page 92

... EEPROM. EENVR1 is not affected with block or bulk erase. Any attempts to read other EEPROM data will read the latched data. If EELAT is set, other writes to the EECR1 will be allowed only after a valid EEPROM write. EEPROM-1 For More Information On This Product, Go to: www.freescale.com /t . EEBULK. MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 93

... EEPROM Data To Be MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, non-EEPROM write has occurred. This is to ensure proper erasing sequence. Once EEPGM is set, the type of erase mode cannot be modified ...

Page 94

... Technical Data 94 Table 6-2. EEPROM Array Address Blocks Block Number (EEBPx) EEBP0 EEBP1 EEBP2 EEBP3 EEPROM-1 For More Information On This Product, Go to: www.freescale.com Table 6-2 Address Range $0800–$087F $0880–$08FF $0900–$097F $0980–$09FF MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 95

... The MC68HC908AS60 has a special protection option which prevents program/erase access to memory locations $08F0–$08FF. This protect function is enabled by programming the EEPRTCT bit in the EENVR to 0. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, EEPROM-1 Go to: www.freescale.com EEPROM-1 Functional Description ...

Page 96

... EEOFF EERAS1 Unimplemented Figure 6-1. EEPROM-1 Control Register (EECR1 Bus clock drives charge pump Internal RC oscillator drives charge pump. EEPROM-1 For More Information On This Product, Go to: www.freescale.com note b and EERAS0 EELAT MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit 0 EEPGM 0 ...

Page 97

... This read/write bit latches the address and data buses for programming the EEPROM array. EELAT cannot be cleared if EEPGM is still set. Reset clears this bit. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product Disable EEPROM array 0 = Enable EEPROM array Table 6-3. EEPROM Program/Erase Mode Select ...

Page 98

... EERA CON2 CON1 EEPRTCT = Unimplemented Figure 6-3. EEPROM-1 Array Control Register (EEACR1) EEPROM-1 For More Information On This Product, Go to: www.freescale.com and Figure 6- EEBP3 EEBP2 EEBP1 EEBP3 EEBP2 EEBP1 EENVR MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit 0 EEBP0 Bit 0 EEBP0 ...

Page 99

... These read/write bits select blocks of EEPROM array from being programmed or erased. Reset loads EEBP3–EEBP0 from EENVR1 to EEACR1. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product EEPROM array is in redundant mode configuration EEPROM array is in normal mode configuration EEPROM protection disabled 0 = EEPROM protection enabled 1 = EEPROM array block is protected ...

Page 100

... The module requires a recovery time, t stop mode. Attempts to access the array during the recovery time will result in unpredictable behavior. Technical Data 100 EEPROM-1 For More Information On This Product, Go to: www.freescale.com , to stabilize after leaving EESTOP MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 101

... Introduction This section describes the electrically erasable programmable read-only memory (EEPROM-2) covering the address range $0600–$07FF. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Section 7. EEPROM-2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 EEPROM Erasing 104 EEPROM Block Protection ...

Page 102

... Technical Data 102 Byte, block, or bulk erasable Non-volatile redundant array option Non-volatile block protection option Non-volatile MCU configuration bits On-chip charge pump for programming/erasing Security option EEPROM-2 For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 103

... Setting EELAT bit configures the address and data buses to latch c. To ensure proper programming sequence, the EEPGM bit cannot d. Any attempt to clear both EEPGM and EELAT bits with a single MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, value (See notes a and b.) EEPGM , to program the byte ...

Page 104

... Any attempts to read other EEPROM data will read the latched data. If EELAT is set, other writes to the EECR2 will be allowed after a valid EEPROM write. EEPROM-2 For More Information On This Product, Go to: www.freescale.com /t . EEBULK MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 105

... EEPROM Data To Be MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, non-EEPROM write has occurred. This is to ensure proper erasing sequence. Once EEPGM is set, the type of erase mode cannot be modified ...

Page 106

... Technical Data 106 Table 7-2. EEPROM Array Address Blocks Block Number (EEBPx) EEBP0 EEBP1 EEBP2 EEBP3 EEPROM-2 For More Information On This Product, Go to: www.freescale.com Table 7-2 Address Range $0600–$067F $0680–$06FF $0700–$077F $0780–$07FF MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 107

... The MC68HC908AS60 has a special protect option which prevents program/erase access to memory locations $06F0–$06FF. This protect function is enabled by programming the EEPRTCT bit in the EENVR2 to 0. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, EEPROM-2 Go to: www.freescale.com EEPROM-2 Functional Description ...

Page 108

... Unimplemented Figure 7-1. EEPROM-2 Control Register (EECR2 Bus clock drives charge pump Internal RC oscillator drives charge pump. EEPROM-2 For More Information On This Product, Go to: www.freescale.com 7.4.1 EEPROM Programming note EERAS0 EELAT MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit 0 EEPGM 0 ...

Page 109

... This read/write bit latches the address and data buses for programming the EEPROM array. EELAT cannot be cleared if EEPGM is still set. Reset clears this bit. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product Disable EEPROM array 0 = Enable EEPROM array Table 7-3. EEPROM Program/Erase Mode Select ...

Page 110

... EERA CON2 CON1 EEPRTCT = Unimplemented Figure 7-3. EEPROM-2 Array Control Register (EEACR2) EEPROM-2 For More Information On This Product, Go to: www.freescale.com and Figure 7- EEBP3 EEBP2 EEBP1 EEBP3 EEBP2 EEBP1 EENVR2 MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit 0 EEBP0 Bit 0 EEBP0 ...

Page 111

... These read/write bits select blocks of EEPROM array from being programmed or erased. Reset loads EEBP3–EEBP0 from EENVR2 to EEACR2. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product EEPROM array is in redundant mode configuration EEPROM array is in normal mode configuration EEPROM protect disabled 0 = EEPROM protect enabled 1 = EEPROM array block is protected ...

Page 112

... The module requires a recovery time, t stop mode. Attempts to access the array during the recovery time will result in unpredictable behavior. Technical Data 112 EEPROM-2 For More Information On This Product, Go to: www.freescale.com , to stabilize after leaving EESTOP MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 113

... Introduction This section describes the central processor unit (CPU08). The M68HC08 CPU is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual, Motorola document order number CPU08RM/AD, contains a description of the CPU instruction set, addressing modes, and architecture. MC68HC908AS60 — Rev. 1.0 ...

Page 114

... Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions Enhanced binary-coded decimal (BCD) data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes Low-power stop and wait modes Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 115

... Freescale Semiconductor, Inc. 8.4 CPU Registers Figure 8-1 the memory map. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, shows the five CPU registers. CPU registers are not part Figure 8-1. CPU Registers Central Processor Unit (CPU) Go to: www ...

Page 116

... Unaffected by reset Figure 8-2. Accumulator (A) Bit Indeterminate Figure 8-3. Index Register (H:X) Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit 0 Bit ...

Page 117

... The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page zero ($0000–$00FF) frees direct address (page zero) space. For correct operation, the stack pointer must point only to RAM locations. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product ...

Page 118

... Read: Write: Reset: Technical Data 118 Bit Loaded with vector from $FFFE and $FFFF Figure 8-5. Program Counter (PC) Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit 1 0 ...

Page 119

... CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Bit ...

Page 120

... Technical Data 120 1 = Negative result 0 = Non-negative result 1 = Zero result 0 = Non-zero result 1 = Carry out of bit carry out of bit 7 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 121

... Freescale Semiconductor, Inc. 8.5 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about CPU architecture. 8.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes ...

Page 122

... MCU to normal operation if the break interrupt has been deasserted. 8.8 Instruction Set Summary Table 8-1 Technical Data 122 Section 12. Break provides a summary of the M68HC08 instruction set. Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com Module. The program MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 123

... ASRA ASRX Arithmetic Shift Right ASR opr,X ASR opr,X ASR opr,SP BCC rel Branch if Carry Bit Clear BCLR n, opr Clear Bit MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Effect on CCR Description (A) + (M) + (C) A (A) + (M) « SP ...

Page 124

... REL 20 DIR (b0) 01 DIR (b1) 03 DIR (b2) 05 DIR (b3) 07 – – – – – DIR (b4) 09 DIR (b5) 0B DIR (b6) 0D DIR (b7) 0F MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 125

... CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X Compare A with M CMP opr,X CMP ,X CMP opr,SP CMP opr,SP MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Effect on CCR Description (PC – PC (PC rel ? (Mn – – ...

Page 126

... C8 IX2 D8 0 – – – IX1 SP1 9EE8 SP2 9ED8 DIR 3C INH 4C INH 5C – – – IX1 SP1 9E6C MC68HC908AS60 — Rev. 1.0 MOTOROLA ii ...

Page 127

... LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ Move MOV #opr,opr MOV X+,opr MUL Unsigned multiply MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Effect on CCR Description Jump Address – PC (PC Push (PCL); SP (SP) – ...

Page 128

... DIR 36 dd INH 46 INH 56 – – IX1 SP1 9E66 ff – – – – – – INH 9C INH 80 – – – – – – INH 81 MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 129

... SUB ,X SUB opr,SP SUB opr,SP SWI Software Interrupt TAP Transfer A to CCR TAX Transfer TPA Transfer CCR to A MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Effect on CCR Description (A) – (M) – ( – – ...

Page 130

... Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two’s complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected 8-2. MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 131

... Freescale Semiconductor, Inc. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Central Processor Unit (CPU) Go to: www.freescale.com Central Processor Unit (CPU) Opcode Map Technical Data 131 ...

Page 132

... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Technical Data 132 Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 133

... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 137 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . 137 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 138 Reset and System Initialization 138 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Active Resets from Internal Sources ...

Page 134

... Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation CPU enable/disable timing Modular architecture expandable to 128 interrupt sources System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Figure 9-1. Figure 9-2 is MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 135

... Freescale Semiconductor, Inc. RESET PIN LOGIC RESET PIN CONTROL SIM RESET STATUS REGISTER MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, STOP/WAIT CONTROL SIM COUNTER 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER RESET CONTROL RESET INTERRUPT CONTROL AND PRIORITY DECODE Figure 9-1 ...

Page 136

... Signal from the power-on reset (POR) module to the SIM IRST Internal reset signal R/W Read/write signal System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com SBSW See Note 0 ILOP ILAD 0 LVI Reserved Description MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit ...

Page 137

... OSC1 CLOCK SELECT CGMVCLK CIRCUIT BCS PLL MONITOR MODE USER MODE CGM MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Section 10. Clock Generator Module Section 10. Clock Generator Module CGMXCLK A CGMOUT *When CGMOUT = B PTC3 Figure 9-3 ...

Page 138

... Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Low-voltage inhibit module (LVI) Illegal opcode Illegal address System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com 9.7.2 Stop Mode. 9.5 SIM Counter), but an 9.8 SIM Registers. MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 139

... The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, shows the relative timing. Table 9-2. PIN Bit Set Timing ...

Page 140

... The RST pin is driven low during the oscillator stabilization time. The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com 32 CYCLES VECTOR HIGH INTERNAL RESET MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 141

... The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address using MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product ...

Page 142

... Technical Data 142 voltage falls to the V voltage. The LVI bit in the SIM reset DD LVII . Another 64 CGMXCLK cycles later, the CPU is LVIR Section 15. Low-Voltage Inhibit (LVI) System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com DD Module. MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 143

... At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 9-9 MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) Figure 9-8 shows interrupt recovery timing ...

Page 144

... SP – – – CCR – 1 [7:0] PC – 1 [15:8] Figure 9-9. Interrupt Recovery System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com VECT H VECT L START ADDR CCR V DATA H V DATA L OPCODE OPCODE OPERAND MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 145

... Freescale Semiconductor, Inc. BREAK INTERRUPT? YES AS MANY INTERRUPTS AS EXIST ON CHIP MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, FROM RESET YES I BIT SET BIT SET? NO YES IRQ1 INTERRUPT? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION YES ...

Page 146

... NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – hardware interrupt does. Technical Data 146 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com Figure 9-11 MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 147

... The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, CLI LDA ...

Page 148

... Technical Data 148 Figure 9-12 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com shows the timing for wait mode MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 149

... An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, WAIT ADDR WAIT ADDR + 1 ...

Page 150

... Note: Previous data can be operand data or the STOP opcode, depending on the last . instruction Figure 9-15. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP + 2 STOP + 2 System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com SAME SAME NEXT OPCODE SAME SAME SP SP – – – 3 MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 151

... The code given here is an example of this. Writing 0 to the SBSW bit clears it. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Break status register, SBSR Reset status register, SRSR Break flag control register, SBFCR ...

Page 152

... See if wait mode or stop mode was exited ; by break RETURNLO is not zero, ; then just decrement low byte. ; Else deal with high byte, too. ; Point to WAIT/STOP opcode. ; Restore H register. System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 153

... PIN — External Reset Bit COP — Computer Operating Properly Reset Bit ILOP — Illegal Opcode Reset Bit ILAD — Illegal Address Reset Bit (opcode fetches only) LVI — Low-Voltage Inhibit Reset Bit MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, $FE01 Bit ...

Page 154

... Reserved Figure 9-19. SIM Break Flag Control Register (SBFCR Status bits clearable during break 0 = Status bits not clearable during break System Integration Module (SIM) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit 0 R ...

Page 155

... MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Phase-Locked Loop Circuit (PLL 159 Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . .161 Manual and Automatic PLL Bandwidth Modes . . . . . . . 161 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Special Programming Exceptions ...

Page 156

... Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation Automatic bandwidth control mode for low-jitter operation Automatic frequency lock detector CPU interrupt on entry or exit from locked condition Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 157

... An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, the constant crystal frequency clock, CGMXCLK. programmable VCO frequency clock CGMVCLK. ...

Page 158

... CONTROL AUTO ACQ PLLIE PLLF MUL7–MUL4 CGMVCLK FREQUENCY DIVIDER Figure 10-1. CGM Block Diagram Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com CGMXCLK A CGMOUT *When CGMOUT = B PTC3 MONITOR MODE USER MODE CGMINT MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 159

... The PLL can change between acquisition and tracking modes either automatically or manually. 10.4.2.1 Circuits The PLL consists of these circuits: • • • • • MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Bit Read: PLLF PLLIE PLLON Write: Reset: ...

Page 160

... The circuit determines the mode of the PLL and the lock RDV Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com . VRS . NOM , and is fed to the PLL through fed VCLK = f /N. See VDV VCLK Modes. The value of MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 161

... See MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, frequency corrections to the VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency ...

Page 162

... The LOCK bit is disabled. CPU interrupts from the CGM are disabled. Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Register 10.4.2.2 24.2 Maximum Ratings. 24.2 Maximum Ratings. 10.6.1 PLL BUSMAX Ratings), after turning on the , after entering tracking mode AL MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 163

... Choose the desired bus frequency Calculate the desired VCO frequency Using a reference frequency Calculate the VCO frequency, f MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Table 10-1. Variable Definitions Variable f Desired bus clock frequency ...

Page 164

... L. Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com , and compare f with BUS BUS 32 MHz ------------------- - = 8 MHz 4 or another f . RCLK , calculate the VCO linear NOM f VCLK ------------ - f NOM 32 MHz = 7 . The VRS f NOM f NOM . --------------- - 2 MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 165

... PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product value for N is interpreted the same as a value value for L disables the PLL and prevents its selection as the source for the base clock ...

Page 166

... S ) may not be required for all ranges of operation, S also shows the external components for the PLL: BYP F 10.10 Acquisition/Lock Time Specifications Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 10-3. Figure 10-3 shows only the for routing MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 167

... The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is connected to this pin. NOTE: To prevent noise problems, C CGMXFC pin as possible with minimum routing distances and no routing of other signals across the C MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, CGMXCLK * ...

Page 168

... DDA ) and comes directly from the crystal oscillator circuit. XCLK shows only the logical relation of CGMXCLK to OSC1 and Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com pin. DD MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 169

... CPU interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, $001C Bit 7 6 ...

Page 170

... PLL off Circuit. Reset and the STOP instruction clear 1 = CGMVCLK divided by two drives CGMOUT CGMXCLK divided by two drives CGMOUT. 10.4.3 Base Clock Selector Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com 10.4.3 Base Clock Selector 10.4.3 Circuit. MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 171

... VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0 and has no meaning. Reset clears the LOCK bit. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Selects automatic or manual (software-controlled) bandwidth control mode ...

Page 172

... PBWC. Technical Data 172 1 = Tracking mode 0 = Acquisition mode 1 = Crystal reference not active 0 = Crystal reference active 4 cycles the VCO frequency multiplier. Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 173

... Reset initializes these bits give a default multiply value of 6. NOTE: The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1). MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, $001E Bit ...

Page 174

... Circuits, 10.4.2.4 Programming the Register.) VRS7–VRS4 cannot be written when Exceptions. A value the VCO range for more information.) Reset initializes Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com PLL, and 10.4.2.5 and 10.4.2.5 Special MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 175

... CGM During Break Interrupts The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See Module. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Clock Generator Module (CGM) Go to: www.freescale.com Clock Generator Module (CGM) Low-Power Modes Section 12 ...

Page 176

... Minor errors may not even be registered. Typical PLL applications prefer to use this definition because the system requires the output frequency to be within Technical Data 176 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 177

... PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Acquisition time the time the PLL takes to reduce the error ...

Page 178

... Technical Data 178 . XCLK 10.10.3 Choosing a Filter 10.10.2 Parametric Influences on Reaction , is critical to the stability and reaction time Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com Capacitor. DDA Time, the V DDA ------------ - Fact f RDV MC68HC908AS60 — Rev. 1.0 MOTOROLA . The ...

Page 179

... Choosing the lower size may seem attractive for acquisition time improvement, but the PLL may become unstable. Also, always choose a capacitor with a tight tolerance ( 20 percent or better) and low dissipation. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, , see 24.2 Maximum Fact ...

Page 180

... Freescale Semiconductor, Inc. Clock Generator Module (CGM) Technical Data 180 Clock Generator Module (CGM) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 181

... If the LVI module and the LVI reset signal are enabled, a reset occurs when V for at least nine consecutive CPU cycles. Once an LVI reset occurs, the MCU remains in reset until V MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Resets caused by the low-voltage inhibit (LVI) module ...

Page 182

... LVISTOP bit must logic 1. Take note that by enabling the LVI in stop mode, the stop I when using a MC68HC08AS20 a register bit will have to be written. See the LVI section of the MC68HC08AS20 Advance Information (Motorola document order number MC68HC08AS20/D.) LVIRST — LVI Reset Enable Bit LVIRST enables the reset signal from the LVI module ...

Page 183

... The enable/disable logic is not necessarily identical in all parts of the AS Family. If there is any doubt, check with a local field applications representative. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Mode Stop mode recovery after 32 CGMXCLK cycles 0 = Stop mode recovery after 4096 CGMXCLK cycles 1 = COP timeout period is 8,176 CGMXCLK cycles ...

Page 184

... For More Information On This Product, Go to: www.freescale.com Bit Value Definition Name 1 Short COP timeout COPL 0 Long COP timeout 1 Short COP timeout COPL 0 Long COP timeout 1 Short COP timeout COPRS 0 Long COP timeout 1 Short COP timeout COPL 0 Long COP timeout MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 185

... Features Features of the break module include: • • • • MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Section 12. Break Module Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 187 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .187 TIM During Break Interrupts ...

Page 186

... IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB[7:0] Figure 12-1. Break Module Block Diagram Break Module For More Information On This Product, Go to: www.freescale.com BREAK CONTROL MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 187

... The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. 12.4.3 TIM During Break Interrupts A break interrupt stops the timer counter. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Bit Read: ...

Page 188

... These registers control and monitor operation of the break module: • • • Technical Data 188 Register.) Break address register high, BRKH Break address register low, BRKL Break status and control register, BSCR Break Module For More Information On This Product, Go to: www.freescale.com is present on the HI 9.8.1 SIM Break MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 189

... This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic before exiting the break routine. Reset clears the BRKA bit. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, $FE0E Bit 7 6 ...

Page 190

... Bit Bit Figure 12-4. Break Address Registers (BRKH and BRKL) Break Module For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA Bit 0 Bit 8 0 Bit 0 0 ...

Page 191

... Introduction This section describes the monitor ROM (MON). The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, Section 13. Monitor ROM (MON) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Entering Monitor Mode ...

Page 192

... Kbaud communication with host computer Execution of code in RAM or FLASH FLASH security FLASH programming shows a sample circuit used to enter monitor mode and Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com 13.4.7 Security). MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 193

... Freescale Semiconductor, Inc. 1 MC145407 + DB- Notes: Position A — Bus clock = CGMXCLK 4 or CGMVCLK Position B — Bus clock = CGMXCLK MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product MC74HC125 2 ...

Page 194

... Characteristics), is applied to either the Section 9. System Integration Module for more information on modes of operation. Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com Bus CGMOUT Frequency CGMXCLK CGMVCLK CGMOUT or ---------------------------- - ---------------------------- - ------------------------- - 2 2 CGMOUT CGMXCLK ------------------------- - and 24.2 Maximum Ratings. MC68HC908AS60 — Rev. 1.0 MOTOROLA 2 2 (see HI ...

Page 195

... BIT 0 BIT 1 BIT START BREAK BIT 0 BIT 1 BIT Figure 13-3. Sample Monitor Waveforms MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product summary of the differences between user mode and Table 13-2. Mode Differences Reset Reset COP Vector Vector High Low Enabled ...

Page 196

... Figure 13-4. Read Transaction MISSING STOP BIT TWO-STOP-BIT DELAY BEFORE ZERO ECHO Figure 13-5. Break Transaction Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com ADDR. LOW ADDR. LOW DATA RESULT Figure MC68HC908AS60 — Rev. 1.0 MOTOROLA 13-5. ...

Page 197

... None Opcode $49 Command Sequence SENT TO MONITOR WRITE WRITE ECHO MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, READ, read memory WRITE, write memory IREAD, indexed read IWRITE, indexed write READSP, read stack pointer RUN, run user program READ ADDR. HIGH ADDR ...

Page 198

... Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence SENT TO MONITOR READSP ECHO Technical Data 198 IREAD DATA DATA RESULT IWRITE DATA DATA READSP SP HIGH SP LOW Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com RESULT MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

Page 199

... The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. MC68HC908AS60 — Rev. 1.0 MOTOROLA For More Information On This Product, SENT TO MONITOR RUN ...

Page 200

... CGMXCLK CYCLES (ONE BIT TIME) FROM HOST 4 1 FROM MCU 2 = Data return delay (2 bit times Wait 1 bit time before sending next byte. Figure 13-6. Monitor Mode Entry Timing Monitor ROM (MON) For More Information On This Product, Go to: www.freescale.com MC68HC908AS60 — Rev. 1.0 MOTOROLA ...

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