PEB2086N Siemens Semiconductor Group, PEB2086N Datasheet
PEB2086N
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PEB2086N Summary of contents
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ICs for Communications ISDN SubscribernAccess Controller ISAC .-S PEB 2085 PEB 2086 User’s Manual 10.94 ...
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PEB 2085/PEB 2086 Revision History: 10.94 Previous Releases: 11.88; 3.89; 12.89; 02.95 Page Subjects (changes since last revision) The present documentation is an editorial update of the Technical Manual 12.89 Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding ...
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Table of Contents 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.4.5 C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.8.1 Message Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.1.7 Mode Register MODE Read/Write Address 22H . . . . . . . . . . . . . . . . . . . . . . . . . 204 4.1.8 Timer Register TIMR ...
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Table of Contents 4.2.15 Additional Feature Register 1 ADF1 Write Address 38H . . . . . . . . . . . . . . . . . . . 226 4.2.16 Additional Feature Register 2 ADF2 Read/Write Address ...
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Table of Contents 6.2.2 HDLC Controller Related Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction ® The PEB 2085/2086 ISAC terminals to an ISDN. The PEB 2085 combines the functions of the S-Bus Interface Circuit (SBC: PEB 2080) and the ISDN Communications Controller (ICC: PEB 2070) on one chip. The component switches B and ...
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ISDN Subscriber Access Controller ISAC 1 Features 1.1 Features of PEB 2085 Full duplex S/T interface transceiver according to CCITT I.430 Conversion of the frame structure between the S/T interface and IOM Receive timing recovery according to ...
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Pin Configurations (top view) P-DIP-40 AD4 1 AD5 2 AD6 3 AD7 4 SDAR 5 SDAX/SDS1 6 SCA/FSD/SDS2 7 RST 8 SIP/EAW SSD PEB 2085 DCL 11 FSC1 12 FSC2 ...
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Pin Definitions and Functions of PEB 2085 Pin No. Pin No. Symbol P-DIP-40 P-LCC- AD0/ AD1/ AD2/ AD3/ AD4/ AD5/ AD6/ AD7/D7 34 ...
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Pin Definitions and Functions of PEB 2085 (cont’d) Pin No. Pin No. Symbol P-DIP-40 P-LCC- SCA 7 8 FSD 7 8 SDS2 8 9 RST 12 13 FSC1 13 14 FSC2 11 12 DCL Semiconductor Group Function Input ...
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Pin Definitions and Functions of PEB 2085 (cont’d) Pin No. Pin No. Symbol P-DIP-40 P-LCC-44 – – – SDAR – – – SIP 9 ...
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Pin Definitions and Functions of PEB 2085 (cont’d) Pin No. Pin No. Symbol P-DIP-40 P-LCC- SSD SSA XTAL1 22 25 XTAL2 24 27 SR2 25 28 SR1 26 ...
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Logic Symbol of PEB 2085 + IDP0 R IOM IDP1 SDAX/SDS1 SSI SDAR SIP/EAW SLD DCL FSC1 Clock Frame CP/BCL Synchronization SCA/FSD/SDS2 FSC2 AD0...7 (D0...7) (A0... Terminating resistors only at the far ...
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ISDN Subscriber Access Controller ISAC 1.2 Features of PEB 2086 Enhanced version of the PEB 2085 with following new features: Symmetrical S/T-interface receiver B-channel mapping on SSI-interface Demultiplexed microprocessor interface in ® IOM -1 mode Multiframe synchronization Type PEB 2086H ...
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Pin Configuration (top view) P-MQFP-64 SDAR SDAX/SDS1 52 SCA/FSD/SDS2 53 RST SIP/EAW SSD DCL 58 FSC1 59 FSC2 P-LCC-44 SDAX/SDS1 ...
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Pin Definitions and Functions of PEB 2086 Pin No. Pin No. Symbol P-MQFP-64 P-LCC- AD0/ AD1/ AD2/ AD3/ AD4/ AD5/ AD6/ AD7/D7 27 ...
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Pin Definitions and Functions of PEB 2086 (cont’d) Pin No. Pin No. Symbol P-MQFP-64 P-LCC- SCA 53 8 FSD 53 8 SDS2 54 9 RST 59 13 FSC1 60 14 FSC2 Semiconductor Group Input (I) Function Output (O) ...
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Pin Definitions and Functions of PEB 2086 (cont’d) Pin No. Pin No. Symbol P-MQFP-64 P-LCC- DCL SDAR ...
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Pin Definitions and Functions of PEB 2086 (cont’d) Pin No. Pin No. Symbol P-MQFP-64 P-LCC- BCL 13 XTAL1 ...
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Logic Symbol of PEB 2086 + IDP0 R IOM IDP1 SDAX/SDS1 SSI SDAR SIP/EAW SLD DCL FSC1 Clock Frame CP/BCL Synchronization SCA/FSD/SDS2 FSC2 AD0...7 (D0...7) (A0... Terminating resistors only at the far ...
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Functional Block Diagram SSI SSI SLD SLD Figure 3 Block Diagram of the ISAC Semiconductor Group R IOM B-Channel Switching R IOM Interface D-Channel Handling FIFO P Interface P ® Features ISDN Basic Buffer Access Layer-1 Functions ...
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System Integration 1.4.1 ISDN Applications The reference model for the ISDN basic access according to CCITT I series recommendations consists of – an exchange and trunk line termination in the central office (ET, LT) – a remote network termination ...
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S TE(1) TE(8) TE(1) TE(1) TE(8) Figure 5 ® Applications of the ISAC Terminal Applications The concept of the ISDN basic access is based on two circuit-switched 64 kbit/s B channels and a message oriented 16 kbit/s D channel for ...
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D, C/I R ISAC -S ICC PEB 2085 PEB 2070 PEB 2086 µ C Data Module Figure 6 ® Example of an ISDN -S Voice/Data Terminal Up to eight D channel components (ICC: ISDN Communication Controller PEB 2070) may be ...
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Line Card Applications An example of the use of the ISAC ISDN PABX line card (decentralized architecture) is shown in figure 8. The ISAC-S is connected to an Extended PCM Interface Controller (EPIC PEB 2055) via an IOM ...
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PSB 2165 ARCOFI -SP LCD Control LCD Display Figure 7 Basic ISDN Feature Telephone PEB 2085 / 86 S-Bus ISAC -S PEB 2085 / 86 S-Bus ISAC Figure 8 ISDN PABX Line Card Implementation Semiconductor Group R IOM -2 PEB ...
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INT(INTX 80C51 ALE (80C188) (PSCX) A15...A8 AD7...AD0 Figure 9 ® Connecting the ISAC -S to Siemens/Intel Microcontroller Semiconductor Group + 5 V INT ALE ALE CS AD7...AD0 AD0 - AD7 Latch Common Bus A15-A0, ...
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Functional Description 2.1 General Functions and Device Architecture The functional block diagram of the ISAC-S is shown in figure 10. The left-hand side of the diagram contains the layer-1 functions, according to CCITT I series recommendations: – S-bus transmitter ...
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The right-hand side consists of: – the serial interface logic for the IOM and the SLD and SSI interfaces, with B-channel switching capabilities – the logic necessary to handle the D-channel messages (layer 2). The latter consists of an HDLC ...
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Table 1 Operating Modes and Functions of Mode Specific Pins of the ISAC ® the IOM -1 Mode Pin No P-DIP-40 (PEB 2085 only) Pin No P-LCC-44 Pin No P-MQFP-64 (PEB ...
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CON Connected to the S bus. Only available on PEB 2085. CON = 0: Disconnected from the S bus; an activation of the S/T line initiated by the TE/LT-T is not possible: Info 1 cannot be transmitted. An activation initiated ...
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The different operating modes in relation to the timing recovery are illustrated in figure 11. TYPE 1 SLD TYPE 2 SSI CLOCK SLAVE PEB 2085/86 FSC2 FSD S CLOCK MASTER PEB 2050/52/55 CLK 4096 kHz System Int. CLOCK SLAVE PEB ...
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IOM -2 Interface Mode (ADF2:IMS=1) In this mode the IOM interface has the enhanced functionality of IOM-2. B-channel interfacing is performed directly via the IOM-2 interface and the auxiliary serial SSI and SLD interfaces are not longer available ...
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SCZ Send continuous binary zeros (96 kHz) SSZ Send single binary zeros (2 kHz) CON Connected to the S bus. CON = 0: Disconnected from S bus; an activation of the S/T line initiated by the TE/LT-T is not possible: ...
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The different operating modes in relation to the timing recovery are illustrated in figure 12. TE Mode, Terminal Timing Mode V/D Module LT-S Mode, Non-Terminal Timing Mode CLOCK SLAVE PEB 2085/86 FSC2 S Figure 12a Operating Modes of ISAC Semiconductor ...
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LT-T Mode, Non-Terminal Timing Mode CLOCK MASTER PEB 2055 System Int. NT Mode CLOCK SLAVE PEB 2085/86 FSC2 S Figure 12b Operating Modes of ISAC Semiconductor Group 2048 kbit/s 2048 kbit/s 4096 kHz 8 kHz 256 kbit/s IDP0 256 kbit/s ...
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IOM -1 Mode Functions ® 2.3.1 IOM -1 Frame Structure / Timing Modes This interface consists of one data line per direction (IOM Data Ports 0 and 1:IDP0, 1). Three additional signals define the data clock (DCL) and ...
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Timing Mode 0 (SPM = 0) In timing mode 0 the SLD operates in master mode and the SSI (Serial Port A) is operational; pin SCA/FSD delivers a 128-kHz clock (SCA). The IOM, SLD and SSI interface frame begin is ...
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Timing Mode 1 (SPM = 1) Timing mode 1 (SPM = 1) is only meaningful in exchange applications (LT-S, LT-T) when the SLD is used. In timing mode 1 the SLD operates in slave mode and the SSI (Serial Port ...
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IOM -1 Interface Connections In IOM-1 interface mode – pin IDP0 carries B channel, MONITOR, D and C/I data from layer-1 to layer-2 – pin IDP1 carries B channel, MONITOR, D and C/I data from layer-2 to layer-1. ...
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SLD Interface The standard SLD interface is a three-wire interface with a 512-kHz clock (DCL), an 8-kHz frame direction signal (TE mode: FSC1/2 output; LT-S/LT-T modes: FSC1 sync input), and a serial ping-pong data lead (SIP) with an effective ...
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Digital exchange applications (LT-S/LT- full duplex time-multiplexed connection to convey the B channels between the S/T interface and a Peripheral Board Controller (e.g. PBC PEB 2050 or PIC PEB 2052), which performs time-slot assignment on the PCM ...
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SSI (Serial Port A) The SSI (Serial Synchronous Interface) is available only in timing mode 0 (SPCR:SPM=0). The serial port SSI serves as a full duplex connection to B-channel sources/destinations in terminal equipment with a data rate of 128 ...
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B-Channel Switching The ISAC-S contains two serial interfaces, SLD and SSI, which can serve as interfaces to B channel sources/destinations. Both channels B1 and B2 can be switched independently of one another to the IOM interface and to the ...
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SSI ) * FF H SLD µP SSI Switching = µP Access = B-Channel Route FF H SSI ) * FF H SLD P µ R IOM ) * Undefines Value Figure 21 B-Channel ...
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Table 3 P Access to B Channels (IOM C R CxC1 CxC0 Read 0 0 SLD 0 1 SLD 1 0 SSI 1 1 IOM Note for channel for channel 2 The Synchronous Transfer ...
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C C1 01, SLD-IOM x x SIP FSC BVS IDP1 B1 SIP B1 IDP0 B1 Semiconductor Group ® Connection CxR SSI BxCR µ SIN(ST0) P µ Access 50 Functional Description IDP1 ...
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C C1 10, SSI-IOM SDAR SDAX FSC SDAR IDP1 B1 IDP0 B1 SDAX Semiconductor Group ® Connection (PEB 2085) CxR SSI BxCR µ µ P Access R IOM B1/2 SSI ...
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C C1 10, SSI-IOM SDAR SDAX FSC SDAR B1 IDP1 IDP0 B1 SDAX Semiconductor Group ® Connection (PEB 2086) CxR SSI BxCR µ µ P Access R IOM B1/2 SSI B2 SIN(ST0) ...
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C C1 11, IOM ® FSC IDP1 B1 IDP0 B1 Semiconductor Group Loop CxR µ µ Access SIN(ST0) 53 Functional Description IDP1 R IOM IDP0 ITS00867 ...
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MONITOR Channel Handling The MONITOR channel in IOM-1 mode is used for the exchange of control information between the ISDN Communication Controller ICC (PEB 2070) and layer-1 devices like the ISDN Burst Controller IBC (PEB 2095) or the ISDN ...
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Command/Indicate (C/I) Channel Handling The C/I channel conveys the commands and indications between the layer-1 and layer-2 parts of the ISAC-S. This channel is available in all timing modes. Beside being accessed by the internal layer-2 part, it can ...
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D-Channel Telemetry/ Packet Communication B-Channel Voice/Data Communication with D-Channel Signaling E-Channel IVD LAN Application B-Channel Voice/Data Communication with D-Channel Signaling Figure 24 ® Applications of IOM Bus Configuration Semiconductor Group R µP IOM -2 ICC (7) ICC (2) DCL ICC ...
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An access request to the TIC bus may either be generated by software ( P access to the C/I channel the ISAC-S itself (transmission of an HDLC frame). A software access request to the bus is effected by ...
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IOM -2 Mode Functions ® 2.4.1 IOM -2 Frame Structure / Timing Modes The IOM generalization and enhancement of the IOM-1. While the basic frame structure is very similar, IOM-2 offers further capacity for the transfer ...
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Thus the data rate per subscriber connection (corresponding to one channel) is 256 kbit/s, whereas the bit rate is 2048 kbit/s. The IOM-2 interface signals are: IDP0 2048 kbit/s DCLK : 4096 kHz input FSC1/ kHz ...
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TE Timing Mode (SPM=0) The frame is composed of three channels (figure 29): * Channel 0 contains 144 kbit/s (for 2B+D) plus MONITOR and Command/Indication channels for the layer-1 device. * Channel 1 contains two 64-kbit/s intercommunication channels plus MONITOR ...
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IOM -2 Interface Connections Output Driver Selection The type of the IOM output is selectable via bit ODS (ADF2 register). Thus when inactive (not transmitting) IDP0, 1 are either high impedance (ODS=1) or open drain "1" (ODS=0). Normally ...
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Non-Terminal Mode (SPCR:SPM=1) Outside the programmed 4-byte subscriber channel (bits CSEL2-0, ADF1 register), both IDP1 and IDP0 are inactive. Inside the programmed 4-byte subscriber channel (see figure 30): – IDP1 carries the 2B+D channels as output towards the subscriber (i.e. ...
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S/T Interface IDP0 Layer 1 (SBC) IDP1 IDP0 B1 S/T IDP1 B1 R IOM Figure 31 ® IOM Data Ports Non-Terminal Mode (SPCR:SPM=1) with Reversed ® IOM Direction (SQXR:IDC=1) Semiconductor Group R ISAC -S B1/B2 IDP0 IDP1 ...
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Terminal Mode (SPM=0) In this case the IOM has the 12-byte frame structure consisting of channels 0, 1 and 2 (see figure 29): – IDP0 carries the 2B+D channels from the S/T interface, and the MONITOR 0 and C/I 0 ...
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X1 and FSC2 are driven between the first and the second falling edge of the DCL signal. They are always not connected between the first rising and the first falling edge as well as the second falling and the first ...
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ISAC -S S/T Interface IDP0 Layer 1 (SBC) IDP1 R ISAC -S in Master Mode (IDC = 0) Master Figure 33a ® IOM Data Ports Terminal Mode (SPCR:SPM=0) Semiconductor Group R IOM -2 Interface (DD) IDP0 (DU) ...
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CH0 IPD0 B1 B2 MON0 (DD) R S/T IOM -2 Layer 1 IPD1 B1 B2 MON0 (DU) R IOM -2 S/T Layer 2 CH0 IPD0 B1 B2 MON0 (DD) R S/T IOM -2 Layer 1 IPD1 B1 B2 MON0 (DU) ...
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P Access to B and IC Channels In IOM-2 terminal mode (TE mode, SPCR:SPM=0) the microprocessor can access the B and IC (intercommunication) channels at the IOM-2 interface by reading the B1CR/B2CR or by reading and writing the C1R/C2R ...
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S/T Interface Layer-1 Functions Figure 34 Principle of B/IC Channel Access in IOM (a) SPCR:C C1 monitoring, IC monitoring (SQXR:IDC=0) S/T Interface Layer-1 Functions Figure 35 Access to B and IC Channels in IOM Semiconductor ...
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SPCR:C C1 monitoring, IC looping (SQXR:IDC=0) S/T Interface Layer-1 Functions (c) SPCR:C C1 access from/to S/T transmission of constant value to S/T S/T Interface Layer-1 Functions Semiconductor Group Functional ...
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SPCR:C C1 looping from/to S/T transmission of variable pattern to S/T S/T Interface Layer-1 Functions 2.4.4 MONITOR Channel Handling In IOM-2 mode, the MONITOR channel protocol is a handshake protocol used for high speed ...
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R IOM -2 Data Communication (MONITOR1) V/D - Module R ITAC PSB 2110 C µ Figure 36 Examples of MONITOR Channel Applications in IOM The MONITOR channel operates on an asynchronous basis. While data transfers on the bus take place ...
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P µ MXE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 MDA Int. MOX = DATA2 MDA Int. MXC = 0 MAC = 0 Figure 37 MONITOR Channel Protocol (IOM Semiconductor Group ...
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Before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by a "0" in the MONITOR Channel Active MAC status bit. After having written the ...
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It can be accessed by an external layer-2 device e.g. to control the layer-1 activation/deactivation procedures. C/I0 channel access may be arbitrated via the TIC bus access protocol in the IOM-2 terminal timing mode (SPCR:SPM=0). In this case the ...
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D-Channel Telemetry/ Packet Communication B-Channel Voice/Data Communication with D-Channel Signaling E-Channel IVD LAN Application B-Channel Voice/Data Communication with D-Channel Signaling Figure 38 Applications of TIC Bus in IOM 2.4.6 TIC Bus Access In IOM-2 interface mode the TIC bus capability ...
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ISAC-S itself (transmission of an HDLC frame). A software access request to the bus is effected by setting the BAC bit (CIX0 register) to "1". In the case of an access request, the ISAC-S checks the ...
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B1 B2 MON0 Figure 40 Structure of Last Octet of Ch2 on IDP0 (DD) The stop/go bit is available to other layer-2 devices connected to the IOM to determine if they can access the S/T bus D channel. Semiconductor Group ...
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Layer-1 Functions for the S/T Interface The common functions in all operating modes are: – line transceiver functions for the S/T interface according to the electrical specifications of CCITT I.430; – conversion of the frame structure between IOM and ...
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R TR ISAC - ISAC -S LT-T The maximum line attenuation toleratet by the ISAC 1) TE1 _ < < ISAC -S TE1 TE8 Figure 41 Wiring Configurations in User ...
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S/T Interface According to CCITT recommendation I.430 pseudo-ternary encoding with 100% pulse width is used on the S/T interface. A logical "1" corresponds to a neutral level (no current), whereas logical "0" ’s are encoded as alternating positive and ...
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Analog Functions For both receive and transmit direction, a 2:1 transformer is used to connect the ISAC-S transceiver to the 4 wire S/T interface. The connections are shown in figure 44 SX1 V DD SX2 10 ...
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R ISAC -S PEB 2085 2 IOM -S PEB 2.5 V Figure 45 Equivalent Internal Circuits of Receiver and Transmitter Stages The transmitter of the PEB 2086 ISAC-S is identical to that ...
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S/T Interface Circuitry 2.5.3.1 S/T Interface Pre-Filter (PEB 2085 only) In some applications it may be desirable to improve the signal-to-noise ratio of the received S/T interface signal by filtering out undesirable frequency (usually high frequency) components. This may ...
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Table 5 TEM/PFS Function Table TEM PFS This delay compensation might be necessary in order to comply with the "total phase deviation input to output" requirement of CCITT recommendation I.430 which specifies ...
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Protection Circuit for Transmitter SX1 SX2 Figure 47 External Circuitry for Transmitters Figure 47 illustrates the secondary protection circuit recommended for the transmitter. An ideal protection circuit should limit the voltage at the SX pins from – 0 ...
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Protection Circuit for Unsymmetrical Receivers (PEB 2085) For unsymmetrical S -receivers (PEB 2085) a 2.5 V reference voltage is supplied at pin SR1 0 (output). The input signal at pin SR2 is referred to the level at pin SR1. In ...
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Protection Circuit for Symmetrical Receivers Figure 49 illustrates the external circuitry used in combination with a symmetrical receiver (PEB 2086 ISAC-S) Protection of symmetrical receivers is rather comfortable. SR2 SR1 Figure 49 External Circuitry for Symmetrical Receivers Between each receive ...
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Receive Signal Oversampling In order to additionally reduce the bit error rate in severe conditions, the ISAC-S performs oversampling of the received signal and uses majority decision logic. (Note: this feature is implemented in TE and LT-T modes only). ...
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Adaptive Receiver Characteristics The integrated receiver uses an adaptively switched threshold detector. The detector controls the switching of the receiver between two sensitivity levels. The hysteresis characteristics of the receiver are shown in figure 51 SR2 ...
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Level Detection Power Down (TE mode) In power down state, (see chapter 3.3.1) only an analog level detector is active. All clocks, including the IOM interface, are stopped. The data lines are "high", whereas the clocks are "low". An ...
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MP: Receive clock for passive bus configuration PP: Receive clock for point-to-point configuration Figure 52 Clock System of the ISAC TE and LT-T In TE/LT-T applications, the transmit and receive bit clocks are derived, with the help of the DPLL, ...
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Figure 53 Clock System of the ISAC Semiconductor Group TE Mode PLL CP LT-T Mode Slip Detector PLL CP ® and LT-T Modes 93 Functional Description DCL FSC ITS02363 FSC "NT2" Clock Generator DCL (PLL) Reference Clock ...
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Activation/Deactivation An incorporated finite state machine controls ISDN layer-1 activation/deactivation according to CCITT (see chapter 3.4). Loss of Synchronization / Resynchronization (TE mode) The following section describes the behaviour of the PEB 2085/86 in respect to the CTS test ...
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FAinfB_1fr This test uses a frame which has no framing and balancing bit. Info 4 Info 3 Device Settings PEB 2085 V2.3 none PEB 2086 V1.1 none 2.5.6.3 FAinfD_1fr This test uses a frame which remains at binary "1" ...
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FAinfA_kfr This test uses a number of IX_96 kHz frames to check the loss of synchronization. Info 4 Info 3 Device Settings PEB 2085 V2 PEB 2086 V1 2.5.6.5 FAinfB_kfr This test uses ...
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FAinfD_kfr This test uses a number of IX_I4voil16 frames to check the loss of synchronization. The first Info 3 frame with the F -bit set to one looks like an i3_SFAL frame but correct info 3 ...
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Device Settings PEB 2085 V2 PEB 2086 V1 2.5.7 D-Channel Access Depending on the application, the D channel is either switched transparently (no collision resolution) from the IOM to the S/T interface ...
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MODE:DIM2-0 to 001 or 011. Selection of the Priority Class The priority class (priority 8 or priority 10) is selected by transferring the appropriate activation command via the Command/Indicate (C/I) channel of the IOM interface to the layer-1 controller. If ...
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S- and Q-Channel Access Access to the received/transmitted channel is provided via registers. As specified by CCITT I.430, the Q bit is transmitted from the position normally occupied by the auxiliary framing ...
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LT-S/NT mode: – Generation of the F and M bit patterns according to table 7. A – The four bits received in the F SQR1 to SQR4 in the SQRR register. A change in any of the received bits (SQR1 ...
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S-Frame and Multiframe Synchronization (PEB 2086 only) The PEB 2086 offers the capability to control the start of the S-frame as well as the start of the multiframe from external signals. Applications which require synchronization between different S-interfaces are ...
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If X2 become "0" again, the multiframe counter counts 20 frames and begins again autonomously kept "1", the multiframe counter is permanently reset and the M-bit stays at "1" becomes "0" for only one S-frame, ...
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Terminal Specific Functions Watchdog and External Awake In addition to the ISAC-S standard functions supporting the ISDN basic access, the ISAC-S contains optional functions, useful in various terminal configurations. The terminal specific functions are enabled by setting bit TSF ...
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A reset signal is generated as a result of the expiration of the watchdog timer (indicated by the WOV interrupt status). Note that the watchdog timer is not running when the ISAC the power-down state (IOM not ...
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Test Functions The ISAC-S provides several test and diagnostic functions which can be grouped as follows: digital loop via TLP (Test Loop, SPCR register) command bit: IDP1 is internally connected with IDP0, output from layer 1 (S/T) on IDP0 ...
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Layer-2 Functions for the ISDN Basic Access LAPD, layer 2 of the D-channel protocol (CCITT I.441) includes functions for: – Provision of one or more data link connections channel (multiple LAP). Discrimination between the data link ...
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For the support of LAPD the ISAC-S contains an HDLC transceiver which is responsible for flag generation/recognition, bit stuffing mechanism, CRC check and address recognition. A powerful FIFO structure with two 64-byte pools for transmit and receive directions and an ...
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Only the logical connection identified through the address combination SAP1, TEI1 will be processed in the auto mode, all others are handled as in the non-auto mode. The logical connection handled in the auto mode must have a window size ...
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S commands – flow control with RR/RNR – response generation – recognition of protocol errors – transmission of S commands acknowledgement is not received – continuous status query of remote station after RNR has been ...
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Figure 57 Contents of RFIFO (short message) Semiconductor Group RFIFO Interrupts in Wait Line 0 Receive Message 1 < bytes Receive Message 2 < bytes) 31 111 Functional Description RME RME ITS01502 ...
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Flag SAP1, SAP2 Auto Mode - (U and Frames SAP1, SAP2 Non-Auto Mode Transparent Mode 1 Transparent Mode 2 SAP1, SAP2 Transparent Mode 3 Description of Symbols: Figure 58 Receive Data Flow Note 1 Only if a 2-byte ...
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When 32 bytes of a message longer than that are stored in the RFIFO, the CPU is prompted to read out the data by an RPF interrupt. The CPU must handle this interrupt before more than 32 additional bytes are ...
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Information about the received frame is available for the P when a RME interrupt is generated, as shown in table 8. Table 8 Receive Information at RME Interrupt Information First byte after flag (SAPI of LAPD address field) Control field ...
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CPU can write a data block bytes to the transmit FIFO. After this, data transmission can be initiated by command. Two different frames types can be transmitted: – Transparent frame (command: XTF), or – ...
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In the case byte address, the ISAC-S takes either the XAD 1 or XAD 2 register to differentiate between command or response frame (as defined by X.25 LAP B). The control field is also generated by the ...
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The termination of the transmission operation may be indicated either with: – XPR interrupt positive acknowledgement has been received, – XMR interrupt negative acknowledgement has been received, i.e. the transmitted message must be repeated (XMR = ...
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Legend of the Auto-Mode-Documentation a. Symbols within a path There are 3 symbols within a path a.1. In the auto mode the device processes all subsequent state transitions branchings etc the next symbol. a.2. In the auto ...
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Symbols at a path There is 1 symbol at a path b.1. marks the beginning of a path, for which a.3 applies. c. Symbols at an internal or external message box. There are 2 symbols at a message box. ...
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Text attached at the side of boxes The text describes an Interrupt associated with the contents of the e.1. Text box. The interrupt is always associated with the box contents, if the Box interrupt name is not followed by ...
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Additional General Considerations when Using the Auto Mode a) Switching from auto mode to non-auto mode. As mentioned in the introduction the auto mode is only applicable in the states 7 and 8 of the LAPD. Therefore whenever these ...
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The occurence of an XMR interrupt in auto mode after an XIF command indicates that the I-frame sent was either rejected by the Peer Entity or that a collision occured on the S-interface. In both cases the I-frame has to ...
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Q921: Invalid Frames and Frame Abortion Paragraphs 2.9 and 2.10 of the Q.921 deal with Invalid Frames and Frame Abortion. In the following the original text is given. Q.921 § 2.9: Invalid Frames An invalid frame is a frame which: ...
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The reaction to § 2.10 has been already discussed under a) Necessary Software Actions The software should read the Register RSTA after a RME-interrupt. After having read RAB = 1 ...
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For a better understanding we insert the text of § 3.6.1, which is referred to in § 5.8.5 and which reads: § 3.6.1 Commands and responses The following commands and responses are used by either the user or the network ...
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Table 9 Q.921 (Table 5) Application Format Information Transfer Supervisory Unacknowledged and Multiple- Frame acknowledged Information Transfer Unnumbered Connection Management *Note: Use of the XID frame other than for parameter negotiation procedures (see § 5.4) is for further study. The ...
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Reaction of the ISAC-S In the following various possible actions to be taken according to § 5.8.5 parts a) through c) are discussed separately. a) There are different types of undefined frames: 1) I-frame which is not command 2) S-frame ...
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The processor should read RBCH, RBCL after each RPF, RME interrupt. If after an RPF or RME the byte count exceeds 528 then CMDR:RRES should be written (abort of frame). The frame was invalid in this case but it was ...
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Further Criteria Leading to a Re-Establishment Q.921 § 5.7.1: Criteria for Re-Establishment § 5.7.1 Criteria for re-establishment The criteria for re-establishing the multiple frame mode of operation are defined in this section by the following conditions: a) The receipt while ...
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Further Possible Error Conditions Appendix II of Q.921: Further Possible Error Conditions Table 10 Q.921 Management Entity Actions for MDL Error Indications Error Type Error Error Code Condition A Supervisory ( DM UA(F = ...
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Table 10 Q.921 Management Entity Actions for MDL Error Indications (cont’d) Error Type Error Error Code Condition J N(R) Error K Receipt of FRMR response L Receipt of non- implemented frame Other M Receipt of I-field (see Note 2) not ...
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I-frame CMDR:RMC Cont. -> Layer 3 Figure 61 Interrupt Service Routine after RME Semiconductor Group RME & /TIN & /PCE = 1 RSTA:RAB CRC RSTA:RDO ISTA:RFO ...
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TIN or PCE Re-establishment of the link Figure 62 Interrupt Service Routines after RPF (top), TIN or PCE (middle left), RSC (middle right), and XDU or RFO (bottom) Semiconductor Group RPF & /TIN & /PCE Y RBCL > 528 RBCH, ...
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XPR & /TIN & /PCE Has a frame been sent since last CMDR:XRES ? Y A frame is currently transmitted ? N Last frame written to XFIFO was an I-frame ? N SRC * ? Y ACK1 & ACK2 * ...
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Figure 64 Interrupt Service Routine after XMR Semiconductor Group XMR & /TIN & /PCE N SRC ? Y Re-transmit the - frame sent last 135 Functional Description Re-transmit the frame sent last ITD05894 ...
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MULTIPLE FRAME ESTABLISHED DL ESTABLISH RELEASE REQUEST REQUEST DISCARD DISCARD I QUEUE I QUEUE ESTABLISH DATA LINK SET TX DISC LAYER 3 XFIFO INITIATED CMDR XTF MODE NAM STOP T203 5 RESTART T200 ...
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MULTIPLE FRAME ESTABLISHED TIMER T200 EXPIRY YES PEER BUSY GET LAST TRANSMIT TRANSMITTED ENQUIRY I FRAME V( COMMAND V( CLEAR ACKNOWLEDGE PENDING START ...
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STORE STAR2: WFA Figure 65c Semiconductor Group 7 MULTIPLE FRAME ESTABLISHED RME RME SABME DISC RCHR: RCHR: DISCARD F=P I QUEUE XFIFO CMDR XTF CLEAR TX UA EXCEPTION XFIFO CONDITIONS CMDR XTF MDL-ERROR DL-RELEASE INDICATION ...
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MULTIPLE FRAME ESTABLISHED RME DM RHCR YES RHCR NO MDL-ERROR MDL-ERROR INDICATION INDICATION (E) (B) 7 ESTABLISH MULTIPLE DATA LINK FRAME ESTABLISHED CLEAR LAYER 3 INITIATED MODE NAM 5 AWAITING ESTABLISHM. Note: These signals are generated ...
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MULTIPLE FRAME ESTABLISHED RR RSC / CLEAR PEER RECEIVER BUSY STAR:RRNR NO COMMAND YES YES ENQUIRY RESPONSE STAR2:SDET Figure 65f Figure 65e Semiconductor Group YES YES MDL-ERROR- INDICATION ...
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NO < < V(A) N(R) V(S) YES NO N(R) = V(S) YES XPR / V(A) = N(R) STAR2:WFA STOP T200 START T203 7 MULTIPLE FRAME ESTABLISHED Figure 65f Semiconductor Group N(R) ERROR RECOVERY MODE NAM 5 YES ...
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MULTIPLE FRAME ESTABLISHED RNR RSC / SET PEER RECEIVER BUSY STAR:RRNR NO COMMAND YES YES ENQUIRY RESPONSE STAR2:SDET XPR / STAR2:WFA Figure 65g Semiconductor Group YES MDL-ERROR- INDICATION (A) NO < ...
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MULTIPLE FRAME ESTABLISHED I COMMAND OWN YES RECEIVER BUSY NO NO N(S) = V(R) YES V( CLEAR REJECT EXCEPTION RME DL-DATA INDICATION RFIFO, RHCR YES YES ACKNOWLEDGE PENDING NO ACKNOWLEDGE PENDING ...
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NO < < < < _ V(A) N(R) V(S) YES PEER NO RECEIVER BUSY YES XPR / V(A) = N(R) STAR2:WFA Figure 65i Semiconductor Group NO N(R) = V(S) YES XPR / V(A) = N(R) N(R) ...
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Figure 65j Semiconductor Group Functional Description 7 MULTIPLE FRAME ESTABLISHED ACKNOWLEDGE PENDING NO ACKNOWLEDGE PENDING YES CLEAR ACKNOWLEDGE PENDING STAR2:SDET 7 MULTIPLE FRAME ESTABLISHED ITD02374 145 ...
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TIMER RECOVERY DL ESTABLISH REQUEST DISCARD I QUEUE ESTABLISH DATA LINK SET LAYER 3 INITIATED MODE NAM 5 AWAITING ESTABLISHM. Figure 66a Semiconductor Group DL DL-DATA ESTABLISH REQUEST REQUEST DISCARD PUT IN I QUEUE I QUEUE I FRAME RC ...
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TIMER RECOVERY TIMER T200 EXPIRY RC = N200 NO YES V(S) = V(A) NO YES TRANSMIT TRANSMITTED ENQUIRY ACKNOWLEDGE TIMER RECOVERY Figure 66b Semiconductor Group YES TIN MDL-ERROR INDICATION(I) ESTABLISH DATA LINK PEER ...
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STORE STAR2: WFA Figure 66c Semiconductor Group 8 TIMER RECOVERY RME RME SABME DISC RHCR: RHCR: DISCARD QUEUE XFIFO CMDR XTF CLEAR TX UA EXCEPTION XFIFO CONDITIONS CMDR XTF MDL-ERROR DL-RELEASE ...
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TIMER RECOVERY RME DM RHCR YES RHCR NO MDL-ERROR MDL-ERROR INDICATION INDICATION (E) (B) ESTABLISH DATA LINK CLEAR LAYER 3 INITIATED MODE NAM 5 AWAITING ESTABLISHM. Note: These signals are generated outside of this SDL representation, ...
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TIMER RECOVERY RR RSC / CLEAR PEER RECEIVER BUSY STAR:RRNR NO COMMAND YES YES ENQUIRY RESPONSE STAR2:SDET NO < < < < V(A) N(R) V(S) YES XPR / V(A) = N(R) ...
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TIMER RECOVERY RNR BUSY STAR:RRNR COMMAND YES YES ENQUIRY RESPONSE STAR2:SDET NO < _ < _ V(A) N(R) V(S) YES XPR / V(A) = N(R) STAR2:WFA 8 TIMER RECOVERY Figure 66f Semiconductor Group RSC / NO ...
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TIMER RECOVERY I COMMAND OWN YES RECEIVER BUSY NO NO N(S) = V(R) YES V( CLEAR REJECT EXCEPTION RME DL-DATA INDICATION RFIFO, RHCR YES YES ACKNOWLEDGE PENDING NO ACKNOWLEDGE PENDING NOTE ...
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V(A) N(R) V(A) = N(R) TIMER RECOVERY Figure 66h Figure 66i Semiconductor Group 4 NO < _ V(S) YES XPR / RECOVERY STAR2:WFA MODE NAM 8 ESTABLISHM. 8 TIMER RECOVERY ACKNOWLEDGE PENDING NO ACKNOWLEDGE PENDING YES CLEAR ACKNOWLEDGE ...
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RELEVANT STATES (NOTE 1) DL UNIT DATA REQUEST PLACE IN UI QUEUE UI FRAME QUEUED UP NOTE 2 Note 1: The relevant states are as follows 4 TEI-assigned 5 Awaiting-establishement 6 Awaiting-release 7 Multiple-frame-established 8 Timer-recovery Note 2: The data ...
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RELEVANT STATES (NOTE 1) CONTROL FIELD ERROR (W) Note 1: The relevant states are as follows 7 Multiple-frame-established 8 Timer-recovery Figure 67b Semiconductor Group INFO NOT INCORRECT PERMITTED LENGHT (X) (X) PCE / MDL-ERROR INDICATION (L,M,N,O) ESTABLISH DATA LINK CLEAR ...
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RELEVANT STATES (NOTE 1) CONTROL FIELD ERROR (W) Note 1: The relevant states are as follows: 4 TEI-assigned 5 Awaiting-establishment 6 Awaiting-release Note 2: The data link layer returns to the state it was in prior to the events shown ...
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N(R) ERROR RECOVERY MDL-ERROR INDICATION(J) PCE ESTABLISH DATA LINK CLEAR LAYER 3 INITIATED Figure 67d Semiconductor Group CLEAR ESTABLISH EXCEPTION DATA LINK CONDITIONS CMDR:RHR,XRES CLEAR EXCEPTION CLEAR PEER CONDITION RECEIVER CMDR:RHR,XRES BUSY MODE: NAM CLEAR REJECT P ...
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ENQUIRY RESPONSE OWN RECEIVER BUSY RESPONSE STAR2:SDET CLEAR ACKNOWLEDGE PENDING Note: The generation of the correct number of signals in order to cause the required retransmission of I frames does not alter their sequence ...
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Operational Description The ISAC-S, designed for the connection of subscribers to an ISDN using a standard S/T interface, has the following applications, corresponding to the operating modes explained in chapter 2: Terminal Equipment TE1, TA e.g. ISDN feature telephone, ...
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Microprocessor Interface Operation The ISAC-S is programmed via an 8-bit parallel microcontroller interface. Easy and fast microprocessor access is provided by 8-bit address decoding on the chip. Depending on the chip package (P-DIP-40, P-LCC-44 or M-QFP-64) either one or ...
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The microprocessor interface signals are summarized in table 11. Table 11 ® P Interface of the ISAC -S Pin No. Pin No. Pin No. P-DIP-40 P-LCC-44 P-MQFP- ...
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Interrupt Structure and Logic Since the ISAC-S provides only one interrupt request output (INT), the cause of an interrupt is determined by the microprocessor by reading the Interrupt Status Register ISTA. In this register, seven interrupt sources can be ...
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A read of the ISTA register clears all bits except EXI and CISQ. CISQ is cleared by reading CIR0. A read of EXIR clears the EXI bit in ISTA as well as the EXIR register. When all bits in ISTA ...
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MOS interrupt logic The MOS interrupt logic shown in figure 68 is valid only in the case of IOM-2 interface mode. Further, only one MONITOR channel is handled in the case of IOM-2 non-terminal timing mo- des. In this case, ...
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INT A status bit is set. This causes an interrupt. The microprocessor starts its service routine and reads the status registers. A new status bit is set before the first status bit has been read. The first status bit is ...
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DCL INT RD Figure 71 Timing of INT Pin The INT line is switched with the rising edge of DCL pending interrupts are internally stored, a reading of ISTA respectively EXIR or CIR0 switches the INT line to ...
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R (a) IOM -1 FSC1/2 DIU IDP1 DR IDP2 R (b) IOM -2 FSC DIU DIU IDP1 DR DR IDP0 DCL Figure 72 ® Deactivation of the IOM Interface Semiconductor Group DIU DIU DIU DR DID DID DIU DIU DIU ...
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The clock pulses will be enabled again when the IDP1 line is pulled low (bit SPU, SPCR register) i.e. the C/I command TIM = "0000" is received by layer 1, or when a non-zero level on the S-line interface is ...
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IOM –2 SPU = 1 FSC IDP1 IDP0 FSC IDP1 0 IDP0 DCL Note : IDP0 is input and IDP1 is low during IOM -CH1 if IDP0 is low and IDP1 is input during IOM ...
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The ISAC-S supplies IOM timing signals as long as there is no DIU command in the C/I (C/I0) channel. If timing signals are no longer required and activation is not yet requested, this is indicated by programming DIU in the ...
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C / S-INFO Figure 74 3.3.2.1 Layer-1 Command/Indication Codes and State Diagrams in TE/LT-T Modes Table 12 Commands TE/LT-T Command (upstream) Timing Reset Send continuous zeros Send single zeros Activate request, set priority 8 Activate request, set priority 10 Activate ...
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Table 13 Indications TE/LT-T Indication (downstream) Power up Deactivate request Slip detected Disconnected Error indication Level detected Activate request downstream Test indication Awake test indication Activate indication with priority class 8 Activate indication with priority class 10 Deactivate indication downstream ...
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F3 Power Down This is the deactivated state of the physical protocol. The receive line awake unit is active except during an RST pulse. Clocks are disabled if ADF1/SQXR:CFS=1 (TE mode). The power consumption in this state is approximately 80 ...
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F8 Lost Framing This is the condition where the ISAC-S has lost frame synchronization and is awaiting re- synchronization by INFO2 or INFO4 or deactivation by INFO0. Unconditional States Loop 3 Closed On Activate Request Loop command, INFO3 is sent ...
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RSYD X F8 Lost Framing Figure 75a State Diagram of TE/LT-T Mode Semiconductor Group DID RST F3 Power Down i0 i0 DIU PU ARU TIM F4 Pend. Act RSYD X ...
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ARL Loop i3 Loop OUT R IOM S : Only Internally Forcing Commands can be : ARL, RES, TM, SSP : is Single Pulses Test Pulses, Figure 75b State Diagram of TE/LT-T Mode: Unconditional Transitions ...
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Layer-1 Command/Indication Codes and State Diagrams in LT-S Mode Table 14 Commands and Indications in LT-S Mode Command (downstream) Deactivate request Send continuous zeros Send single zeros Activate request downstream Activate request loop Deactivate indication downstream Indication (upstream) Lost ...
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G1 Deactivated The ISAC-S is not transmitting. No signal detected on the S interface, and no activation command is received in the C/I channel. G2 Synchronized As a result of an INFO1 detected on the S line or an ARD ...
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DIU SCZ Test Mode Continuous Puls. ic DID OUT Ind. R IOM State S ix TIU : Transparent Indication Upstream can be : AIU, RSYU, LSL : is Single Pulses Continuous Pulses, Figure 76 State Diagram of ...
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Layer-1 Command/Indication Codes and State Diagrams in NT Mode Table 15 Commands and Indications NT Command (downstream) Deactivate request Resynchronization downstream Activate request downstream Activate request loop Deactivate indication downstream Activate indication downstream Activate indication loop Send single zeros ...
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G1 Deactivated The ISAC-S is not transmitting. No signal is detected on the S/T interface, and no activation command is received in the C/I channel output as a response to RST, DIU is output in the normal deactivated ...
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DIU * SCZ Test Mode Continuous Puls DID OUT IN Ind. Cmd. R IOM State TIU : Transparent Indication can be : AIU, RSYU, LSL : is Single Pulses, 4 kHz ic : Continuous Pulses, ...
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Example of Activation/Deactivation An example of an activation/deactivation of the S interface, with the time relationships mentioned in the previous chapters, is shown in figure 78, in the case of an ISAC LT-S modes. ARU RSYD ARD AID DR ...
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Control of Layer-2 Data Transfer The control of the data transfer phase is mainly done by commands from the P to ISAC-S via the Command Register (CMDR). Table 16 gives a summary of possible interrupts from the HDLC controller ...
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Mnemonic Register (addr. hex) XPR ISTA (20) XMR EXIR (24) XDU EXIR (24) RSC ISTA (20) TIN ISTA (20) Semiconductor Group Meaning Layer-2 Transmit Transmit Pool Ready. Further octets of an HDLC frame can be written to XFIFO. If XIFC ...
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Table 17 List of Commands (CMDR (21) Register) Command HEX Bit 7…0 Mnemonic RMC 80 1000 RRES 40 0100 RNR 20 0010 STI 10 0001 XTFC 0A 0000 (XTF+XME) XIFC 06 0000 (XIF+XME) XTF 08 0000 XIF 04 0000 XRES ...
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HDLC Frame Reception Assuming a normally running communication link (layer-1 activated, layer-2 link established, TEI assigned), figure 79 illustrates the transfer of an I-frame via the D channel. The transmitter is shown on the left and the receiver on ...
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Flag SAP1, SAP2 Auto Mode - (U and Frames SAP1, SAP2 Non-Auto Mode Transparent Mode 1 Transparent Mode 2 SAP1, SAP2 Transparent Mode 3 Description of Symbols: Figure 80 Receive Data Flow Note 1 Only if a 2-byte ...
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RMC, the corresponding interrupt will be generated only when RMC has been issued. When RME has been indicated, bits 0-4 of the RBCL register represent the number of bytes stored in the RFIFO. Bits 7-5 of RBCL and bits ...
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The HDLC controller will request another data block by an XPR interrupt if there are no more than 32 bytes in XFIFO and the frame close command bit (Transmit Message End XME) has not been set. To this the microcontroller ...
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Register (address (hex)) MODE (22) RBCL (25) RBCH (2A) SPCR (30) CIR0 (31) CIX0 (31) STCR (37) ADF1 (38) ADF2 (39) SQXR (3B) Semiconductor Group Value after Meaning Reset (hex) 00 – auto mode – 1-octet address field – external ...
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Initialization During initialization a subset of registers have to be programmed to set the configuration parameters according to the application and desired features. They are listed in table 19. Table 19 Register (address) Bit ADF2 (39 ) IMS H ...
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Register (address) Bit ADF1 (38 ) TEM H CFS PFS CSEL2-0 IOF FC1-2 CIX0 (31 ) RSS H STCR (37 ) TSF H TBA2-0 MODE (22 ) MDS2-0 H TMD DIM2-0 Semiconductor Group Effect Test Mode 0 Permanent standby 1 ...
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Register (address) Bit TIMR (23 ) CNT H VALUE XAD1 ( XAD2 ( SAP1/2 (26 / TEI1/2 (28 / Note: After a hardware reset the pins SDAX/SDS1 and SCA/FSD/SDS2 are ...
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Detailed Register Description The parameterization of the ISAC-S and the transfer of data and control information between the P and ISAC-S is performed through two register sets. The register set in the address range 00-2B controller. It includes the ...
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Table 21 ® ISAC -S Address Map 30-3B Address Read (hex) Name Description 30 SPCR Serial Port Control Register 31 CIRR/ Command/Indication CIR0 Receive (0) 32 MOR/ MONITOR Receive (0) MOR0 33 SSCR/ SIP Signaling Code Receive/ CIR1 Command/Indication Receive ...
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Table 22 Register Summary: HDLC Operation and Status Registers 7 20 RME RPF H 20 RME RPF H 21 XDOV XFW XRNR H 21 RMC RRES H 22 MDS2 MDS1 MDS0 H 23 CNT H 24 XMR XDU H 24 ...
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Table 23 Register Summary: Special Purpose Register IOM ® IOM - SPU SAC H 31 SQC BAS H 31 RSS BAC ...
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Table 24 Register Summary: Special Purpose Register IOM ® IOM - SPU SQC BAS H 31 RSS BAC ...
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HDLC Operation and Status Registers 4.1.1 Receive FIFO A read access to any address within the range 00-1F location selected by an internal pointer which is automatically incremented after each read access. This allows for the use of efficient ...