SAB82525 Infineon Technologies AG, SAB82525 Datasheet

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SAB82525

Manufacturer Part Number
SAB82525
Description
SAB82525Data Communications ICs
Manufacturer
Infineon Technologies AG
Datasheet

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Data Communications ICs
High-Level Serial Communication
Controller Extended (HSCX)
SAB 82525; SAB 82526
SAF 82525; SAF 82526
User’s Manual 10.94

Related parts for SAB82525

SAB82525 Summary of contents

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... Data Communications ICs High-Level Serial Communication Controller Extended (HSCX) SAB 82525; SAB 82526 SAF 82525; SAF 82526 User’s Manual 10.94 ...

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SAB 82525; SAF 82525; SAB 82526; SAF 82526 Revision History: Previous Releases: Page Subjects (changes since last revision) Update Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irrevers- ible damage to ...

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Table of Contents 1 Features ..................................................................................................................... 6 1.1 Pin Definitions and Functions ................................................................................... 10 1.2 System Integration .................................................................................................... 17 1.3 Functional Description .............................................................................................. 22 2 Operating Modes ..................................................................................................... 24 2.1 Auto-Mode (MODE: MDS1, MDS0 = 00) .................................................................. 24 2.2 Non-Auto ...

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Table of Contents 6.8 Test Mode ................................................................................................................. 68 6.7 Special RTS Function ............................................................................................... 68 7 Operational Description ......................................................................................... 69 7.1 RESET ...................................................................................................................... 69 7.2 Initialization ............................................................................................................... 70 7.3 Operational Phase .................................................................................................... 71 7.4 Data Transmission .................................................................................................... 71 7.5 Data Reception ...

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The SAB 82525 is a High-Level Serial Communication Controller compatible to the SAB 82520 HSCC with extended features and functionality (HSCX). The SAB 82526 is pin and software compatible to the SAB 82525, realizing one HDLC channel (channel B). The ...

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High-Level Serial Communications Controller Extended (HSCX) Preliminary Data 1 Features Serial Interface Two independent full-duplex HDLC channels (SAB 82526: one channel) On chip clock generation or external clock source – On chip DPLL for clock recovery for each channel – ...

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Features (cont’d) Protocol Support Various types of protocol support depending on operating mode – Auto-mode – Non-auto mode – Transparent mode Handling of bit oriented functions in all modes Support of LAPB/LAPD/SDLC/HDLC protocol in auto-mode (I- and S-frame handling) Modulo ...

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Pin Configurations (top view) WR/IC0 CS RxDA RTSA CTSA/CxDA TxDA TxDB CTSB/CxDB RTSB RxDB RES WR/IC0 CS N.C. N.C. N.C. N.C. TxDB CTSB/CxDB RTSB RxDB RES Semiconductor Group P-LCC- ...

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Pin Configurations (top view) DRQTA RD/IC 1 Semiconductor Group P-MQFP-44 HSCX ...

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Pin Definitions and Functions Pin No. Symbol Input (I) Output (O) P-LCC P-MQFP I ...

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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) P-LCC P-MQFP 9 14 RXDA RXDB RTSA 15 20 RTSB 11 16 CTSA/ I CXDA 14 19 CTSB/ CXDB 12 17 TXDA ...

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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) P-LCC P-MQFP 18 23 IM1 ALE/ I IM0 ...

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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) P-LCC P-MQFP INT 30 35 DACKA DACKB 34 39 AxCLK AxCLK B Semiconductor Group Function Interrupt Request The ...

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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) P-LCC P-MQFP 36 41 TxCLK A I TxCLK RxCLK RxCLK DRQRA DRQRB Semiconductor ...

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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) P-LCC P-MQFP 40 1 DRQTA DRQTB Semiconductor Group Function DMA Request Transmitter (channel A/channel B) The transmitter of the HSCX ...

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A0-A6 D0-D7 RD/IC1 WR/IC0 CS ALE/IMO µP Bus INT Interface RES IM1 DRQTA DRQRA DMA DACKA Interface DRQTB DRQRB DACKB Figure 1 Block Diagram SAB 82525/SAB 82526 The HSCX SAB 82526 comprises one (channel B), the SAB 82525 two completely ...

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System Integration General Aspects Figure 2 gives a general overview of the system integration of HSCX. Memory DMA Controller DATA Figure 2 General System Integration of HSCX The HSCX bus interface consists of an 8-bit bidirectional data bus (D0–D7), ...

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Specific Applications HSCX with SAB 8051 Microcontroller For cost-sensitive applications, the HSCX can be interfaced with a small SAB 8051 microcontroller system (without DMA support) very easily as shown in figure 3. INT0 RD WR ALE SAB 8051 CPU A8 ...

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HSCX with SAB 80188 Microprocessor A system with minimized additional hardware expense can be with a SAB 80188 microprocessor as shown in figure 4. INTn PSCn DRQ0 DRQ1 SAB 80188 CPU A8 - A15 AD0 - AD7 Latches Transceiver Figure ...

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HSCX with SAB 80186 Microprocessor and SAB 82258 Advanced DMA Controller (ADMA) In applications, where two high-speed channels are required, a 16-bit system with SAB 80186 CPU and SAB 82258 ADMA is suitable. This is shown in figure 5. INTn ...

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The four selector channels of ADMA are used for serving the four DMA request sources of HSCX, allowing very high data rates at both the system bus and the serial channels. Another big advantage of the ADMA is it’s data ...

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Point-to-Point Configuration TxD RxD HSCX Controller RxD - Receive Data TxD - Transmit Data Point-to-Multipoint Configuration CxD TxD RxD HSCX Slave 1 Controller RxD - Receive Data TxD - Transmit Data Multimaster Configuration CxD TxD RxD HSCX Master 1 Controller ...

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Support of layer-2 functions by HSCX Beside those bit-oriented functions usually supported with the HDLC protocol, such as bit stuffing, CRC check, flag and address recognition, the HSCX provides a high degree of procedural support special operating mode ...

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Operating Modes The HDLC controller of each channel can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus, the receive data flow and the address recognition features ...

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Transparent Mode 1 (MODE: MDS1, MDS0, ADM = 101) Characteristics: address recognition high byte Only the high byte of a 2-byte address field will be compared. The whole frame except the first address byte will be stored in RFIFO. ...

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Receive Data Flow (Summary) The following figure gives an overview of the management of the received HDLC frames as affected by different operating modes. MDS1 MDS0 ADM MODE Auto/ Auto/8 Non 0 1 ...

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Transmit Data Flow Two different types of frames can be transmitted: – I-frames and – transparent frames as shown below. FLAG Transmit Transparent Frame (XTF) Transmit I-Frame (XIF) *1 Optional checkram handling in version 2 upward Figure 9 Transmit ...

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Procedural Support (Layer-2 Functions) When operating in the auto-mode, the HSCX offers a high degree of procedural support. In addition to address recognition, the HSCX autonomously processes all (numbered) S- and I-frames (prerequisite window size 1) with either normal ...

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Transmission of Frames The HSCX autonomously transmits S commands and S responses in the auto-mode. Either transparent or I-frames can be transmitted by the user. The software timer has to be operated in the internal timer mode to transmit I-frames. ...

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RR, REJ , SREJ Y CRC Error or Abort ? N Y Prot. Error ? N : Int PCE RESET RRNR 1 Wait for N Acknowledge ? (S) V ...

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Rec. RNR Set RRNR 1 t Run Out Load t1 N Rec. Ready ? Y Trm RR Trm RNR Command ...

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Examples The interaction between the HSCX and the CPU during the transmission and reception of I-frames is illustrated in figure 12, the flow control with RR/RNR during the reception of I-frames in figure 13, and during the transmission of I-frames ...

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Figure 14 Flow Control/Transmission Figure 15 S Commands/Protocol Error Semiconductor Group XPR (0.0) RNR (0) RSC(RNR) t1 WFA RR ( RNR ( XMR ALLS ...

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Half-Duplex SDLC-NRM Operation The LAP controllers of the two serial channels can be configured to function in a half-duplex Normal Response Mode (NRM), where they will operate as a slave (secondary) station, by setting the NRM bit in the ...

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Since the on-chip timer of the HSCX must be operated in the external mode (a secondary may not poll the primary for acknowledgements), time supervisory must be done by the primary station. Upon the arrival of an acknowledgement the XFIFO ...

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Examples A few examples of HSCX/CPU interaction in case of NRM mode are provided in figure 16 to figure 19. Figure 16 No Data to Send Figure 17 Data Reception/Transmission Semiconductor Group RR ( (0) f ...

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Figure 18 Data Transmission (no Error) Figure 19 Data Transmission (Error) Semiconductor Group RR ( XIF (0, ( ALLS ITD00238 XIF RR ( (0. ...

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Error Handling Depending on the error type, erroneous frames are handled according table 1. Table 1 Error Handling Frame Type Error Type CRC error I aborted unexpec. N(S) unexpec. N(R) S CRC error aborted unexpec. N(R) with I-field Note: ...

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Interrupt Interface Special events in the HSCX are indicated by means of a single interrupt output, which requests the CPU to read status information from the HSCX, or, if Interrupt Mode is selected, transfer data from/to HSCX. Since only ...

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Five interrupt indications can be read directly from the ISTA register and another six interrupt indications from the extended interrupt register (EXIR). After the HSCX has requested an interrupt by setting its INT pin to low, the CPU must first ...

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Table 2 Receive Interrupts RECEIVE INTERRUPTS RPF Receive Pool Full (ISTA) RME Receive Message End (ISTA) RFO Receive Frame Overflow (EXIR) RFS Receive Frame Start (EXIR) Semiconductor Group *Only activated in Interrupt Mode! Activated as soon as 32-bytes are stored ...

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Table 3 Transmit Interrupts TRANSMIT INTERRUPTS XPR Transmit Pool Ready (ISTA) XMR Transmit Message Repeat (EXIR) XDU Transmit Data Underrun (EXIR) Semiconductor Group Activated whenever a 32-byte FIFO pool is empty and accessible to the CPU, i.e. – following a ...

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Table 4 Special Condition Interrupts SPECIAL CONDITION INTERRUPTS Layer 2-Specific * Activated only if the "Auto" operating mode has been selected via MODE register) RSC Receive Status Change PCE Protocol Error Internal Timer TIN Timer Interrupt (ISTA) External Pin CSC ...

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HSCX supports target synchronous as well as source synchronous DMA transfer. In source synchronous DMA transfer mode a DMA cycle is started when an active level occurs an the DMA request line. This request is controlled by the source (transfer ...

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CLOCKOUT DRQ RD (Memory) WR (FIFO DRHSYS max CVCTV f t CLKOUT CLCL 8 MHz 125 ns 12.5 MHz MHz 62 you use the write signal instead of ...

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CLOCKOUT DRQTx DRQ RD (Memory) CS (FIFO) WR (FIFO T4/2 DRHSYS max f t CLKOUT CLCL 8 MHz 125 ns 12.5 MHz MHz 62.5 ns The circuit mentioned above results in ...

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FIFO Structure In both transmit and receive direction 64-byte deep FIFO’s are provided for the intermediate storage of data between the serial interface and the CPU interface. The FIFO’s are divided into two halves of 32-bytes, where only one ...

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If frames longer than 64 bytes are received, the device will repeatedly prompt to read out 32- byte data blocks via interrupt or DMA. In the case of several shorter frames may be stored in the HSCX. ...

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Serial Interface (Layer-1 Functions) The two serial interfaces of the HSCX provide two fully independent communications channels, supporting layer-1 functions to a high degree by various means of clock generation and clock recovery. 5.1 Clock Modes The HSCX includes ...

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Clock Mode 1 (Receive/Transmit Strobes) Externally generated, but identical receive and transmit clocks are forwarded via R CLK pins. In addition, a receive strobe can be connected via A CLK and a transmit strobe via T CLK pins. The operating ...

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Register : TSAR TSAX CLK T x CLK Figure 23 Location of Time-Slots The transmit time-slot is additionally indicated by a control signal via T CLK, which output is set to log 0 during the transmit window. ...

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RTS Signal in Clock Mode 5 When using the RTS signal in clock mode 5, it has to be considered, that the RTS signal is deactivated after the transmission of the second last bit (instead of the last ...

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This must be considered for applications, where several transmitters are sharing the same time-slot on a non open-drain bus, e.g. a balanced bus, not using collision detection as the resolution mechanism. One such application is slave stations in a point-to-multipoint ...

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RTS (e.g. for NRM mode with balanced bus). RTS HSCX TxCLK TxD Figure 26 Timing diagram for recommendation b): Time-Slot n TxCLK (TS-Ctrl) TxD RTS RTS ideal RTS (rec. b) INT XPR Int Status ...

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CTS Signal in Clock Mode 5 In clock mode 5 the CTS signal is evaluated not only in the time-slot “window“, but also between the time-slot “windows“. If data transmission must not be stopped, CTS has to be active, even ...

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Summary The features of the different clock modes are summarized in table 6. Table 6 Clock Modes of HSCX Channel Configuration Clock Mode CCR2 CCR1 TSS TIO BRG CM2, CM1, CM0 – – 2 ...

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Normally 33 pF capacitors are used for frequencies below 10 MHz and 22 pF capacitors are used for frequencies above 10 MHz. To guarantee oscillation use the capacitances which are specified by the crystal manufacturer. 5.2 Clock Recovery (DPLL) The ...

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The following functions have been implemented to facilitate a high-speed and reliable synchronization (see figures 28). – Interference Rejection In the case where two or more edges appear in the data stream within a time period of 16 reference clocks, ...

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Phase Shift In the case the DPLL detects an edge in the data stream in the range of DPLL count (Phase Shift) and this is the only one in the assumed bit cell period, then the ...

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Bus Configuration Beside the point-to-point configuration, the HSCX effectively supports point-to-multipoint (pt- mpt, or bus) configurations by means of internal idle and collision detection/collision resolution methods pt-mpt configuration, comprising a central station (master) and several peripheral stations ...

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Bus Access Procedure The idle state of the bus is identified by eight or more successive 1’s. In case of a transmit re- quest in the HSCX, the frame is transmitted and the bus is identified as busy with the ...

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Functions of RTS Output In clock modes and 5, the RTS output can be programmed via CCR2 (SOC bits active when a frame is being transmitted. The signal is delayed by one clock period with ...

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Data Encoding In the point-to-point configuration, the HSCX supports both NRZ and NRZI data encoding (selectable via CCR1 register). NRZ Encoding 1 NRZI Encoding 1 Figure 30 NRZ Encoding/NRZI Encoding During NRZI encoding, level changes are interpreted as log ...

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CTS Signal Clock Mode 5 In clock mode 5 the CTS signal is evaluated not only in the time-slot "window", but also between the time-slot "windows". CTS must not be disabled during the transmission of a frame. Even between the ...

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Special Functions 6.1 Fully Transparent Transmission and Reception When programmed to the extended transparent mode via the MODE register (MDS1, MDS0 = 11), each channel of the HSCX supports fully transparent data transmission and reception without HDLC framing overhead, ...

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Continuous Transmission (DMA Mode only) If data transfer from system memory to the HSCX is done by DMA (DMA bit in XBCH set), the number of bytes to be transmitted is usually defined via the Transmit Byte Count registers ...

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One Bit Insertion Similar to the zero bit insertion (bit-stuffing) mechanism, as defined by the HDLC protocol, the HSCX offers a completely new feature of inserting/deleting a one after seven consecutive zeros in the transmit/receive data stream, if the ...

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Special RTS Function Beyond the regular RTS function, signifying the transmission of a frame (Request To Send), the RTS output may be programmed for a special function via SOC1, SOC0 bits in the CCR2 register, provided the serial channel ...

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Operational Description 7.1 RESET The HSCX is forced into the reset state if a high signal is input to the RES pin for a minimum period of 1.8 s. During RESET, the HSCX is temporarily in the power-up mode, ...

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Initialization After reset the CPU has to write a minimum set of registers and an optionally set dependent on the required features and operating modes. First, the configuration of the serial port and the clock mode has to be ...

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Table 9 User Demand Registers User Demand CTS/RFS Interrupt Provided Selective Interrupts Should be Masked Timer will be used by CPU (external timer mode) DMA Controlled Data Transfer Receive Length Check Feature Extended (module 128) Counting 7.3 Operational Phase After ...

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Command XTF XIF / Figure 32 Interrupt Driven Data Transmission (Flow Diagram) The activities at both serial and CPU interface during frame transmission (supposed frame length = 70 bytes) is shown in figure 33. Serial Interface HSCX CPU . . ...

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Back to Back Frames If two or more frames should be transmitted in a high speed sequence without interframe time fill, the transmission sequence according figure 34 has to be used. This means that the closing flag will be immediately ...

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The activities during frame transmission (supposed two frames, 18 bytes and 52 bytes) is shown in figure 35. Serial ITF Interface HSCX CPU . . . Interface WR XTF 18 Bytes XPR Figure 35 Continuous Frames Transmission Sequence Example DMA ...

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The following figure gives an example of a DMA driven transmission sequence with a supposed frame length of 70 bytes, i.e. programmed transmit byte count (XCNT) equal 69 bytes. Serial Interface HSCX (69) CPU/DMA DRQT(32) Interface WR XTF XCNT Figure ...

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In addition to the message end (RME) interrupt, the following information about the received frame is stored by the HSCX in special registers and/or RFIFO: Table 10 Status Information after RME Interrupt Length of message (bytes) Address combination and/or Address ...

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The following figure gives an example of an interrupt controlled reception sequence, supposed that a long frame (66 bytes) followed by two short frames (6 bytes each) are received. Receive Frame 1 (66 Bytes Serial Interface HSCX CPU ...

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After the DMA controller has been set up for the reception of the next frame, the CPU must be issue a RMC command to acknowledge the completion of the receive frame processing. The HSCX will not initiate further DMA cycles ...

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Detailed Register Description 8.1 Register Address Arrangement Table 11 Layout of Register Addresses ADDRESS REGISTER Channel A B Read Write RFIFO XFIFO Receive/Transmit FIFO : : ISTA MASK Interrupt STAtus/Mask 21 ...

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Register Definitions Receive FIFO (Read) RFIFO (00. . .1F/40. . .5F) Interrupt Controlled Data Transfer (Interrupt Mode) selected if DMA bit in XBCH is reset bytes of receive data can be read from the RFIFO following ...

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Transmit FIFO (WRITE) XFIFO (00. . .1F/40. . .5F) Interrupt Mode selected if DMA bit in XBCH is reset bytes of transmit data can be written to the XFIFO following an XPR interrupt. DMA Mode selected if ...

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Interrupt Status Register (READ) 7 ISTA RME RPF Value after RESET RME. . .Receive Message End One message bytes or the last part of a message greater then 32 bytes has been received and is ...

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EXA … Extended Interrupt of Channel A (Channel B only) An interrupt is caused by channel B and source(s) is (are) indicated in the EXIR register of channel B. Note: The ICA, EXA, and EXB bit are present in channel ...

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Extended Interrupt Register (READ) Value after RESET EXIR XMR XDU EXE XMR … Transmit Message Repeat The transmission of the last message has to be repeated because – the HSCX has received a negative acknowledgement in auto-mode, ...

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PCE … Protocol Error (significant in auto-mode only!) The HSCX has detected a protocol error, i.e. it has received – an S-, or I-frame with incorrect N (R) – an S-frame containing an I-field. RFO … Receive Frame Overflow One ...

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Status Register (READ) Value after RESET STAR XDOV XFW XDOV … Transmit Data Overflow More than 32 bytes have been written to the XFIFO. XFW … Transmit FIFO Write Enable Data can be written to the XFIFO. ...

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Command Register (WRITE) Value after RESET CMDR RMC RHR Note: The maximum time between writing to the CMDR register and the execution of the command is 2.5 clock cycles. Therefore, if the CPU operates with a very ...

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STI … Start Timer The internal timer is started. Note: The timer is stopped by rewriting the TIMR register after start. XTF … Transmit Transparent Frame Interrupt mode After having written bytes the XFIFO, this command initiates ...

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Mode Register (READ/WRITE) Value after RESET MODE MDS1 MDS0 MDS1, MDS0 … Mode Select The operating mode of the HDLC controller is selected. 00 … auto-mode 01 … non-auto mode 10 … transparent mode 11 … extended ...

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TMD … Timer Mode The operation mode of the internal timer is set. 0 … external mode The timer is controlled by the CPU and can be started at any time setting the STI bit in CMDR. 1 … internal ...

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Timer Register (READ/WRITE) 75 TIMR CNT VALUE … Sets the time period (VALUE + 1) TCP 1 where – the timer resolution factor which is either 32.768 or 512-clock cycles dependent on the programming of ...

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Transmit Address Byte 1 (WRITE) XAD1 2-byte address 1-byte address XAD1 (and XAD2) can be programmed with one individual address byte which is appended automatically to the frame by HSCX in auto-mode. The function depends on the selected address mode ...

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Transmit Address Byte 2 (WRITE) XAD2 2-byte address 1-byte address Second individually programmable address byte. – – 2-byte address (MODE.ADM = 1) XAD2 builds up the low byte of the 2-byte address field (In the ISDN, the low address byte ...

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Receive Address Byte High Register 1 (WRITE) RAH1 In operating modes that provide high byte address recognition, the high byte of the received address is compared with the individual programmable values in RAH1, or RAH2. RAH1 … Value of the ...

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Receive Status Register (READ) 7 RSTA VFR RDO VFR … Valid Frame Determines whether a valid frame has been received. 1 … Valid 0 … Invalid An invalid frame is either – – a frame which is not an integer ...

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HA1, HA0 … High Byte Address Compare; significant only if 2-byte address mode has been selected. In operating modes which provide high byte address recognition, the HSCX compares the high byte of a 2-bytes address with the contents of two ...

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Receive Address Byte Low Register 1 (READ/WRITE) 7 RAL1 The general function (READ/WRITE) and the meaning or contents of this register depends on the selected operating mode: – – Auto-/non-auto mode (16-bit address) – WRITE only: RAL1 can be programmed ...

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Receive HDLC Control Register (READ) 7 RHCR Value of the HDLC control field corresponds to the last received frame. Note: RHCR is duplicated into RFIFO for every frame. Mode Auto-mode,1-byte address (U-frames) (Note 1) Auto-mode, 2-byte address (U-frames) (Note 1) ...

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Transmit Byte Count Low (WRITE) 7 XBCL XBC7 Together with XBCH (bits XBC11…XBC8) this register is used in DMA mode only, to program the length (1…4095 bytes) of the next frame to be transmitted. This allows the HSCX to request ...

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Channel Configuration Register 2 (READ/WRITE) Value after RESET The meaning of the individual bits in CCR2 depends on the selected clock mode via CCR 1 as follows: CCR2 clock mode 0,1 SOC1 SOC0 clock mode 2,6 BR9 clock ...

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CIE … Clear To Send Interrupt Enable Any state transition at the CTS input pin may cause an interrupt which is indicated in the EXIR register (CSC bit). The actual state at the CTS pin can be determined reading the ...

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Transmit Byte Count High (WRITE) Value after RESET: 000xxxxx 7 XBCH DMA NRM DMA … DMA Mode Selects the data transfer mode of HSCX to system memory. 0 … Interrupt controlled data transfer (interrupt mode) 1 … DMA controlled data ...

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Received Byte Count High (READ) Value after RESET: 000xxxxx 7 RBCH DMA NRM see XBCH DMA, NRM, CAS … These bits represent the read-back value programmed in XBCH (see XBCH!) OV … Counter Overflow More than 4095 bytes received! The ...

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Receive Length Check Register (WRITE) 7 RLCR RC RL6 RC … Receive Check (on/off) 0 … receive length check feature disabled 1 … receive length check feature enabled Note: All bytes stored in the RFIFO are relevant for the receive ...

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ODS … Output Driver Select Defines the function of the transmit data pins (T DA pins are open drain outputs pins are push-pull outputs Note: Since in time-slot oriented systems ...

Page 106

Time-Slot Assignment Register Transmit (WRITE) This registers is only used in clock mode 5! 7 TSAX TSNX … Time-Slot Number Transmit Selects one possible time-slots (00 number of bits per time-slot can be programmed via XCCR. XCS2, ...

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Transmit Channel Capacity Register (WRITE) Value after RESET This register is only used in clock mode 5. 7 XCCR XBC7 XBC7 … XBC0 … Transmit Bit Count, Bit 7-0 Defines the number of bits to be transmitted with ...

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Electrical Characteristics Absolute Maximum Ratings Parameter Ambient temperature under bias: SAB Storage temperature Voltage on any pin with respect to ground Maximum voltage on any pin Note: Stresses above those listed here may cause permanent damage to the device. ...

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Capacitances = 25 ° Parameter Input capacitance MHz C Output capacitance I/O Characteristics SAB ° ...

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Microcontroller Interface Timing Intel Bus Mode DRQR P Read Cycle DRQT P Write Cycle ALE Multiplexed Address Timing Semiconductor ...

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Microcontroller Interface Timing Intel Bus Mode DACK Address Timing Semiconductor Group t DCD 111 SAB 82525 SAB 82526 SAF 82525 SAF 82526 ITT00956 ...

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Motorola Bus Mode R DRQR P Read Cycle R DRQT P Write Cycle DACK Address Timing Semiconductor Group t RWH t DSD ...

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Interface Timing Parameter ALE pulse width Address setup time to ALE Address hold time from ALE Address latch setup time to WR, RD Address setup time to WR, RD Address hold time from WR, RD DMA request delay: SAB SAF ...

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Serial Interface Timing R Clock RxDA/B X Clock t TxDA/B TxDA/B CxDA/B CTSA/B RTSA/B RTSA/B RTSA/B Semiconductor Group CPH CPL t RDS t RDH CPH XDD 1 t XDD 2 t CDS t ...

Page 115

Strobe Timing (Clock Mode1) RxCLK AxCLK t TxCLK TxD TxD Parameter Receive strobe delay Receive strobe setup Receive strobe hold Transmit strobe delay Transmit strobe setup Transmit strobe hold Transmit data delay Strobe data delay High impedance from clock High ...

Page 116

Clock Mode 5 RxCLK AxCLK TxCLK t TCD TxCLK Synchronization Timing Parameter Sync pulse delay Sync pulse setup Sync pulse width Time-slot control delay Semiconductor Group TCD Symbol min ...

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Clock Mode Internal Clocking Parameter Clock frequency Baudrate generator used Clock frequency Baudrate generator not used RESET Timing RES Characteristics Parameter RES HIGH RxCLK RxD AxCLK (CD) CD Timing Semiconductor Group Symbol min. f CLK f ...

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Quartz Specifications Characterization of Quartz Crystals for the HSCX – Mode of oscillation – Frequency calibration tolerance – Frequency shift during lifetime – Temperature coefficient/frequency drift – Motional capacitance – Effective serial resistance – Shunt capacitance – Drive level ...

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Appendix A Upgrades of HSCX Version A3 The HSCX Version A3 is fully upward compatible to Version A2. The differences with respect to HSCX Technical Manual Rev. 2.89 are shown in table 12. Table 12 Differences HSCX A2 – HSCX ...

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Upgrades of HSCX Version V2.1 3 Version ID The bits VN3 … VN0 of the Version Status Register (VSTR) contain the value 5 for version V2.1. All HSCX version numbers are listed below: VN3 … 0 Version 0: 000 VA1 ...

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Clock Recovery (DPLL) In case the DPLL detects an edge in the data stream in the range of DPLL count (Phase Shift) and this is the only one in the assumed bit cell period, then the ...

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Appendix B HSCX Auto-Mode: Specific Points HSCX auto-mode of SAB 82525/SAB 82520 (HSCX/HSCC) is optimized for a window size of one. Therefore the following simplifications are made: No REJ-frame is generated, an RR-frame will be transmitted instead REJ-frame ...

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Appendix C Application Example HSCX with 80(C)188 using DMA DMA information, see chapter 4. Appendix D HSCX for Siemens Primary Access Interface The Siemens devices for the Primary Access Interface are the Advanced CMOS Frame Aligner (ACFA) and the Primary ...

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The adaption of the AxCLKA/B pulses is solved by means of shifting the receive data and transmit data in the ACFA device appropriately. In this case the AxCLKA and AxCLKB synchronization pulses are also identical. The ACFA device contains special ...

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Package Outlines Plastic Package, P-LCC-44-1 (SMD) (Plastic-Leaded Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 125 SAB 82525 SAB 82526 SAF ...

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Plastic Package, P-MQFP-44-2 (SMD) (Plastic-Leaded Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 126 SAB 82525 SAB 82526 SAF 82525 SAF 82526 ...

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