UPD431000AGZ-70LL-KJH NEC, UPD431000AGZ-70LL-KJH Datasheet
UPD431000AGZ-70LL-KJH
Available stocks
Related parts for UPD431000AGZ-70LL-KJH
UPD431000AGZ-70LL-KJH Summary of contents
Page 1
... CC The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M11657EJBV0DS00 (11th edition) Date Published April 2002 NS CP (K) ...
Page 2
Ordering Information Part number Package PD431000ACZ-70L 32-pin PLASTIC DIP PD431000ACZ-85L (15.24mm (600)) PD431000ACZ-70LL PD431000ACZ-85LL PD431000AGW-70L 32-pin PLASTIC SOP PD431000AGW-85L (13.34 mm (525)) PD431000AGW-70LL PD431000AGW-85LL PD431000AGW-A10 PD431000AGW-B12 PD431000AGW-B15 PD431000AGZ-85L-KJH 32-pin PLASTIC TSOP(I) PD431000AGZ-70LL-KJH (8x20) (Normal bent) PD431000AGZ-85LL-KJH PD431000AGZ-B10-KJH PD431000AGZ-B15-KJH PD431000AGZ-70LL-KKH 32-pin ...
Page 3
... A0 - A16 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable V : Power supply CC GND : Ground connection Data Sheet M11657EJBV0DS PD431000A V CC A15 CE2 /WE A13 A8 A9 A11 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 3 ...
Page 4
... A0 - A16 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable V : Power supply CC GND : Ground connection Data Sheet M11657EJBV0DS PD431000A V CC A15 CE2 /WE A13 A8 A9 A11 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 ...
Page 5
... A16 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable V : Power supply CC GND : Ground connection Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M11657EJBV0DS PD431000A 32 /OE 31 A10 30 /CE1 29 I/O8 28 I/O7 27 I/O6 26 I/O5 25 ...
Page 6
... Remark Refer to Package Drawings for the 1-pin index mark PD431000AGU-Bxx-9JH] [ PD431000AGU-Bxx-9KH A16 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable V : Power supply CC GND : Ground connection Data Sheet M11657EJBV0DS PD431000A 32 /OE 31 A10 30 /CE1 29 I/O8 28 I/O7 27 I/O6 26 I/O5 25 I/O4 24 ...
Page 7
Block Diagram V CC GND A0 Address buffer A16 I/O1 I/O8 /CE1 CE2 /OE /WE Truth Table /CE1 CE2 / Remark : Row Memory cell ...
Page 8
Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Input / Output voltage Operating ambient temperature Storage temperature Note –3.0 V (MIN.) (Pulse width: 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause ...
Page 9
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Test condition Input leakage current I/O leakage I/O CC current /CE1 ...
Page 10
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol Input leakage current I/O leakage current I Operating ...
Page 11
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ PD431000A-70L, PD431000A-85L, PD431000A-70LL, PD431000A-85LL] Input Waveform (Rise and Fall Time 2.2 V 1.5 V 0.8 V Output Waveform 1.5 V Output Load AC characteristics should be measured with ...
Page 12
Read Cycle (1/2) Parameter Symbol Read cycle time t RC Address access time t AA /CE1 access time t CO1 CE2 access time t CO2 /OE to output valid t OE Output hold from address change t OH /CE1 to ...
Page 13
Read Cycle Timing Chart Address (Input) /CE1 (Input) CE2 (Input) /OE (Input) I/O (Output) Remark In read cycle, /WE should be fixed to high level CO1 t LZ1 t CO2 t LZ2 ...
Page 14
Write Cycle (1/2) Parameter Symbol ` Write cycle time t WC /CE1 to end of write t CW1 CE2 to end of write t CW2 Address valid to end of write t AW Address setup time t AS Write pulse ...
Page 15
Write Cycle Timing Chart 1 (/WE Controlled) Address (Input) /CE1 (Input) CE2 (Input /WE (Input) I/O (Input / Output) Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. ...
Page 16
Write Cycle Timing Chart 2 (/CE1 Controlled) Address (Input) /CE1 (Input) CE2 (Input) /WE (Input) High impedance I/O (Input) Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated not input data ...
Page 17
Write Cycle Timing Chart 3 (CE2 Controlled) Address (Input) /CE1 (Input) CE2 (Input) /WE (Input) High impedance I/O (Input) Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated not input data ...
Page 18
Low V Data Retention Characteristics (T CC Parameter Symbol Test Condition Data retention V /CE1 V CCDR1 CC supply voltage CE2 V 0 CE2 0.2 V CCDR2 Data retention 3.0 V, /CE1 CCDR1 CC ...
Page 19
Data Retention Timing Chart (1) /CE1 Controlled t CDR V CC Note 4.5 V /CE1 V (MIN (MIN.) CCDR V (MAX.) IL GND Note A version : 3 version : 2.7 V Remark On the data ...
Page 20
Package Drawings 32-PIN PLASTIC DIP (15.24mm(600 NOTES 1. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2. Item "K" to center ...
Page 21
PLASTIC SOP (13.34 mm (525 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 17 detail of lead ...
Page 22
PLASTIC TSOP(I) (8x20 NOTES 1. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) ...
Page 23
PLASTIC TSOP(I) (8x20 NOTES 1. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX ...
Page 24
PLASTIC TSOP(I) (8x13. NOTES 1. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm ...
Page 25
PLASTIC TSOP(I) (8x13. NOTES 1. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm ...
Page 26
Recommended Soldering Conditions The following conditions must be met when soldering conditions of the PD431000A. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Please consult with our sales offices in case other soldering process is ...
Page 27
Revision History Edition/ Page Date This Previous edition edition 11th edition/ Throughout Throughout April 2002 25 Type of Location revision Addition Part number PD431000AGZ-B10-KJH PD431000AGU-B10-9JH PD431000AGU-B10-9KH Addition Package 32-pin PLASTIC TSOP(I) (8x13.4) ...
Page 28
Data Sheet M11657EJBV0DS PD431000A ...
Page 29
Data Sheet M11657EJBV0DS PD431000A 29 ...
Page 30
Data Sheet M11657EJBV0DS PD431000A ...
Page 31
... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
Page 32
... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others ...