AM386SX Advanced Micro Devices, AM386SX Datasheet
AM386SX
Available stocks
Related parts for AM386SX
AM386SX Summary of contents
Page 1
... A large number of PC operating systems and Real Time Operating Systems (RTOS) support the Am386SX/SXL/SXLV microprocessors. This means cheaper development costs, and improved time to mar- ket. The Am386SX/SXL/SXLV microprocessor is available in a small footprint 100-pin Plastic Quad Flat Pack (PQFP) package. Publication# 21020 Rev: A Amendment/0 ...
Page 2
... AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below 80386 SX Valid Combinations NG80386 SX SXL SXLV ING80386 SX 2 Am386SX/SXL/SXLV Microprocessors Data Sheet –40 SPEED OPTION – MHz – MHz – MHz PROCESSOR TYPE Processor SXL = SX Processor with Static Clock Implementation ...
Page 3
... Standby Mode (Am386SXL/SXLV Only) The true static design of the Am386SXL/SXLV micro- processor allows for a Standby Mode. At any operating speed, the microprocessor will retain its state (i.e., the contents of all its registers). By shutting off the clock completely, the device enters Standby Mode ...
Page 4
... FCC approval easier to ob- tain. SMM—System Management Mode (Am386SXLV Only) The Am386SXLV microprocessor has a System Man- agement Mode (SMM) for system and power manage- ment. This mode consists of two features: System Management Interrupt (SMI) and I/O instruction break. ...
Page 5
... CPU and normal code execution will continue at the point where it left off before the SMI occurred. There are 114 data transfer cycles in the restore operation. Software Features (Am386SXLV Only) Several features of the SMI function provide support for special operations during the execution of the system’s software ...
Page 6
... I/O Instruction Break (Am386SXLV Only) The Am386SXLV microprocessor has an I/O instruc- tion break feature that allows the system logic to imple- ment I/O trapping for peripheral devices. To enable the I/O Instruction break feature, IIBEN must first be as- serted active Low ...
Page 7
... M/IO 23 D/C 24 W/R 25 Notes : Pin 1 is marked for orientation NC = Not connected; connection pin may cause a malfunction or incompatibility with future shippings of the Am386SX/SXL/SXLV microprocessors * = On Am386SXLV only Am386SX/SXL Am386SX/SXL/SXLV Microprocessors Data Sheet Top Side View 75 A20 74 A19 73 A18 72 A17 71 ...
Page 8
... HLDA Notes : Pin 1 is marked for orientation NC = Not connected; connection pin may cause a malfunction or incompatibility with future shippings of the Am386SX/SXL/SXLV microprocessors * = On Am386SXLV only Am386SX/SXL 8 Am386SX/SXL/SXLV Microprocessors Data Sheet Pin Side View ...
Page 9
... A14 65 D13 A15 66 D14 A16 70 D15 A17 72 A18 A18 73 74 A19 A20 75 A21 76 A22 79 A23 Am386SXLV only Am386SX/SXL PIN DESIGNATION TABLE (Sorted by Pin Number) Pin No. Pin Name Pin No HLDA 23 4 HOLD ...
Page 10
... NC pin may cause the processor to malfunction or be incompatible with future steppings of the Am386SX/ SXL/SXLV microprocessor. NMI Non-Maskable Interrupt Request (Active High; Input) A non-maskable input that signals to the Am386SX/ SXL/SXLV microprocessor to suspend execution of the current program and execute an interrupt acknowledge function. PEREQ Processor Extension Request (Active High; Input) Indicates that the processor has data to be transferred by the Am386SX/SXL/SXLV microprocessor ...
Page 11
... SMM. SMI is not three-stated during Hold Acknowl- edge bus cycles. SMIADS (Am386SXLV Only) SMI Address Status (Active Low; Output) When active, this pin indicates that a valid bus cycle definition and address (W/R, D/C, M/IO, BHE, BLE, and A23–A1) are being driven at the Am386SXLV mi- LOGIC SYMBOL 2X Clock 23 Address Bus ...
Page 12
... Stresses above those listed may cause permanent damage to the device. Functionality at or above these limits is not implied. Exposure to ABSOLUTE MAXI- MUM RATING conditions for extended periods may af- fect device reliability. DC CHARACTERISTICS over COMMERCIAL operating ranges for 25 MHz Am386SXLV +100 C cc ...
Page 13
... Not 100% tested. 5. Outputs are CMOS and will pull rail-to-rail if the load is not resistive SMI only valid on SMI output when exiting SMM for two CLK2 periods (on Am386SXLV only SMI and IIBEN leakage Low will be I when pull-up is inactive and ...
Page 14
... Legend: A–Maximum Output Delay Characteristic B–Minimum Output Delay Characteristic C–Minimum Input Setup Characteristic D–Minimum Input Hold Characteristic Notes: 1. Input waveforms have tr 2.0 ns from 0.8 V–2.0 V (on Am386SXLV only Am386SX/SXL 1.5; on Am386SXLV Am386SXLV only. Figure 2. Drive Levels and Measurement Points for Switching Characteristics ...
Page 15
... SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges at 25 MHz V = 5 +100 C (Commercial CASE V = 3.0 V–5 +100 C (Am386SXLV only) CC CASE Symbol Parameter Description Operating Frequency: Am386SX CPU Am386SXL/SXLV CPU 1 CLK2 Period 2 CLK2 High Time: Am386SXLV CPU ...
Page 16
... SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges at 33 MHz V = 5 +100 C CC CASE Symbol Parameter Description Operating Frequency: Am386SX CPU Am386SXL CPU 1 CLK2 Period 2a CLK2 High Time 2b CLK2 High Time 3a CLK2 Low Time 3b CLK2 Low Time 4 CLK2 Fall Time 5 CLK2 Rise Time 6 A23– ...
Page 17
... SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges at 40 MHz V = 5 +100 C (Am386SX only) CC CASE Symbol Parameter Description Operating Frequency 1 CLK2 Period 2 CLK2 High Time 3 CLK2 Low Time 4 CLK2 Fall Time 5 CLK2 Rise Time 6 A23–A1 Valid Delay 7 A23–A1 Float Delay ...
Page 18
... V IHC CLK2 2 Figure 3. CLK2 Timing (Am386SXLV 25 MHz) t2a t2b V – 0 CLK2 2 Figure 4. CLK2 Timing (Am386SX/SXL 25 and 33 MHz – 0 CLK2 2 Figure 5. CLK2 Timing (Am386SX 40 MHz) Am386SX/SXL/SXLV CPU Output 18 Am386SX/SXL/SXLV Microprocessors Data Sheet ...
Page 19
... SWITCHING WAVEFORMS Tx CLK2 READY, SMIRDY* HOLD D15–D0 (Inputs) BUSY, ERROR, IIBEN*, PEREQ, FLT NA SMI*, INTR, NMI * – On Am386SXLV only Am386SX/SXL/SXLV Microprocessors Data Sheet t19, t19s* t20, t20s* t23 t24 t21 t22 t29 t30 t15 t27, t27s* t28, t28s* Figure 7 ...
Page 20
... CLK2 + + BHE , BLE BE3–BE0*, LOCK t10, t10s* W/R, M/IO, D/C, ADS, SMIADS* A23–A1 D15–D0 (Outputs) SMI* + HLDA + – On Am386SX/SXL only * – On Am386SXLV only 20 Am386SX/SXL/SXLV Microprocessors Data Sheet Min Max Valid n Valid n+1 Min Max Valid n Valid n+1 t6 Min Max ...
Page 21
... CLK2 W/R t12 D15–D0 Figure 9. Write Data Valid Delay Timing CLK2 W/R t12a D15–D0 Am386SX/SXL/SXLV Microprocessors Data Sheet Min Max Min Valid n Figure 10. Write Data Hold Timing Valid n 13605C–007 16305C–008 21 ...
Page 22
... BUSY should be held stable for eight CLK2 periods before and after the CLK2 period in which the RESET falling edge occurs self-test is requested, the Am386SXLV microprocessor outputs remain in their reset state as shown here. Figure 11. Bus Activity from Reset Until First Code Fetch (Am386SXLV Only) ...
Page 23
... Valid Data Valid Address Reset SMI Valid Figure 12. Entering and Exiting FLT (Am386SXLV Only CLK2 SMI SMIADS *Once initiated, the system must hold SMI Low until the first SMIADS. At this time, the system cannot drive SMI until three CLK2 cycles after the CPU drives SMI High. (The CPU will drive SMI High for two CLK2 cycles. The additional clock allows the CPU to completely release SMI and prevents any driver overlap ...
Page 24
... CLK2 t9 BHE, BLE, LOCK t11, t11s* W/R, M/IO, D/C, ADS, SMIADS* t7 A23–A1 D15–D0 t14f HLDA SMI* * – On Am386SXLV only Figure 15. Output Float Delay and HLDA and SMI* Valid Delay Timing 24 Am386SX/SXL/SXLV Microprocessors Data Sheet Cycle 1 Cycle ...
Page 25
... HLDA t32 SMI Figure 16. Output Float Delay Entering and Exiting FLT (Am386SXLV Only) CLK2 RESET The second internal processor phase following RESET High-to-Low transition (provided t25 and t26 are met Figure 17. RESET Setup and Hold Timing and Internal Phase ...
Page 26
... Output Valid Delay (ns) nom nom –3 nom –6 Note: This graph will not be linear outside the C Figure 19. Typical Output Valid Delay Versus Load Capacitance at Maximum Operating Temperature (C 26 Am386SX/SXL/SXLV Microprocessors Data Sheet nom 50 75 100 125 C (picofarads) L range shown. ...
Page 27
... Figure 20. Typical Output Valid Delay Versus Load Capacitance at Maximum Operating Temperature (C Rise Time (ns) 0.8 V – 2.0 V Note: This graph will not be linear outside the C Figure 21. Typical Output Rise Time Versus Load Capacitance Am386SX/SXL/SXLV Microprocessors Data Sheet 100 125 150 ...
Page 28
... DIFFERENCES BETWEEN THE Am386SX/SXL/SXLV AND Am386DX/DXL CPU The following are the major differences between the Am386SX/SXL/SXLV and the Am386DX/DXL CPU. For brevity, throughout this section the Am386SX/SXL/ SXLV CPU is referred to as the SX CPU, and the Am386DX/DXL CPU is referred to as the DX CPU. ...
Page 29
... Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance can be reduced by shorten- ing circuit board traces between the Am386SX/SXL/ SXLV CPU and decoupling capacitors as much as pos- sible. Resistor Recommendations ...
Page 30
... AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386 is a registered trademark; and E86 is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 30 Am386SX/SXL/SXLV Microprocessors Data Sheet 0.897 0.903 ...