93C56

Manufacturer Part Number93C56
Description93C562K 128 x 16 or 256 x 8 SERIAL MICROWIRE EEPROM
ManufacturerSTMicroelectronics
93C56 datasheet
 


1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
Page 5/12:

Erase All (ERAL)

Download datasheet (113Kb)Embed
PrevNext
3.4
ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. This cycle begins
on the rising clock edge of the last address bit.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
). DO at logical “0” indicates that program-
CSL
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
FIGURE 3-2:
ERASE TIMING
CS
CLK
1
1
A
DI
1
HIGH-Z
DO
FIGURE 3-3:
ERAL TIMING
CS
CLK
1
0
0
1
DI
HIGH-Z
DO
1998 Microchip Technology Inc.
3.5

Erase All (ERAL)

The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identical
to the ERASE cycle, except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences at the rising clock edge of the last address bit.
Clocking of the CLK pin is not necessary after the
device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (T
) and before the entire ERAL cycle is com-
CSL
plete.
T
CSL
•••
N
A
-1
A
-2
A0
N
N
T
WC
T
CSL
0
X
•••
X
T
EC
Preliminary
93C56A/B
CHECK STATUS
T
T
SV
CZ
BUSY
READY
HIGH-Z
CHECK STATUS
T
T
SV
CZ
BUSY
READY
HIGH-Z
DS21206B-page 5