CS82C52 Intersil Corporation, CS82C52 Datasheet
CS82C52
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CS82C52 Summary of contents
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... PART TEMP 1M BAUD MARKING RANGE (°C) CP82C52 CP82C52 0 to +70 CP82C52Z CP82C52Z 0 to +70 (Note) IP82C52 IP82C52 -40 to +85 CS82C5296 CS82C52 0 to +70 CS82C52Z* CS82C52Z 0to +70 (Note) IS82C52 IS82C52 -40 to +85 IS82C52Z* IS82C52Z -40 to +85 (Note) ID82C52 ID82C52 -40 to +85 MD82C52/B MD82C52/B -55 to +125 8501501XA 8501501XA MR82C52/B -55 to +125 ...
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Pinouts 82C52 (PDIP, CERDIP) TOP VIEW Block Diagram DATA ...
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Pin Description PIN ACTIVE SYMBOL NO. TYPE LEVEL Low Low D0-D7 3-10 I/O High A0 High IX, OX 13, 14 I/O SDO 15 O High GND 16 Low CTS 17 ...
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Pin Description (Continued) PIN ACTIVE SYMBOL NO. TYPE LEVEL SDI 25 I High High V 27 High CC CS0 28 I Low 4 82C52 82C52 SERIAL DATA INPUT: Serial data input to the 82C52 receiver circuits. A ...
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Reset During and after power-up, the 82C52 Reset Input (RST) must be held high for at least two IX clock cycles in order to initialize and drive the 82C52 circuits to an idle mode until proper programming can be done. ...
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The Prescaler design has been optimized to provide standard baud rates using any one of three popular crystal frequencies. By using one of these common system clock frequencies, 1.8432MHz, 2.4576MHz or 3.072MHz and Prescaler divide ratios of ÷3, ÷4, or ...
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SDI input and is not a resynchronized output. Also note that normal UART transmission via the Transmitter Register is disabled when operating in the Echo mode (see Figure 4). The Loop ...
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Parity Error (PE) Framing Error (FE) Overrun Error (OE) Received Break (RBRK) Modem Status (MS) Transmission Complete (TC) Transmitter Buffer Register Empty (TBRE) Data Ready (DR) FIGURE 5. USR Modem Status Register ...
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The transmitter always has the same word length and number of stop bits as the receiver. For words of less than 8 bits the unused bits at the microprocessor data bus are ignored by the transmitter ...
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C1 (NOTE) GND C2 (NOTE) NOTE 20pF For CL = 20pF 47pF For CL = 32pF FIGURE 10. 82C52 - 80C86 Interfacing The following example (Figure 11) shows the interface for an ...
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Absolute Maximum Ratings Supply Voltage ...
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AC Electrical Specifications V CC Timing Requirements and Responses SYMBOL PARAMETER (1) TSVCTL Select Setup to Control Leading Edge (2) TCTHSX Select Hold from Control Trailing Edge (3) TCTLCTH Control Pulse Width (4) TCTHCTL Control Disable to Control Enable (5) ...
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Timing Waveform CS0, A0 WRITE OPERATION D0-D7 RD READ OPERATION D0-D7 AC Test Circuit V1 R1 OUTPUT FROM DEVICE UNDER TEST 82C52 82C52 SELECT VALID (1) (3) (2) TSVCTL TCTLCTH TCTHSX (7) (8) TDVWH TWHDX ...
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UART Timing Characterization All parameters listed in this table were laboratory bench characterized at room temperature on a small sample of parts. No guarantee is implied. The main intent here is to clarify functional operation of the 82C52. 82C52 UART ...
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UART Timing Characterization IX CO(IX) CO(BRG) CO(BRG) TDTX (18) TX DATA CO(BRG) 8 CO(BRG) PERIODS RX DATA START BIT RX BAUD COUNTER STARTS HERE INTERNAL SAMPLE 15 82C52 82C52 TCHCL (11) TCLCH (10) (15) TS1 (16) TS2 TCY (17) FIGURE ...
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UART Timing Characterization 8/I 9/I 10/I CO(BRG) WR (19) TWLTL NOTE 1 TBRE SDO RD INTR CO(BRG) NOTE 4 CTS TBRE LAST STOP BIT SDO 16 82C52 82C52 (Continued) 11/I 12/I 13/I 14/I NOTE 2 LAST STOP ...
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UART Timing Characterization NOTES: 1. TBRE bit D6 in USR is updated each time TBRE changes state With TR initially empty, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after WR goes high. B. With TR initially ...
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UART Timing Characterization WR RTS/DTR RD DSR/CTS INTR NOTE 3 NOTES bit D7 in USR is updated each time DR changes state. TDRH always from trailing edge of 11th CO(BRG) in last Stop bit. 2. INTR on receive ...
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Burn-In Circuits GND VCC NOTES: = 5.5V ±0. GND = 0V = 4.5V ±10 ...
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... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...