K4H561638D-TCA2 Samsung, K4H561638D-TCA2 Datasheet

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DDR SDRAM DDR SDRAM Specification Version 1.0 REV. 1.0 November. 2. 2000 - 1 - ...

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DDR SDRAM Revision History Version 0 (May, 1998) - First version for internal review Version 0.1(June, 1998) - Added x4 organization Version 0.2(Sep,1998) 1. Added "Issue prcharge command for all banks of the device" as the fourth step of ...

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DDR SDRAM Revision History(continued) Version 0.7 (March, 2000) - Changed 128Mb spec from target to Preliminary version. - Changed partnames as follows. from KM44L32031BT-G(L)Z/Y/0 KM48L16031BT-G(L)Z/Y/0 KM416L8031BT-G(L)Z/Y/0 - Changed input cap. spec. from CK/CK 2.5pF ~ 3.5pF DQ/DQS/DM 4.0pF ~ ...

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DDR SDRAM Contents Revision History General Information 1. Key Features 1.1 Features 1.2 Operating Frequencies 2. Package Pinout & Dimension 2.1 Package Pintout 2.2 Input/Output Function Description 2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension 3. Functional Description 3.1 Simplified ...

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DDR SDRAM 3.3.7 Write Interrupted by a Read & DM 3.3.8 Write Interrupted by a Precharge & DM 3.3.9 Burst Stop 3.3.10 DM masking 3.3.11 Read With Auto Precharge 3.3.12 Write With Auto Precharge 3.3.13 Auto Refresh & Self ...

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DDR SDRAM List of tables Table 1 : Operating frequency and DLL jitter Table 2. : Column address configurtion Table 3 : Input/Output function description Table 4 : Burst address ordering for burst length Table 5 : Bank selection ...

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DDR SDRAM List of figures Figure 1 : 128Mb Package Pinout Figure 2 : Package dimension Figure 3 :State digram Figure 4 : Power up and initialization sequence Figure 5 : Mode register set Figure 6 : Mode register ...

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... K4H281638B-TCA2 8Mx16 K4H281638B-TLA2 Memory DRAM Small Classification Density and Refresh Organization Bank 1. SAMSUNG Memory : K 2. DRAM : 4 3. Small Classification H : DDR SDRAM 4. Density & Refresh 64 : 64M 4K/64ms 28 : 128M 4K/64ms 56 : 256M 8K/64ms 51 : 512M 8K/64ms 16K/32ms 5. Organization ...

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DDR SDRAM 1. Key Features 1.1 Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK ...

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DDR SDRAM 1. Package Pinout & Dimension 2.1 Package Pinout DDQ SSQ DDQ ...

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DDR SDRAM 2.2 Input/Output Function Description SYMBOL TYPE CK, CK Input CKE Input CS Input RAS, CAS, WE Input LDM,(U)DM Input BA0, BA1 Input Input DQ I/O LDQS,(U)DQS I/O QFC Output ...

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DDR SDRAM 2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10×) Figure 2. Package dimension - ...

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DDR SDRAM 3. Functional Description 3.1 Simplified State Diagram MODE REGISTER SET POWER POWER APPLIED REFS MRS IDLE CKEH POWER ACT DOWN CKEL CKEH ROW ACTIVE WRITE WRITEA READA READ WRITEA WRITE WRITEA READA PRE WRITEA PRE PRE PRE ...

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DDR SDRAM 3.2 Basic Functionality 3.2.1 Power-Up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state(all other inputs may be undefined.) - Apply ...

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DDR SDRAM 3.2.2 Mode Register Definition 3.2.2.1 Mode Register Set(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various ...

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DDR SDRAM Burst Length Address(A2, A1, A0 Table 4. Burst address ordering for burst length DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returing to ...

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DDR SDRAM 3.2.2.2 Extended Mode Register Set(EMRS) The extended mode register stores the data for enabling or disabling DLL, QFC and selecting output driver size. The default value of the extended mode register is not defined, therefore the extened ...

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DDR SDRAM 3.2.3 Precharge The precharge command is used to precharge or close a bank that has been activated. The precharge com- mand is issued when CS, RAS and WE are low and CAS is high at the rising ...

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DDR SDRAM 3.2.5 Row Active The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The DDR SDRAM has four independent banks, so two Bank ...

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DDR SDRAM 3.3 Essential Functionality for DDR SDRAM The essential functionality that is required for the DDR SDRAM device is described in this chapter 3.3.1 Burst Read Operation Burst Read operation in DDR SDRAM is in the same manner ...

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DDR SDRAM 3.3.2 Burst Write Operation The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The address inputs determine the starting column address. There ...

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DDR SDRAM 3.3.3 Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are overridden by the ...

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DDR SDRAM 3.3.5 Read Interrupted by a Precharge A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable ...

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DDR SDRAM 3.3.6 Write Interrupted by a Write A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restric- tion that the interval that separates the commands must be at ...

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DDR SDRAM 3.3.7 Write Interrupted by a Read & burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the ...

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DDR SDRAM 3.3.8 Write Interrupted by a Precharge & burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time(tWR) is ...

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DDR SDRAM 3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where tWR+tRP starts on the falling DQS edge that strobed in the last valid data and ...

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DDR SDRAM 6. When terminating a burst Read command, the BST command must be issued L cycles before the clock edge at which the output buffers are tristated, where L for read operations. This is shown in previous page ...

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DDR SDRAM 3.3.11 Read With Auto Precharge If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the ...

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DDR SDRAM 3.3.12 Write with Auto Precharge If A10 is high when write command is issued , the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge ...

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DDR SDRAM 3.3.13 Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the ris- ing edge of the clock(CK). All banks ...

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DDR SDRAM 3.3.14 Power down The power down mode is entered when CKE is low and exited when CKE is high. Once the power down mode is initiated, all of the receiver circuits except clock, CKE and DLL circuit ...

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DDR SDRAM 4. Command Truth Table COMMAND Register Extended MRS Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto ...

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DDR SDRAM 5. Functional Truth Table Current State CS RAS CAS PRECHARGE L H STANDBY ACTIVE L H STANDBY ...

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DDR SDRAM Current State CS RAS CAS WRITE READ with L H AUTO PRECHARGE L H (READA ...

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DDR SDRAM Current State CS RAS CAS PRECHARG ING L H (DURING tRP ROW L H ACTIVATING L H (FROM ROW L L ACTIVE tRCD) L ...

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DDR SDRAM Current State CS RAS CAS RE FRESHING MODE L H REGISTER L H SETTING Address H ...

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DDR SDRAM CKE CKE Current State n-1 n SELF REFRESHING POWER L H DOWN L L ALL BANKS IDLE H L ...

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DDR SDRAM 6. Absolute Maximum Rating Parameter Voltage on any pin relative to V Voltage on V supply relative Voltage on V supply relative to V DDQ Storage temperature Power dissipation Short circuit current Note : ...

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DDR SDRAM 7.2 DDR SDRAM SPEC Items and Test Conditions Conditions Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing ...

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DDR SDRAM 7.3 DDR SDRAM I DD 32Mx4 K4H280438B-TCA2 (DDR266A) Symbol typical IDD0 85 IDD1 125 IDD2P 21 IDD2F 40 IDD2Q 30 IDD3P 25 IDD3N 35 IDD4R 140 IDD4W 125 IDD5 185 IDD6 Normal 2 Low power 1 IDD7 ...

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DDR SDRAM 8Mx16 K4H281638B-TCA2 (DDR266A) Symbol typical IDD0 90 IDD1 140 IDD2P 21 IDD2F 40 IDD2Q 30 IDD3P 25 IDD3N 45 IDD4R 210 IDD4W 150 IDD5 195 IDD6 Normal 2 Low power 1 IDD7 300 Table 12. 128Mb DDR ...

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DDR SDRAM DD7 I : Operating current: Four bank operation 1. Typical Case : Vdd = 2.5V, T=25’ Worst Case : Vdd = 2.7V, T= 10’ Four banks are being interleaved with tRC(min), Burst Mode, ...

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DDR SDRAM 8.2 AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to ...

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DDR SDRAM Parameter Exit self refresh to bank active command tXSA Exit self refresh to read command Refresh interval time 64Mb, 128Mb 256Mb Output DQS valid window Clock half period DQS write postamble time QFC setup to first DQS ...

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DDR SDRAM 9. AC Operating Test Conditions (V =2.5V, V =2.5V DDQ A Parameter Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate Input Levels(V /V ...

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DDR SDRAM 11. IBIS: I/V Characteristics for Input and Output Buffers 11.1 Normal strength driver 1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. ...

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DDR SDRAM Pulldown Current (mA) Typical Typical Voltage (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 43.7 49.8 0.9 47.5 55.2 1.0 ...

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DDR SDRAM 11.2 Half strength driver 1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The full variation in driver pulldown current from ...

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DDR SDRAM Pulldown Current (mA) Typical Typical Voltage (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.6 22.1 0.7 22.3 25.0 0.8 24.7 28.2 0.9 26.9 31.3 1.0 ...

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DDR SDRAM 12. QFC function QFC definition when drive low on reads coincident with the start of DQS, this DRAM output signal says that one cycle later there will be the first valid DQS output and returned to HI-Z ...

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DDR SDRAM QFC timing on Write operation QFC on writes is enabled as soon as possible after the clock edge of write command and disabled as soon as possible after the last DQS-in low going edge ...

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DDR SDRAM QFC timing example for interrupted Writes operation Command Write DQS DQ’ S Hi-Z QFC t QCSW Figure 29. : QFC timing example for Interrupted writes operation Precharge Dout 2 Dout ...