PEB2091NV5.3 Siemens Semiconductor Group, PEB2091NV5.3 Datasheet
PEB2091NV5.3
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PEB2091NV5.3 Summary of contents
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ICs for Communications ISDN Echocancellation Circuit IEC-Q PEB 2091 Version 5.3 PEF 2091 Version 5.3 Data Sheet 01. ...
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PEB/F 2091 Revision History: Previous Version: Page Page (in previous (in current Version) Version) ® ® ® ABM , AOP , ARCOFI , ARCOFI ® ® ® FALC 56, FALC -E1, FALC -LH, IDEC ® ® ® ISAC -P TE, ...
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Table of Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.2.2.9 Miscellaneous Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 2.2.2.10 ...
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Table of Contents 3.7.6 Microprocessor Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 ...
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Table of Contents 4.4.2 State Machine in LT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 5.2.1 ISTA-Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 7 Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents Appendix A Basic Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Logic Symbol for µP Mode ...
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List of Figures Figure 41 C/I Channel Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 83 Serial Data Port of Pin PS2 in LT Modes . . . . . . . . . . . . . . . . . . . . . . .195 Figure 84 Sampling ...
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List of Figures Figure 126 Package Outline for M-QFP- .288 Figure ...
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List of Tables Table 1 Microprocessor Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ...
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List of Tables Table 43 MON-1 S/Q-Channel Commands and Indications . . . . . . . . . . . . . . . 227 Table 44 MON-1 M-Bit Commands ...
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Preface The ISDN Echocancellation Circuit for the 2B1Q line code (IEC- U-interface transceiver for level 1 basic access subscriber lines covering a wide range of applications related to this function. This data sheet describes the properties of the ...
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Chapter 7, Application Hints Describes the external circuitry needed and gives useful hints for some applications. • Chapter 8, Electrical Characteristics Specifies the statical and dynamical characteristics of the device’s inputs and outputs, its maximum rating, power supply, power ...
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Overview Version 5.3 of the PEB/F 2091 (IEC-Q optimized version of the IEC-Q, which features all functions needed for building basic rate digital subscriber line systems. It complies to all international and all important national standards (e.g. ...
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ISDN Echocancellation Circuit IEC-Q Version 5.3 1.1 Features • ISDN U transceiver microprocessor interface control • Pin and functionally compatible to all previous PEB 2091 versions • Perfectly suited to all LT, NT, TE, DAML, Repeater, NT-PBX and Wireless Local ...
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IOM • Adjustable microcontroller clock source between 0.96MHz and 7.68MHz • Selection between Bit clock (BCL) and Data clock (DCL) • Supports synchronization of base stations in Wireless Local ...
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Logic Symbol for µP Mode +5V PMODE Clock CLS FSC* DCL* ® IOM -2 DOUT Interface DIN AD0-AD7 *) FSC and DCL are ® inputs in the IOM -2 Slave mode and ® outputs from the IOM -2 Master ...
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Logic Symbol for Stand-Alone Mode 0V PMODE Clock CLS FSC* DCL* IOM-2 Interface DOUT DIN ® DOD IOM -2 Control MTO PCD0-2 *) FSC and DCL are ® inputs in the IOM -2 Slave mode and ® outputs from ...
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System Integration The PEB/F 2091 can be combined with a variety of other devices to fit in numerous applications. Some of the typical 1.5.1 PCM 2 Systems U Interface Figure 3 COT Application SICOFI PEB 2266 V1.4 Figure 4 ...
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PCM 4 with FAX/Modem Features a/b a/b ® SICOFI -4 µC PEB 2466 a/b a/b Figure 5 PCM 4 Application 1.5.3 Repeater The IEC-Q offers several special features to allow simple and cost effective design of repeaters. Beside the ...
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U Interface Upstream Figure 6 Architecture of Repeater Application 1.5.4 Wireless Local Loop In Figure 7 an example for base station configuration is sketched. The PEB/F 2091 Version 5.3 is designed to suit to PEB 24911/PEB 24902 (DFE-Q/AFE) in the ...
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Burst Mode Air Interface Controller Figure 7 Architecture of the Wireless Local Loop Base Station 1.5.5 TE Applications One example for terminal application is the ISDN feature phone. Figure 8 TE Application Semiconductor Group ® IOM -2 SG ® IOM ...
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Dual Mode U and S Terminals and PC Cards In this application the IOM master mode. This allows introduction of dual mode terminals and PC adapter cards using e.g. IPAC. See 3.2.4, page 53 for details. S Interface Figure ...
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NT-PBX Upstream U Interface PEB/F 2091 U PEB/F 2091 Interface Figure 10 NT-PBX Application Semiconductor Group ® IOM -2 IEC-Q 1 IDEC PEB 2075 IDEC PEB 2075 8 IEC-Q µP i/f (Optional) Microprocessor 28 ® ® PCM PBX EPIC ...
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LT Application and Access Network Note 1: For LT applications in general it is recommended to use the device kit PEB 24911 / PEB/F 24902 (Quad IEC DFE-Q/AFE), which offers the same function for four metallic lines. In some ...
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NT1 Note 2: In new designs the IEC-Q is not recommended for this application more cost effective and more convenient to use PEB/F 8091 in this application. As the PEB/F 8091 combines the functionality of SBC-X and ...
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Pin Descriptions The PEB/F 2091 is available in three packages, P-LCC-44, T-QFP-64 and M-QFP-64. The detailed pin configurations of these three packages are given in section 2.1 below. Section 2.2 on page 32 provides a detailed definition and a ...
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T-QFP-64 and M-QFP-64 Packages Figure 14 ...
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Pin Definition in Stand-Alone Mode (i.e. PMODE="0" or unconnected) Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 2.2.1.1 Mode Selection Pins 12 24 PMODE 28 47 RES 3 10 TSP BURST Semiconductor Group Input ...
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Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 33 55 TS0 35 58 TS1 36 59 TS2 18 35 AUTO 2.2.1.2 Power Supply Pins GNDA1 ...
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Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 ® 2.2.1.3 IOM -2 Pins 31 53 DCL 30 52 FSC 26 45 DIN 27 46 DOUT ® 2.2.1.4 IOM -2 Control Pins 17 32 DOD 34 57 MTO Semiconductor Group Input ...
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Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 2.2.1.5 U-Interface Pins 15 29 AIN 14 28 BIN 6 16 AOUT 4 13 BOUT 2.2.1.6 Power Controller Pins 44 5 PCD0 43 4 PCD1 42 3 PCD2 39 62 PCA0 38 ...
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Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 37 60 DISS 21 38 PS1 22 39 PS2 2.2.1.7 Clocks 10 22 XOUT Semiconductor Group Input (I) Function Output (O) O Disable power supply: Different function in LT and NT modes. ...
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Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 11 23 XIN 32 54 CLS Semiconductor Group Input (I) Function Output (O) I Crystal IN: External 15.36-MHz clock signal or 15.36-MHz crystal is connected. In case a crystal is connected, suitable ...
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Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 2.2.1.8 Miscellaneous Function Pins Not 64 ICE available Not 42 SG available 2.2.1.9 Test Pins TP1 Semiconductor Group Input (I) Function Output (O) ® I IOM -2 ...
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Pin Definition in Microprocessor Mode (i.e. PMODE="1") Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 2.2.2.1 Mode Selection Pins 12 24 PMODE 28 47 RES 2.2.2.2 Data, Address and µP Selection Pins 24 43 SMODE A0 SMODE 36 59 ...
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Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 35 58 CDOUT A2 not used 33 55 not used I A3 not used 44 5 not used I/O D0 AD0 43 4 not used I/O D1 AD1 42 3 not used ...
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Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 39 62 not used I/O D5 AD5 38 61 not used I/O D6 AD6 25 44 not used I/O D7 AD7 2.2.2.3 µP Control Pins 19 36 INT ...
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Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 34 57 not used CCLK (Mode Select) ALE 2.2.2.4 Power Supply Pins GNDA1 ...
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Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 ® 2.2.2.5 IOM -2 Pins 31 53 DCL 30 52 FSC 26 45 DIN 27 46 DOUT 2.2.2.6 U-Interface Pins 15 29 AIN 14 28 BIN 6 16 AOUT 4 13 BOUT ...
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Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 2.2.2.7 Power Controller Pins 21 38 PS1 22 39 PS2 2.2.2.8 Clocks 10 22 XOUT Semiconductor Group Input (I) Function Output (O) I Power status (primary): Different function in LT and NT ...
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Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 11 23 XIN 32 54 CLS 37 60 MCLK 2.2.2.9 Miscellaneous Function Pins 18 35 RST Semiconductor Group Input (I) Function Output (O) I Crystal IN: External 15.36-MHz clock signal or 15.36-MHz ...
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Pin No. Pin No. Symbol P-LCC-44 T-QFP64 M-QFP64 Not 64 ICE available Not 42 SG available 2.2.2.10 Test Pin Semiconductor Group Input (I) Function Output (O) ® I IOM -2 Clocks Enable ® In IOM -2 Master ...
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Microprocessor Bus Interface (Overview) The table below gives an overview of the different microprocessor bus modes. Table 1 Microprocessor Bus Interface Pin Number Stand-Alone Mode P-LCC-44 T-QFP-64 and M-QFP- PMODE = PCD0 43 4 ...
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Functional Description Interfaces and functional blocks of the PEB/F 2091 V5.3 differ depending on the mode used, i.e. depending on whether the stand-alone mode or the microprocessor mode is being used. Section 3.1 defines these two modes and gives ...
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R IOM -2 Figure 15 Stand-Alone Mode (left) and µP Mode (right) In µP mode B channels, D channel, C/I codes and Monitor commands can either be passed between the U transceiver and IOM the µP via the PI. Any ...
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Table 2 Setting Modes of Operation (Stand-Alone and µP Mode) Mode Selection Stand-Alone Mode/µP Mode 1) Mode Burst NT-Auto 0 0 Activation NT-PBX ...
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Table 3 Setting IOM ® 1) IOM -2 TS2 TS1 Channel No ...
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Table 4 Setting Test Modes Test-Mode 1) Master-Reset 2) Send Single-Pulses 3) Data-Through Normal Operation 1) Used for Quiet Mode and Return Loss measurements 2) Used for Pulse Mask measurements 3) Used for Insertion Loss, Power Spectral Density and Total ...
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Table 6 Setting DOUT Driver in µP Mode Mode Pin RES Normal 1 (Tristate) Normal 1 4) (Open Drain ) 1) See also "ADF2-Register", page 214 2) Refer to Notes 10, page 72, 12, page 72, and 15, page 73 ...
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Active means that the behavior former versions of the IEC-Q. The IOM FSC and DCL are output on the corresponding pins. Due to the 100 kOhm pull-up resistor this is the default configuration after reset if pin ...
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Table 8 Setting EOC Mode EOC Mode Transparent Automatic function transfers the Monitor Channel into the idle state thereby resolving possible lock-up situations. It therefore used in all systems where capable of detecting and ...
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Setting the ADF:BCL bit to ’1’ will change DCL frequency to the bit data rate, dividing the default DCL frequency by 2. Note 6: Setting this mode will change the output frequency on pin DCL. Internally, ...
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Block Diagram Microprocessor Mode In the microprocessor mode the following interfaces and functional blocks are used. For an overview of block functions refer to sections 3.4 through 3.15. *) Available only in M-QFP-64 and T-QFP-64 packages Figure 16 Device ...
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Stand-Alone Mode In stand-alone mode the following interfaces and functional blocks are used. For an overview of block functions refer to sections 3.4 through 3.15. *) Available only in M-QFP-64 and T-QFP-64 packages Figure 17 Device Architecture in Stand-Alone Mode ...
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Transceiver Core The U transceiver establishes the direct link between the exchange and the terminal side over two copper wires. Transmission over the U-interface is performed at a rate of 80 kBaud. Two binary informations are coded into one ...
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Figure 18 U Transceiver Block Diagram Semiconductor Group Functional Description 61 PEB 2091 PEF 2091 Data Sheet 01.99 ...
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U transceiver can be subdivided in three main blocks: SIU System Interface Unit REC Receiver LIU Line Interface Unit 3.4.1 System Interface Unit The System Interface Unit (SIU) provides the link between the different interfaces of the ® IEC-Q, ...
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Transmitter Scrambler in NT, NT-PBX and TE Mode without Loop-Back Transmitter Scrambler for all LT Modes and for Loop-Back 3 in all NT Modes - Receiver Descrambler for all LT Modes and ...
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Control Block Complete activation and deactivation procedures are implemented, which are controlled by activation and deactivation indications from U, IOM transition of the procedures depend on the actual status of the Receiver (adaptation and synchronization) and timing functions to watch ...
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The check digits (CRC bits CRC1, CRC2, …, CRC12) generated are transmitted at position M5 and M6 in the U-superframe (see "U-Frame Structure", page 68). At the receiving side this value is compared with the value calculated from the received ...
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The shape of a DAC-output signal is shown below, the peak amplitude is normalized to one. This signal is fed to an RC-lowpass of first order with a corner frequency of 1 MHz 50%. 1.0 0.75 0.5 0.25 ...
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U-Interface The IEC-Q interfaces with the metallic line through this block. Both are linked by an external circuitry consisting of a transformer and a hybrid circuitry (refer to Figure 93, page 250 for details). 3.5.1 Output and Input Signals ...
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Table 10 U-Frame Structure Framing Overhead Bits (M1 – M6) Quat 1 – 9 Positions Bit 1 – 18 Positions Super Basic Sync Frame # Frame # Word 1 1 ISW ...
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Embedded Operations Channel (EOC) EOC-data are available in the U-frame at the positions M1, M2 and M3 thereby permitting the transmission of two complete EOC-messages (2 U-superframe. The EOC contains an address field, a data/message indicator (d/m) and an eight-bit ...
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Interface IOM ® The IOM -2 interface is used to interconnect telecommunication ICs. It provides a symmetrical full-duplex communication link, containing user data, control/programming and status channels. The structure used follows the 2B + 1D-channel structure of ...
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Within one FSC-period, 32 bit up to 256 bit are transmitted, corresponding to DCL-frequencies ranging from 512 kHz up to 4096 kHz. ® Three optimized IOM -2 timing modes exist for: Multiplexed Timing Mode Plain Timing Mode (NT, NT-Auto Activation, ...
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DIN. The IEC-Q is assigned to an individual channel by pin strapping (see "Setting Operating Modes", page 50). Note 10: This assigned channel is called the ’active channel’ of the IEC-Q. All other channels, if available, ...
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The IOM -2 signals are: DIN, DOUT 256 kbit/s DCL 512 kHz FSC 8 kHz FSC Figure 26 Plain Frame Structure of the IOM 3.6.1.3 Terminal Timing Mode Note 13: This timing applies to the ...
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FSC R IOM Channel MON0 MON0 Figure 27 Terminal Frame Structure of the IOM ® – C/I0 in IOM -2 Channel two bits for the 16 ...
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S/G-bit (Stop/Go), available to a connected HDLC controller to determine if it can access the D-channel (S stop, S go). A/B-bit (available/blocked), supplementary bit for D-channel control. (A ...
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C/I Channel 1 C/I Channel 1 (C/I1) is only available in TE mode (DCL = 1.536 MHz). The channel consists of six bits in each direction. In stand-alone mode the C/I1 channel is ignored by the U transceiver. In ...
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The first four bits of this two byte message gives the address of the Monitor message. This address defines the type of the Monitor message. Example: A Monitor message with an address ’0 MON-0 message. A Monitor message with an ...
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M 1/2:Monitor message 1. and 2. byte R 1/2:Monitor response 1. and 2. byte EOM:End of message: MX=’1’ and MR=’1’ in two consecutive IOM R IOM -2 Frame No 1.Byte DIN Mon. ...
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R IOM -2 Frame DIN DOUT Figure 29 Abortion of Monitor Channel Transmission Example: Standard Transmission Procedure in stand-alone mode 1. The first byte of monitor data is placed by the external controller (e.g. ICC, EPIC the DIN line of ...
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Procedure Time-Out (MTO)", page 55. Figure 28, page 78 illustrates the case where the response can be sent immediately. The procedure for the response is similar to that described in ...
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Receive 1 isw U Frame Superframe Marker R IOM Frame 12 1 Possible Start of Monitor Procedure Reset Figure 30 Monitor Access with MTO Enabled Monitor Channel Transmitter and MTO Enabled The transmitter is reset intervals in ...
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Activation/Deactivation of IOM Note 18: This section applies only in the NT, NT-Auto Activation, NT-RP and TE modes. ® The IOM -2 clocks may be switched off if the IEC state ’Deactivated’ (see "State Machine in NT ...
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CIWU:SPU is set to ’0’ or • a wake-up tone is detected on the U-interface DCL is activated such that its first rising edge occurs with the beginning of the bit following the C/I0 channel. After the ...
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LT Mode U Interface LT U Interface LT U Interface LT Synchr. ( Downstream Figure 32 Clock Generation for LT Mode The LT mode is typically chosen for ISDN-line card applications. The U transceiver has to synchronize onto an ...
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The dynamic characteristics of this clock are described in "LT Modes", page 281. Clock CLS This clock is not defined in this mode. 3.7.2 NT and TE Mode XIN XOUT CLS=7680 kHz FSC=8 kHz NT DCL=512 kHz Synchr. (Downstream) Figure ...
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NT-PBX U Interface U Interface U Interface Synchr. (Downstream) Figure 34 Clock Generation in NT-PBX Mode ® In NT-PBX mode IOM -2 clock signals are not issued by the device but need to be generated externally. In order to ...
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Note 19: It may be necessary to use a multiplexer for the PLL-reference clock because the CLS-signal is available only if the corresponding line is active. If the referenced line is not active the PLL must be supplied by the ...
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NT Repeater XIN/XOUT A free running crystal or other clock source shall provide a 15.36-MHz base clock (see also "External Circuitry", page 249 for more informations about crystal properties). CLS In this mode version 5.3 provides an unsychronized 15.36 ...
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IEC-Q issues all IOM -2 clocks. An external clock generation circuit is not required. Information on the U-interface is transmitted synchronous to the system clock. XIN/XOUT A free running crystal or other clock source should provide a 15.36-MHz base ...
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Microprocessor Interface Note 21: This Interface is only available in the microprocessor mode. The parallel/serial microprocessor interface can be selected to be either of the 1. Siemens/Intel non-multiplexed bus type with control signals CS, WR Motorola type ...
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S/G Status Indication on Pin SG If one of the packages M-QFP-64 or T-QFP-64 is being used the S/G bit status information will be additionally provided on pin SG, see "Miscellaneous Function Pins", page 46. This feature is not available ...
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Power Status Two pins PS1 and PS2 are available for comfortably surveying and controlling the power status. In addition, if the stand-alone mode is being used, a third pin (DISS) is also available mode, power status bits ...
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Vdd 1.0V RST Figure 37 UVD Control of Pin RST While the supply voltage is below threshold U stopped and the MCLK output remains low U , the clock is stopped immediately which may result in ...
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This is independent of mode setting. However there is a difference in reset duration and indication between the stand-alone mode and the microprocessor mode. In stand-alone mode this internal reset (POR) will be fully equivalent to the hardware reset ...
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The clock MCLK is delivered during reset (except for power-on and undervoltage detection). Table 13 shows that the output pin RST is controlled by power-on reset, undervoltage detection and the watchdog timer. Figure 38 illustrates the reset sources that have ...
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Operational Description In chapters 2 and 3 the pins and user’s interfaces of the IEC-Q are described in detail. Using this information, this chapter describes the interaction between these interfaces in detail. The approach used is to describe how ...
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Microprocessor Access to Note 27: This chapter applies only in µP mode. In µP mode the microcontroller has access to the IOM interface (PI) and registers Figure 39 Access to IOM The processor interface can be understood ...
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Note 28: The microprocessor interface provides almost unlimited access possibilities to the active IOM is that all actions described in this document involving the active channel of the IOM channels) can be also performed using the PI. ® In the ...
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D-Channel Access Setting SWST:D to "1" enables the microprocessor to access D-channel data between ® the IOM -2 and the transceiver core. Four registers (see Table 15) handle the transfer of data from IOM ® µP to IOM -2, ...
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C/I Channel Access Setting SWST:CI to "1" enables the microprocessor to access C/I-commands and indications between IOM A change in two consecutive frames (double last look) in the C/I-channel on IOM indicated by an interrupt ISTA:CICI. The received C/I-command ...
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C Bit) C/I (4 Bit) CIRI CIWI CIRU CIWU R C/I access to IOM -2 channel 0 Figure 41 C/I Channel Access 4.1.4 Monitor Channel Access Setting SWST:MON to "1" enables the microprocessor to access Monitor-channel ® messages ...
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DIN DOUT P Interface SWST : MON = 0 MODE 1 : Monitor Channel access disabled DIN R IOM -2 Channel 0 DOUT P Interface SWST : MON = 1 ADF2 : MIN = 0 ADF2 : TE1 = 0 ...
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Monitor Channel Protocol The PI allows to program the IEC-Q Monitor Channel in the way known from the PEB 2070 (ICC). The Monitor Channel operates on an asynchronous basis. While data transfers on the ® IOM -2-bus occur synchronized ...
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P MXE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 MDA Int. MOX = DATA2 MDA Int. MXC = 0 MAC = 0 Figure 43 Monitor Channel Protocol Before starting a transmission, ...
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Alerted by the MDR interrupt, the microprocessor reads the Monitor Receive (MOR) register. When it is ready to accept data (e.g. based on the value in MOR, which in a point-to-multipoint application might be the address of the destination device), ...
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Access to U-Interface The U-frame is not directly accessible by the user. Communication with the U-interface will be established using the user interfaces IOM shows how this can be done for both receive and transmit directions. Figures 44 and ...
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Data During normal operation (i.e. transparent transmission and no test mode) the 2B+D channels can be accessed via the IOM page 108 for details. EOC Basically the EOC channel can be accessed via MON-0 messages. However, internal processing, manipulation and ...
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Single Bits User access to the Single Bits (SB) channel is mode dependent. In transmit direction there are five possible sources for setting (different) SB: MON-1 messages, MON-2 messages, MON-8 messages, the pins PS1 and PS2 and the state machine. ...
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Data Access in LT Mode In LT modes (see "Setting Operating Modes", page 50) transparent data access is available in both directions in the states: LT Pending Transparent Transparent Pending Deactivation Line Active S/T Deactivated i.e. when the IEC-Q issues ...
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M5-M6 2 Bit Time Figure 47 Access to Data Received from U 4.2.2 Access to EOC of U-Interface The MON-0-commands provide access to device internal EOC-registers. Via MON-0 the EOC overhead bits of the U-interface are controlled. This access is ...
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Transmitter Data (To U) MON-0 ® From IOM -2 Processor or µP Figure 48 Access to EOC Transmission on U M5-M6 2 Bit Time Figure 49 Access to EOC Received from U In other states the EOC-processor clamps all EOC-maintenance ...
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MON-0-commands may be passed at any instant and need to be transferred only once (applicable for Auto and Transparent mode). Code repetition is performed within the chip by the EOC processor. A summery of the EOC procedure in EOC Auto ...
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Table 19 Predefined EOC Messages 53 RCC Request corrupt CRC 54 NCC Notify of corrupt CRC AA UTC Unable to comply FF RTN Return to normal XX Acknowledge If a command is declared as data (d/m = (0)), the IEC-Q ...
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MON-0 EOC IOM - Execute R IOM -2 MON-0 EOC A: Auto-Mode T: Transparent-Mode Figure 50 EOC-Procedure in Auto and Transparent Mode Semiconductor Group M1, M2, M3, EOC U A Echo ...
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Access to the Single Bits of U-Interface The transmission procedure of the Single Bits (SB) on the U-interface is mode dependent. The reception procedure of the SB from the U-interface is independent the mode used. Transmission and reception of ...
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SB channel will be set to "1", which is the default value after the signal SL2 in the LT modes and SN3 in the NT modes are issued on the U-interface (see state machines, ...
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Table 21 Single Bits Control in NT Modes (Upstream) M61 1 M42 PS1 M52 1 M62 FEBE M43 PS2 M44 NTM M45 CSO M46 1 M47 SAI M48 1 Table 22 Function of the Predefined Modes Bit ...
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Table 22 Function of the Predefined Modes Bit Function PS1 (Power Status Primary Source) The PS1-bit is used to indicate the status of the primary NT power supply set to (1) if the level at ...
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Table 23 Single Bits Control in LT Modes (Downstream) Position MON-2/U Bit M41 ACT M51 1 M61 1 M42 DEA M52 1 M62 FEBE M43 1 M44 1 M45 1 M46 1 M47 UOA M48 1 Table 24 Function of ...
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SB Transmission in Repeater Modes Note 36: This section applies to NT-RP and NT-RP modes (see "Basic Operating Mode", page 50). In these modes all of the Single Bits need to be controlled via MON-2-messages. This permits to implement national ...
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The last setting for the M4 bits complies with ANSI T1.601 without need for further software efforts. Note that this is the default setting for the M4 bits in all non repeater modes (see Table 26). Note also that this ...
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Verification Control for M4 Bits Table 26 gives the available settings for M4 Bits filtering via MON-8 command. Table 26 Setting Filtering Method for M4 Bits Code Symbol 1) D7-D0 (Bin) 1000 1110 TLL (Default, not RP) 1000 1101 CRC ...
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Verification Control for Additional Overhead Bits Table 27 gives the available settings for Additional Overhead Bits (M51, M52, M61) filtering via MON-8 command. Table 27 Setting Filtering Method for Additional Overhead Bits Code Symbol 1) D7-D0 (Bin) 1000 1010 TLL ...
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Setting Superframe Marker In the NT and TE modes, with superframe marker selected (see "Setting Modes of Operation (Stand-Alone and µP Mode)", page 51) the start of a new superframe is indicated with a FSC high-phase lasting for one ...
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Layer 1 Activation and Deactivation The IEC-Q is designed to meet the newest standards of ANSI and ETSI regarding status control. The following sections describe some of the most important protocols implemented in the IEC-Q. They illustrate the interaction ...
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Complete Activation Initiated by LT Figure 53 depicts the procedure if the activation has been initiated by the exchange side. If activation is initiated with the C/I code AR, as shown in Figure 53, activation will fail if the ...
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Activation with ACT-Bit Status Ignored by the Exchange Side Activation with C/I-command "AR0" forces the state machine into the state "Line Active" independently of the ACT-bit status transmitted upstream from the network. Activation may be completed after the ACT-bit ...
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Complete Activation Initiated by TE Figure 55 depicts the procedure if the activation has been initiated by the terminal side. S/T IOM -2 INFO 0 DC INFO 0 DI INFO 1 TIM INFO 2 INFO ...
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Complete Deactivation S/T IOM -2 INFO 4 AI INFO INFO 0 INFO SBCX NT Figure 56 Complete Deactivation Semiconductor Group R U-Reference Point SL3T act = 1 dea = 1 uoa =1 ...
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Partial Activation (U Only) The IEC the "Synchronized 1" state (see "State Machine in NT Modes", page 160) after a successful partial activation. IOM the C/I-message "DC" as well as the LT user data is sent. While ...
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Activation Initiated by LT with U Active The S-interface is activated from the exchange with the command "AR". Bit "UOA" changes to (1) requesting S-interface activation. S/T IOM -2 INFO 0 DC INFO INFO 2 AR ...
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Activation Initiated by TE with U Active The TE initiates complete activation with INFO 1 leading to "SAI" = (1). Case 1 requires the exchange side to acknowledge the TE activation by sending C/I = "AR", Case 2 activates ...
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S/T IOM -2 INFO 0 DC INFO 0 DI INFO INFO 2 INFO INFO 4 SBCX NT Figure 60 TE Activation with U Active and no Exchange Control (case 2) Semiconductor Group R U-Reference ...
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Deactivating S/T-Interface Only Deactivation of the S-interface without deactivating the U-interface is initiated from the exchange by setting the "UOA" bit = (0). S/T IOM -2 INFO 4 INFO 3 INFO 0 INFO 0 SBCX Figure 61 Deactivation of ...
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Activation Initiated by LT with Repeater R S/T IOM -2 INFO 0 DI INFO INFO 2 SBCX IEC-Q NT Figure 62 Activation with Repeater Initiated by LT Semiconductor Group R U-Ref. Point IOM -2 ...
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Activation Initiated by TE with Repeater R S/T IOM -2 INFO 0 DC INFO 0 DI TIM INFO INFO 2 SBCX IEC-Q NT Figure 63 Activation with Repeater Initiated by TE Semiconductor Group R ...
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Loss of Synchronization / Signal at Repeater R S/T IOM - INFO 0 INFO SBCX IEC-Q NT Figure 64 Loss of Synchronization at Repeater (LT Side) Semiconductor Group R U-Ref. Point IOM ...
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R S/T IOM - INFO 0 INFO SBCX IEC-Q NT Figure 65 Loss of Signal at Repeater (LT Side) Semiconductor Group R U-Ref. Point IOM -2 IOM -2 SL3T AR SN3T AI dea = ...
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R S/T IOM - INFO 0 INFO SBCX IEC-Q NT Figure 66 Loss of Synchronization at Repeater (NT side) Semiconductor Group R U-Ref. Point IOM -2 IOM -2 SL3T AR SN3T AI Loss of ...
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R S/T IOM - INFO 0 INFO SBCX IEC-Q NT Figure 67 Loss of Signal at Repeater (NT side) Semiconductor Group R U-Ref. Point IOM -2 IOM -2 SL3T AR SN3T AI Loss of ...
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Deactivation with Repeater R S/T IOM - INFO 0 INFO SBCX IEC-Q NT Figure 68 Deactivation with Repeater Semiconductor Group R U-Ref. Point IOM -2 IOM -2 SL3T AR SN3T AI SL3T ...
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Activation Attempt Initiated NT-Auto Activation Mode Note 39: See "Basic Operating Mode", page 50, for setting this mode. If the LT transceiver is available and ready for activation, e.g. if the LT is not in the ...
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To activate the IEC mode from power down without external control of the pin DIN the following procedure has to be used: • Set the SPU bit to "0" in the CIWU-register (see "CIWU-Register", page 217) • Write ...
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Example: Repeater activation initiated by the terminal • NT and LT repeater are in power down. No Monitor Channel command is active or pending. • A wake-up tone is received from downstream. • The LT repeater pulls DOUT low which ...
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State Machines 4.4.1 State Machine Notation Rules The state machine includes all information necessary for the user to understand and predict the activation/deactivation status of the IEC-Q. The information contained in a state bubble is: – State name – ...
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Leave for state "Awake" after NT wake up tone (TN) was detected and the C/I-code DC is present in the downstream direction – Leave for state "Alerting" after C/I-commands "AR", "ARX", "AR0" or "UAR" and not TN were received ...
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LT Modes State Diagram SL0/SP Test Any State HI DEAC Pin-SSP or Pin-RES or Pin PS1=1 Pin (PS1=1) or µP-SSP or µP-RES or SSP or RES or PFOFF or LTD Legend IN Signal State ...
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Transition Criteria in LT Modes The transition criteria used by the IEC-Q are described in the following sections. They are grouped into: – C/I-commands – Pin states – Events related to the U-interface – Timers C/I-Commands AR Activation Request ...
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This can be done in the following manner - Assumption: The IEC-Q on the LT side is in the "S/T Deactivated" state. It receives SAI=0 from the NT side, i.e. the terminal is deactivated. The control ...
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RES Reset Unconditional command which resets the transceiver core (see "Reset Behavior", page 94). For cold start the reset code should be applied for a period of at least 8 IOM needs to be applied during reset. RES1 Reset 1 ...
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Pin-PFOFF Power Feed OFF Corresponds to pin PS1 being activated. This pin indicates that the remote-power-feed circuit for the subscriber line has been turned off. The IEC-Q is requested to forward this indication making use of the C/I-channel code HI. ...
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UAI is issued. Until the status "ready for sending" is reached, binary "0s" have to be passed in the B- and D-channels on DIN. – ACT = 0 indicates the loss of transparency on the NT side (loss of ...
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TN Tone (wake-up signal) received from the NT. When in the "Deactivated" state, the IEC-Q is requested to start an activation procedure and to inform the LT side making use of the C/I-channel code AR. When in the "Wait for ...
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Table 29 Timers for LT State Machine Timer Duration (ms) T1 15000 6000 T5 1000 T6 6000 T10 40 4.4.2.3 Output Signals and Indications in LT Modes Signals and ...
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DI Deactivation Indication Idle code on the IOM "Deactivated" state unless an activation procedure is started by the NT side. EI2 Error Indication 2 EI2 is issued if the received ACT-bit is (0). The NT receiver indicates a loss of ...
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Signals on U-Interface The signals SLx, TL and SP transmitted on the U-interface are defined in Table 28, page 125. The polarity of the overhead bits ACT and DEA is indicated as follows 0/1 corresponds to ACT bit ...
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Deactivated (Full Reset) In the "Deactivated" state the device may enter the low power consumption condition. The power-down mode is entered if no monitor messages are active or pending. In power-down the Receiver and parts of the interface are deactivated ...
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Line Active In the "Line Active" state, the IEC-Q transmits transparently in both directions. The U-Interface is synchronized and the maintenance channel is operational. The IEC-Q stays in the line-active state – during a normal activation procedure while the "ACT" ...
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Reset for Loop "Reset for Loop" resets the Receiver in order to guarantee a correct adaption of the echo- and equalizer coefficients. Receive Reset The "Receive Reset" state assures that for a period signal, especially no wake-up ...
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Test This "Test" mode is entered when the unconditional commands RES, SSP, LTD, Pin-RES, Pin-SSP or PFOFF are used left when the pins RESQ, TSP and PS1 are inactive and the C/I-channel code DR is received. The output ...
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NT Modes State Diagram - SN0 T14S Pending Timing DC T14S Any State Pin-SSP or Pin-RES or DI µP-SSP or µP-RES or - SN0/SP SSP or RES Test DR ARL T12S - SN1 EC-Training AL DC LSEC or T12E ...
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SN0 T14S Pending Timing DC Any State Pin-SSP or Pin-RES or µP-SSP or µP-RES or - SN0/SP SSP or RES Test DR ARL T12S - SN1 EC-Training AL DC LSEC or T12E SN3 act=0 Wait for ...
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Transition Criteria in NT Modes C/I-Commands AI Activation Indication The S-transceiver issues this indication to announce that the S-receiver is synchronized. The IEC-Q informs the LT side by setting the "ACT" bit to "1". AR Activation Request INFO1 has ...
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RES Reset Unconditional command which resets the transceiver core (see "Reset Behavior", page 94). Especially the EC- and EQ-coefficients are set to zero. SSP Send Single Pulses Unconditional command which requests the transmission of single pulses on the U-interface. The ...
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Single Pulses Applies only in microprocessor mode. Corresponds to the setting: STCR:TM1 = ’1’ and STCR:TM2 = ’1’. The function of this setting is the same as of the C/I-code SSP. C/I-message DR will be issued. See "Test ...
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LSU Loss of Signal level on the U-interface This signal indicates that a loss of signal level for a duration has been detected on the U-interface. This short response time is relevant in all cases where the ...
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Timers The start of timers is indicated by TxS, the expiry by TxE. The Table 30 shows which timers are used by the IEC mode: Table 30 Timers for NT State Machine Timer Duration (ms) Function T1 15000 ...
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DC Deactivation Confirmation Idle code on the C/I Channel. The IEC-Q stays in the power-down mode unless an activation procedure has been started from the LT side. The U-interface may be activated but the S/T-interface has to remain deactivated. DR ...
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Alerting 1 "Alerting 1" state is entered when a wake-up tone was received in the "Receive Reset" state and the deactivation procedure on the NT side was not yet finished. The transmission of wake-up tone TN is started. Analog Loop-Back ...
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EQ-Training The Receiver waits for signal SL1 or SL2 to be able to update the AGC, to recover the timing phase, to detect the synch-word (SW), and to update the EQ-coefficients. The "EQ-training" state is left upon detection of binary ...
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Pending Alerting 1 Note 46: This state only exists in NT-Auto Activation mode. The "Pending Alerting" state is entered upon detection of loss of framing on the U-interface or expiry of timer T1. This failure condition is signalled to the ...
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Synchronized 2 In this state the IEC-Q has received UOA = 1. This is a request to activate the S/T-reference point. The loop-back commands detected by the EOC-processor control the output of indications and transmit signals: – Normal activation and ...
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Wait for SF AL This state is entered in the case of an analog loop-back and allows the Receiver to update the AGC, to recover the timing phase, and to update the EQ-coefficients. Signal SN3 is sent instead of signal ...
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SL0/SP Test Any State HI DEAC Pin-SSP or Pin-RES or Pin PS1=1 Pin (PS1=1) or µP-SSP or µP-RES or SSP or RES or PFOFF or LTD Legend IN Signal State Name CI-Code Indication (DU) OUT ...
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SN0 T14S Pending Timing DC T14S Any State Pin-SSP or Pin-RES or DI µP-SSP or µP-RES or - SN0/SP SSP or RES Test DR ARL T12S - SN1 EC-Training AL DC LSEC or T12E - SN3 Wait for SF ...
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Monitoring Transmission Quality The basic tool for monitoring transmission quality is the cyclic redundancy check procedure (see "Cyclic Redundancy Check (CRC)", page 64). Calculation verification and insertion of the CRC bits are performed automatically by the IEC-Q and there ...
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LT --> NT Superframe Frame Number Current CRC Bits Related to Frame Number Current FEBE Bit Related to Frame Number NT --> LT Superframe Frame Number Current CRC Bits Related to Frame Number Current FEBE Bit Related to Frame Number ...
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Note 50 and COT modes a FEBE will not be actively indicated by the IEC-Q. To monitor NEBE violations the NEBE counter should be read out, see "Block Error Counters", page 178. Note also that although the FEBE ...
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LT modes Line Active Pend. Transparent Transparent S/T Deactivated 4.5.1.2 FEBE Counter Each detected FEBE will cause the FEBE counter to be incremented. The maximum count further incrementation will be done after maximum count is reached. ...
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Testing Block Error Counters The block error counter is tested by simulating transmission errors on the line. To simulate transmission errors artificially corrupted CRC bits (as a matter of fact, inverted CRC bits) are send from the LT to ...
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Initialization (LT side) MON Acknowledgment (NT and LT side) MON Notify of Corrupt CRC (NCC) If the EOC Auto mode is used on the NT side (see "EOC Auto/Transparent Mode", ...
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Initialization (LT side) MON Acknowledgment (NT and LT side) MON Corrupt CRCs (CCRC) If the EOC Transparent mode is used on the NT side one of the LT ...
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R IOM -2 NT Transparent (MON-0) NCC (MON -0) ACK (MON -1) NEBE ERROR COUNT NEBE (MON -0) RTN (MON-0) ACK (MON-0) RCC (MON -0) ACK (MON -8) CCRC ERROR (MON-1) FEBE COUNT FEBE (MON-0) RTN (MON -0) ACK Figure ...
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R IOM - D G(u) CRC 1...CRC12 No =? (MON-1) NEBE NEBE (MON-8) Error Counter DU G(u) CRC 1 ... CRC FEBE (MON-8) Error Counter (MON-1) FEBE Figure 79 CRC Violation Indications Semiconductor Group ...
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Chip Internal Test Options The IEC-Q permits limited access to internal test procedures and internal data. This chapter explains how these tests can be performed. 4.6.1 Self-Test Note 52: This section applies only in the NT, NT-PBX and TE ...
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Initialization Read request MON-8 (1. Byte) (2. Byte) For each requested coefficient 16 bit are returned in the following manner MON-8 (1. Byte) (2. Byte) (3. Byte) (4. Byte) Table 31 Internal Coefficient Addresses Register Echo Canceller Equalizer For more ...
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IOM S-Bus Loop 2 SBCX NT IOM ICC ICC PBX or TE Figure 80 Test Loop-Backs Supported by the IEC-Q Loop-backs #1, #1A and #2 are controlled by the exchange. Loop-back #3 is controlled by the terminal. All four loop-back ...
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Analog Loop-Back Control Before an analog loop-back is closed with the C/I-command ARL (activation request loop-back, see "C/I Channel Codes", page 224), the device should have been reset. In order to open an analog loop-back correctly, reset the device into ...
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Complete Loop-Back When receiving the EOC-command LBBD in Auto mode, the NT IEC-Q does not close the loop-back immediately. Because the intention of this loop-back is to test the complete NT, the IEC-Q passes the complete loop-back request on ...
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Single-Channel Loop-Backs Single-channel loop-backs are always performed directly in the IEC-Q. No difference between the B1-channel and the B2-channel loop-back control procedure exists. They are therefore discussed together. In EOC Auto mode the B1-channel is closed with the EOC-command ...
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Repeater Adr = C/I = AIL Figure 82 Closing Loop-Back # Multi-Repeater System 4.7.2.4 Codes This section gives the Monitor Channel messages used to control test loop-back #2. For ...
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Codes Used in EOC Auto Modes for Complete Loop-Backs If the complete loop should be closed outside the IEC-Q, the following code is applied. Initialization (LT side) MON Acknowledgment (issued on LT and NT side) ...
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Initialization (NT side) MON acknowledgment issued. Initialization (NT side) MON acknowledgment issued. Initialization (NT side) MON acknowledgment issued. 4.8 Chip Identification The ...
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Access to Power Status Pins This chapter deals with the operational aspects of accessing the power controller maintenance features provided by the IEC-Q. Pins PS1 and PS2 are available to support these features. Furthermore, in stand-alone mode pin DISS ...
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B 1 Channel 0 PFC Figure 83 Serial Data Port of Pin PS2 in LT Modes This value can be read out through MON8-Channel. The MON-8 command RPFC (Read Power Feed Current) requests the IEC-Q to return the current feed ...
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LT Modes The pin DISS is used for switching off the remote power supply of the subscriber line set to ’1’ by the C/I-command "LTD" (0011 not affect the DISS-pin. While the DISS-pin is set to (1), the ...
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MON MON MON After the receipt of a MON-8-command the IEC-Q will set the address/data bits and generate a read or write pulse. The ...
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Figure 84 Sampling of Interrupts 4.11 S/G Bit and BAC Bit Operations Note 61: This chapter applies only in the µP-TE mode (see "Setting Operating Modes", page 50). If DCL = 1.536 MHz the IOM "Terminal Timing Mode", ...
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Table 33 S/G Bit Control Overview SWST: SWST: ADF: BS SGL CBAC ’x’ is don’t care Semiconductor ...
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State Machine The exact S/G Bit Control function is given in the following state diagrams. The values in the state diagrams are to be interpreted as follows : Figure 85 State Machine Notation for S/G Bit Control Semiconductor Group ...