AD8138ARZ Analog Devices Inc, AD8138ARZ Datasheet - Page 7

IC AMP DIFF LDIST LP 95MA 8SOIC

AD8138ARZ

Manufacturer Part Number
AD8138ARZ
Description
IC AMP DIFF LDIST LP 95MA 8SOIC
Manufacturer
Analog Devices Inc
Type
ADC Driverr
Datasheet

Specifications of AD8138ARZ

Design Resources
DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7352 (CN0040) DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7356 (CN0041) DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7357 (CN0061)
Applications
Data Acquisition
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Number Of Channels
1
Number Of Elements
1
Power Supply Requirement
Single/Dual
Common Mode Rejection Ratio
70dB
Voltage Gain Db
0.028dB
Input Resistance
6@5VMohm
Input Offset Voltage
2.5@5VmV
Input Bias Current
7@5VnA
Single Supply Voltage (typ)
3/5/9V
Dual Supply Voltage (typ)
±3/±5V
Power Supply Rejection Ratio
70dB
Power Dissipation
550mW
Rail/rail I/o Type
No
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
11V
Dual Supply Voltage (min)
±1.4V
Dual Supply Voltage (max)
±5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC N
No. Of Amplifiers
1
Gain Db Max
1.0045dB
Bandwidth
320MHz
Slew Rate
1150V/µs
Supply Voltage Range
2.7V To 11V, ± 1.4V To ± 5.5V
Supply Current
20mA
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Supply Voltage
V
Internal Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
specified for the device soldered in a circuit board in still air.
Table 6.
Package Type
8-Lead SOIC/4-Layer
8-Lead MSOP/4-Layer
Maximum Power Dissipation
The maximum safe power dissipation in the AD8138 packages
is limited by the associated rise in junction temperature (T
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8138. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
JA
OCM
is specified for the worst-case conditions, that is, θ
θ
121
145
JA
Ratings
±5.5 V
±V
550 mW
−40°C to +85°C
−65°C to +150°C
300°C
150°C
S
JA
Unit
°C/W
°C/W
is
J
) on
Rev. F | Page 7 of 24
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
internal common-mode feedback loop. The internal resistor tap
used in the common-mode feedback loop places a negligible
differential load on the output. RMS voltages and currents
should be considered when dealing with ac signals.
Airflow reduces θ
with the package leads from metal traces through holes, ground,
and power planes reduces the θ
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(121°C/W) and 8-lead MSOP (θ
JEDEC standard 4-layer board. θ
1.75
1.50
1.25
1.00
0.75
0.50
0.25
Figure 3. Maximum Power Dissipation vs. Temperature
0
–40 –30 –20 –10
JA
S
. In addition, more metal directly in contact
). The load current consists of the differential
0
AMBIENT TEMPERATURE (°C)
10
20
30
MSOP
JA
JA
.
JA
40
= 145°C/W) packages on a
values are approximations.
50
SOIC
D
60
) is the sum of the
70
80
S
90 100 110 120
) times the
AD8138

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