X1243S8 Xicor, X1243S8 Datasheet
X1243S8
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X1243S8 Summary of contents
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... Logic Interface SCL Decoder SDA 8 IRQ Xicor, Inc. 1994, 1995, 1996 Patents Pending 9900-3003.1 4/1/99 X1243 DESCRIPTION The X1243 is a Real Time Clock with clock/calendar circuits and two alarms. The dual port clock and alarm registers allow the clock to operate, without loss of accuracy, even during read and write operations ...
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X1243 X1243 8 pin SOIC IRQ X1243 8 pin TSSOP V Back PIN DESCRIPTIONS Serial Clock ...
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X1243 the clock on the ACK bit prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continues to run. Alarms occuring during a read are unaffected by the read operation. ...
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X1243 disables the output IRQ for that alarm condition, but the alarm condition can still be checked by polling the alarm flag. Table 1. Clock/Control Memory Map Reg Addr. Type Name 7 003F Status SR BAT 0037 Y2K 0 0036 ...
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X1243 value to a specific day of the week is arbitrary and may be decided by the system software designer. The Clock Default values define 0=Sunday. Clock/Calendar Registers (YR, MO, DT, HR, MN, SC) These registers depict BCD representations of ...
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X1243 CONTROL REGISTERS Block Protect Bits - BP2, BP1, BP0 - (Nonvolatile) The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The ...
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X1243 initiate another change to the CCR contents. If the sequence is not completed for any reason (by send- ing an incorrect number of bits or sending a start instead of a stop, for example) the RWEL bit is not ...
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X1243 SCL from Master Data Output from Transmitter Data Output from Receiver Start Figure 5. Acknowledge Response From Receiver Acknowledge Acknowledge is a software convention used to indi- cate successful data transfer. The transmitting device, either master or slave, will ...
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X1243 Signals from the Master SDA Bus Signals from the Slave 7 bytes address = 6 Figure 7. Writing 30 bytes -byte page starting at adress Signals from a the Master Slave r ...
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X1243 the address counter would point to location 7 on the page that was just written. If the master supplies more than the maximum bytes in a page, then the previously loaded data is over written by the new data, ...
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X1243 Signals from the Master SDA Bus Signals from the Slave Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to ...
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X1243 DEVICE ADDRESSING Following a start condition, the master must output a Slave Address Byte. The first four bits of the Slave Address Byte specify access to the EEPROM array or to the CCR. Slave bits ‘1010’ access the EEPROM ...
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X1243 Device Identifier Array 1 0 CCR Figure 13. Slave Address, Word Address, and Data Bytes (64 Byte pages A10 A9 A5 ...
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X1243 ABSOLUTE MAXIMUM RATINGS Temperature Under Bias.................. -65˚C to +135˚C Storage Temperature....................... -65˚C to +150˚C Voltage on any pin with respect to ground-1.0V to 7.0V DC Output Current .............................................5 mA Lead Temperature (Soldering, 10 Seconds) .... 300˚C DC OPERATING CHARACTERISTICS ...
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X1243 0V. BACK Others=GND or V SDA SCL BACK 7: V ...
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X1243 AC Specifications - T = -40˚C to +85˚ Symbol f SCL Clock Frequency SCL (1) t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t Time the bus must ...
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X1243 Write Cycle Timing SCL 8th bit of last byte SDA Power Up Timing Symbol (1) t Time from Power Up to Read PUR (1) t Time from Power Up to Write PUW 1. Delays are measured from the time ...
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... Operating Temperature Range - 8-Lead SOIC X1243 X XX Blank = 2.7 to 5.5V +70° 2.7 to 5.5V, -40 to +85°C 18 PART NUMBER 16Kb EEPROM RESET (LOW) X1243S8 X1243S8I X1243V8 Blank = 8-Lead SOIC ...