PALCE16V8Q-15JC/4 Lattice Semiconductor Corp., PALCE16V8Q-15JC/4 Datasheet

no-image

PALCE16V8Q-15JC/4

Manufacturer Part Number
PALCE16V8Q-15JC/4
Description
Manufacturer
Lattice Semiconductor Corp.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PALCE16V8Q-15JC/4
Manufacturer:
AMD
Quantity:
7 596
Part Number:
PALCE16V8Q-15JC/4
Manufacturer:
AMD
Quantity:
7 596
Part Number:
PALCE16V8Q-15JC/4
Manufacturer:
AMD
Quantity:
1 348
Part Number:
PALCE16V8Q-15JC/4
Manufacturer:
AMD
Quantity:
1 000
Part Number:
PALCE16V8Q-15JC/4
Manufacturer:
LATTICE
Quantity:
1 000
Part Number:
PALCE16V8Q-15JC/4
Manufacturer:
AMD
Quantity:
20 000
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-
erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The
macrocells provide a universal device architecture. The PALCE16V8 will directly replace the
PAL16R8, with the exception of the PAL16C1.
The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALCE16V8Z allows battery-powered operation for an extended period.
The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
Publication# 16493
Amendment/0
Pin and function compatible with all 20-pin PAL
Electrically erasable CMOS technology provides reconfigurable logic and full testability
High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
Direct plug-in replacement for the PAL16R8 series
Outputs programmable as registered or combinatorial in any combination
Peripheral Component Interconnect (PCI) compliant
Programmable output polarity
Programmable enable/disable control
Preloadable output registers for testability
Automatic register reset on power up
Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
Extensive third-party software and programmer support
Fully tested for 100% programming and functional yields and high reliability
5-ns version utilizes a split leadframe for improved performance
Rev: F
Issue Date: September 2000
PALCE16V8
PALCE16V8Z
PALCE16V8 and PALCE16V8Z Families
EE CMOS (Zero-Power) 20-Pin Universal
Programmable Array Logic
COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25
COM’L:-25
®
devices
IND:-12/15/25

Related parts for PALCE16V8Q-15JC/4

PALCE16V8Q-15JC/4 Summary of contents

Page 1

DISTINCTIVE CHARACTERISTICS Pin and function compatible with all 20-pin PAL Electrically erasable CMOS technology provides reconfigurable logic and full testability High-speed CMOS technology — 5-ns propagation delay for “-5” version — 7.5-ns propagation delay for “-7” version Direct plug-in replacement ...

Page 2

BLOCK DIAGRAM MACRO MACRO MACRO I/O I FUNCTIONAL DESCRIPTION The PALCE16V8 is a universal PAL device. The PALCE16V8Z is the zero-power version of the PALCE16V8. It has all the architectural ...

Page 3

Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the PALCE16V8 device code. This option allows full utilization of the macrocell SG1 *In macrocells MC and MC , SG1 ...

Page 4

Registered Output Configuration The control bit settings are SG0 = 0, SG1 = 1 and SL0 configuration. All eight product terms are available as inputs to the OR gate. Data polarity is determined by SL1 The flip-flop is loaded on ...

Page 5

Programmable Output Polarity The polarity of each macrocell can be active-high or active-low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), ...

Page 6

CLK a. Registered active low c. Combinatorial I/O active low Combinatorial output active low Notes: 1. Feedback is not available on pins 15 and 16 in the combinatorial output mode. 2. This configuration ...

Page 7

Power-Up Reset All flip-flops power logic LOW for predictable system initialization. Outputs of the PALCE16V8 will depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial ...

Page 8

The current will go to almost zero (I maintain the states held before the device went into the standby mode. There is no speed penalty associated with coming out of standby mode. When any input ...

Page 9

LOGIC DIAGRAM CLK ...

Page 10

LOGIC DIAGRAM (CONTINUED ...

Page 11

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...

Page 12

CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 13

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...

Page 14

CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 15

... Max OUT (Note 0 Max (Note 3) OUT CC Outputs Open ( mA), OUT V = Max MHz CC and I (or I and I ). OZL IH OZH PALCE16V8Q-10 (Com’ Min Max , V = Min 2 Min 0.5 CC 2.0 0.8 10 –100 10 –100 –30 –150 55 Unit µ ...

Page 16

... CNT S CF 1/( and t are defined under best case conditions. Future process improvements PZX PXZ EA ER can be found using the following equation: CF PALCE16V8Q-10 (Com’l) Typ Unit 5 ° MHz -10 2 Min Max Unit ...

Page 17

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...

Page 18

CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 19

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...

Page 20

CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 21

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...

Page 22

CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 23

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...

Page 24

CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 25

SWITCHING WAVEFORMS Input or V Feedback Combinatorial Output a. Combinatorial output t WH Clock c. Clock width Output Notes 1 Input pulse amplitude 3 Input rise ...

Page 26

KEY TO SWITCHING WAVEFORMS WAVEFORM SWITCHING TEST CIRCUIT Specification Closed Open Closed H Z: Open Closed 26 INPUTS OUTPUTS Must be Will be ...

Page 27

TYPICAL I CHARACTERISTICS 25° 150 125 100 The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, ...

Page 28

ENDURANCE CHARACTERISTICS The PALCE16V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link used in bipolar parts result, the device can be erased and reprogrammed—a feature which ...

Page 29

INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE16V8Z ESD Input Protection Transition and Detection Clamping POWER-UP RESET The PALCE16V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will ...

Page 30

V Power Registered Output Clock TYPICAL THERMAL CHARACTERISTICS Measured ambient. These parameters are not tested. Parameter Symbol Parameter Description Thermal impedance, junction to case jc Thermal impedance, junction to ambient ja Thermal impedance, junction to ambient ...

Page 31

CONNECTION DIAGRAMS Top View DIP/SOIC CLK ...

Page 32

... PALCE16V8H-10 PC, JC, SC, PI, JI PALCE16V8Q-10 JC PALCE16V8H-15 PC, JC, SC PALCE16V8Q-15 PC, JC PALCE16V8Q-20 PI, JI PALCE16V8H-25 PC, JC, SC, PI, JI PALCE16V8Q-25 PC, JC, PI, JI PALCE16V8Z-12 PI, JI PALCE16V8Z-15 PALCE16V8Z-25 PC, JC, SC, PI, JI Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local Lattice/ /5 Vantis sales offi ...

Related keywords