UPD750064CU NEC, UPD750064CU Datasheet
UPD750064CU
Related parts for UPD750064CU
UPD750064CU Summary of contents
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... PD750064(A), PD750066 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U10165EJ2V0DS00 (2nd edition) ...
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... " " NEC Corporation to know the specification of quality grade on the devices and its recommended applications. ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Functional Outline Item Instruction execution time • 0.95 s, 1.91 s, 3. 4.19-MHz operation with main system clock) • 0.67 s, 1.33 s, 2. 6.0-MHz operation ...
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... BLOCK DIAGRAM ................................................................................................................................ 7 3. PIN FUNCTION ..................................................................................................................................... 8 3.1 Port Pins ...................................................................................................................................... 8 3.2 Non-port Pins ............................................................................................................................ 10 3.3 Pin Input/Output Circuits ......................................................................................................... 12 3.4 Recommended Connection of Unused Pins .......................................................................... 15 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................ 16 4.1 Differences between Mk I Mode and Mk II Mode .................................................................... 16 4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 17 5. MEMORY CONFIGURATION ............................................................................................................. 18 6 ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) APPENDIX A. PD75068, 750068 AND 75P0076 FUNCTIONAL LIST .................................................. 73 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................. 75 APPENDIX C. RELATED DOCUMENTS ................................................................................................. 79 Data Sheet U10165EJ2V0DS00 5 ...
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... SS P63/KR3/AN7 P62/KR2/AN6 P61/KR1/AN5 P60/KR0/AN4 P113/AN3 P112/AN2 P111/AN1 P110/AN0 AV REF IC: Internally Connected (Connect pin directly to V Pin Identification AN0 to AN7 : Analog Input Analog Reference REF AV : Analog Ground SS BUZ : Buzzer Clock IC : Internally Connected INT0, INT1, INT4 : External Vectored Interrupt ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 2. BLOCK DIAGRAM Basic interval timer/watchdog timer INTBT BUZ/P23 Watch timer INTW INTW INTT0 8-bit TI0/P13 timer/ event Cascaded PTO0/P20 counter#0 16-bit timer/ event 8-bit TI1/P12/INT2 counter timer/ event PTO1/P21 counter#1 INTT1 SI/SB1/P03 Clocked ...
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... If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low-level input leakage current increases when input or bit manipulation instruction is executed. 8 Function 4-bit input port (PORT0). For P01 to P03, connection of on-chip pull- up resistors can be specified by software in 3-bit units. 4-bit input port (PORT1). Connection of on-chip pull-up resistors can be specified by software in 4-bit units ...
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... Note Circuit types enclosed in brackets indicate the Schmitt trigger input. Function Programmable 4-bit input/output port (PORT6). This port can be specified for input/output in 1-bit units. Connection of on-chip pull-up resistors can be specified by software in 4-bit units. 4-bit input port (PORT11). Data Sheet U10165EJ2V0DS00 8-bit ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 3.2 Non-port Pins (1/2) Alternate Pin Name Input/Output Function TI0 Input P13 TI1 P12/INT2 PTO0 Output P20 PTO1 P21 PCL P22 BUZ P23 SCK Input/Output P01 SO Output P02 SB0 Input/Output SI Input P03 ...
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... SS Note Circuit types enclosed in brackets indicate the Schmitt trigger input. Function Crystal/ceramic connection pin for the main system clock oscillation. When inputting the external clock, input the external clock to pin X1, and the inverted phase of the external clock to pin X2. ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 3.3 Pin Input/Output Circuits The PD750068 pin input/output circuits are shown schematically. TYPE P-ch IN N-ch CMOS standard input buffer TYPE B IN Schmitt-triggered input with hysteresis characteristics TYPE B-C V ...
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... Note P.U.R. Voltage limitation (+13 V circuit withstand voltage) Note This pull-up resistor operates only when an input instruction is executed without a pull-up resistor connected using the mask option (current flows from V to the pin when the pin is low). DD Data Sheet U10165EJ2V0DS00 TYPE P.U.R. IN ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) TYPE Y-D P.U.R. enable data Type D output disable Type B Type Y P.U.R.: Pull-Up Resistor 14 TYPE Z REF P.U.R. P-ch IN/OUT ADEN Data Sheet U10165EJ2V0DS00 (3/3) Reference voltage N-ch ...
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... PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 3.4 Recommended Connection of Unused Pins Table 3-1. List of Recommended Connection of Unused Pins Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0, P11/INT1 P12/TI1/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ P30 to P33 P40 to P43 P50 to P53 P60/KR0/AN4 to P63/KR3/AN7 P110/AN0 to P113/AN3 ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Differences between Mk I Mode and Mk II Mode The CPU of the PD750068 has the following two modes and ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the stack bank select register (SBS). Figure 4-1 shows the format. ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 5. MEMORY CONFIGURATION Program memory (ROM) .... 4096 .... 6144 .... 8192 • Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 5-1. Program Memory Map ( PD750064) Address MBE RBE 0 0 Internal reset start address Internal reset start address MBE RBE ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 5-2. Program Memory Map ( PD750066) Address MBE RBE 0 Internal reset start address Internal reset start address MBE RBE ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 5-3. Program Memory Map ( PD750068) Address MBE RBE 0 Internal reset start address Internal reset start address MBE RBE ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) General-purpose register area Note Stack area Data area static RAM (512 4) Peripheral hardware area Note Memory bank can be selected as the stack area. 22 Figure 5-4. Data Memory Map ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6. PERIPHERAL HARDWARE FUNCTION 6.1 Port The following three types of I/O ports are available. • CMOS input (PORT0, 1, 11) • CMOS input/output (PORT2 • N-ch open-drain input/output (PORT4, 5) Total ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 6-1. Clock Generator Block Diagram XT1 Subsystem f XT clock oscillator XT2 X1 f Main system X clock oscillator X2 WM.3 Oscillation SCC stop SCC3 SCC0 PCC PCC0 PCC1 4 PCC2 Note HALT ...
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... Note When the subsystem clock is not used, set SOS (so as not to use the internal feedback resistor) by software, connect XT1 to V consumption in the subsystem clock oscillator. The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (Refer to Figure 6-2 ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.4 Clock Output Circuit The clock output circuit is provided to output the clock pulses from the P22/PCL pin to the remote control wave output applications and peripheral LSIs. • Clock output (PCL) : ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.5 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. (a) Interval timer operation to generate a reference time interrupt (b) Watchdog timer operation to detect a runaway of program ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.6 Watch Timer The PD750068 has one channel of watch timer. The watch timer has the following functions. (a) Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.7 Timer/Event Counter The PD750068 has two channels of timer/event counters. Its configuration is shown in Figures 6-6 and 6-7. The timer/event counter has the following functions. (a) Programmable interval timer operation (b) Square ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 6-6. Timer/Event Counter Block Diagram (Channel 0) 8 – TM06 TM05 TM04 TM03 TM02 TM01 TM00 Decoder PORT1. 3 Input buffer TI0/P13 Watch timer (INTW) output 2 MPX ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 6-7. Timer/Event Counter Block Diagram (Channel 1) 8 – TM16 TM15 TM14 TM13 TM12 TM11 TM10 PORT1.2 Input buffer TI1/P12/INT2 Timer/event counter output (channel 0) MPX ...
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... I/O mode • 2-wire serial I/O mode The 3-wire serial I/O mode enables connections to be made with the 75X Series, 78K Series, and many other types of I/O devices. The 2-wire serial I/O mode enables communication with two or more devices. Figure 6-8. Serial Interface Block Diagram ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.9 A/D Converter The PD750068 incorporates the 8-bit resolution A/D converter which has eight channels analog input pins (AN0 to AN7). This A/D converter is a successive approximation type. Figure 6-9. A/D Converter Block ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 6.10 Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 7. INTERRUPT FUNCTION AND TEST FUNCTION The PD750068 has seven interrupt sources and two test sources. One test source, INT2, has two types of edge detection testable inputs. The interrupt control circuit of the ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Figure 7-1. Interrupt Control Circuit Block Diagram IM2 IM1 IM0 INTBT Both edge INT4/P00 detector Edge INT0/P10 Note detector Edge INT1/P11 detector INTCSI INTT0 INTT1 INTW Rising edge INT2/P12 detector Selector ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 8. STANDBY FUNCTION In order to save power dissipation while a program standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the PD750068. Table 8-1. ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 9. RESET FUNCTION There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/ watchdog timer. When either one of the reset signals are input, an internal ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Table 9-1. Status of Each Hardware After Reset (1/2) Hardware Program counter (PC) PD750064 PD750066, Sets the low-order 5 bits of 750068 PSW Carry flag (CY) Skip flag (SK0 to SK2) Interrupt status flag ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Table 9-1. Status of Each Hardware After Reset (2/2) Hardware Serial interface Shift register (SIO) Operation mode register (CSIM) SBI control register (SBIC) Clock generator, Processor clock control register (PCC) clock output System clock ...
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... MHz, 7. • Mask option of subsystem clock Can select whether to enable the internal feedback resistor. (1) The internal feedback resistor is enabled (switch internal feedback resistor ON/OFF by software). (2) The internal feedback resistor is disabled (disconnect internal feedback resistor by hardware). = 4.19 MHz 4.19 MHz) X Data Sheet U10165EJ2V0DS00 ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 11. INSTRUCTION SET (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) (2) Legend in explanation of operation register; 4-bit accumulator register register register register register L : ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) (3) Explanation of symbols under addressing area column * MBE•MBS (MBS = MBE = (000H to 07FH ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Number Mnemonic Operand Group of Bytes Transfer MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL– A, @rpa1 XA, @HL @HL, A @HL ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Mnemonic Operand Group Table MOVT XA, @PCDE reference XA, @PCXA XA, @BCDE XA, @BCXA Bit transfer MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Operation ADDS A, #n4 ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Number Mnemonic Operand Group of Bytes Operation AND A, #n4 A, @HL XA, rp' rp' #n4 A, @HL XA, rp' rp'1, XA XOR A, #n4 A, @HL XA, rp' rp'1, ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Mnemonic Operand Group Memory bit SET1 mem.bit manipulation fmem.bit pmem.@L @H+mem.bit CLR1 mem.bit fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY, fmem.bit ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Mnemonic Operand Group Note Branch BR addr addr1 ! addr $addr $addr1 Note The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Mnemonic Operand Group Branch BR PCDE PCXA BCDE BCXA Note 3 BRA BRCB !caddr Note 3 Subroutine CALLA !addr1 stack control Notes 1. “0” must be set to B register. 2. Only low-order ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Mnemonic Operand Group Note Subroutine CALL !addr stack control Note CALLF !faddr Note The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Mnemonic Operand Group Note Subroutine RET stack control RETS Note Note The operations indicated with thick lines can be performed only in the Mk II mode. The other operations can be performed only ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Mnemonic Operand Group Note 1 Subroutine RETI stack control PUSH rp BS POP rp BS Interrupt EI control Note 2 Input/output IN A, PORTn XA, PORTn Note 2 OUT PORTn, ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Instruction Mnemonic Operand Group Notes 1, 2 Special GETI taddr Notes 1. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. 2. The operations indicated with thick ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25˚C) A Parameter Symbol Supply voltage V DD Input voltage V Other than ports Ports Output voltage V O ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Main System Clock Oscillator Characteristics (T Recommended Resonator Constants Ceramic resonator Crystal resonator External clock X1 X2 Notes 1. The oscillation frequency and X1 input frequency ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Subsystem Clock Oscillator Characteristics (T Recommended Resonator Constants Crystal resonator XT1 XT2 External clock XT1 XT2 Notes 1. The oscillation frequency and XT1 input frequency shown above indicate only oscillator characteristics. ...
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... FCR6.0MC5 Note When using the CSB1000J (1.0 MHz) by Murata Mfg. Co., Ltd ceramic resonator, a limiting resistor ( necessary (refer to the figure below). The limiting resistor is not necessary when using the other recommended resonators. Caution The oscillator constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee precision of the oscillation frequency ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) DC Characteristics (T = –40 to +85˚ Parameter Symbol Output current, low I Per pin OL Total of all pins Input voltage, high V Ports IH1 V Ports 0, ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) DC Characteristics (T = –40 to +85˚ Parameter Symbol Note 1 Note 2 Supply current I 6.0-MHz DD1 crystal oscillation DD2 = 22 pF Note 2 I 4.19-MHz ...
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... RSL Notes 1. The cycle time (minimum instruction execution time) of the CPU clock ( ) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC), and processor clock control register (PCC). The figure on the right shows the supply voltage V vs ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (T Parameter Symbol SCK cycle time t KCY1 SCK high-/low-level width t , KL1 t KH1 Note 1 SI setup ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) A/D Converter Characteristics (T = –40 to +85˚ Parameter Symbol Resolution Absolute accuracy Note 1 Conversion time t CONV Sampling time t SAMP Analog input voltage V IAN Analog input impedance R ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) AC timing test points (excluding X1 and XT1 inputs) V (MIN (MAX (MIN (MAX.) OL Clock timing X1 input XT1 input TI0, TI1 timing TI0, TI1 64 V ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Serial transfer timing 3-wire serial I/O mode SCK SI t KSO1 2-wire serial I/O mode t KL1, 2 SCK SB0 KSO1 KCY1 KL1, 2 KH1, ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Interrupt input timing INT0 KR0 to 3 RESET input timing RESET INTL INTH t RSL Data Sheet U10165EJ2V0DS00 ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T Parameter Symbol Release signal set time t SREL Oscillation stabilization t WAIT Note 1 wait time Notes 1. The oscillation stabilization wait time ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 13. CHARACTERISTICS CURVES (REFERENCE VALUES (main system clock: 6.0-MHz crystal resonator 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 PCC = 0011 PCC = ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068( (main system clock: 4.19-MHz crystal resonator 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 Data Sheet U10165EJ2V0DS00 PCC = 0011 PCC = 0010 PCC ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 14. PACKAGE DRAWINGS 42 PIN PLASTIC SHRINK DIP (600 mil NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 42 PIN PLASTIC SHRINK SOP (375 mil NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ...
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... The PD750068 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 15-1. Surface Mounting Type Soldering Conditions PD750064GT- : 42-pin plastic shrink SOP (375 mil, 0 ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) APPENDIX A. PD75068, 750068 AND 75P0076 FUNCTIONAL LIST Item Program memory Data memory 000H to 1FFH (512 CPU 75X Standard CPU General-purpose register 4 bits Instruction When main system 0.95, 1.91, 15.3 s execution ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Item Clock output (PCL) , 524, 262, 65.5 kHz (@4.19-MHz operation with main system clock) Buzzer output (BUZ kHz (@4.19-MHz operation with main system clock or @32.768-kHz operation with subsystem clock) ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for system development using the PD750068. In the 75XL Series, the relocatable assembler which is common to the series is used in combination with ...
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... PA-75P0076CU PROM programmer adapter for the programmer adapter to PG-1500 for use. Software PG-1500 controller PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is controlled on the host machine. Host Machine PC-9800 Series IBM PC/AT compatible machines Note Ver ...
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... Subseries, the emulation board IE-75300-R-EM and emulation probe that are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine and PROM programmer. IE-75300-R-EM Emulation board for evaluating the application systems that use a PD750068 Subseries. ...
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PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) OS for IBM PC The following IBM PC OS’s are supported. OS Version PC DOS TM Ver. 5.02 to Ver. 6.3 Note Note J6.1/V to J6.3/V MS-DOS Ver. 5.0 to Ver. 6.22 Note Note ...
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... Document Name SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J Guide to Microcomputer-Related Products by Third Party Caution The related documents listed above are subject to change without notice ...
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... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices ...
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... PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability • ...
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... The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...