PALCE22V10Q-25PC/4 Lattice Semiconductor Corp., PALCE22V10Q-25PC/4 Datasheet

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PALCE22V10Q-25PC/4

Manufacturer Part Number
PALCE22V10Q-25PC/4
Description
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and
flip-flops at a reduced chip count.
The PALCE22V10Z is an advanced PAL
erasable CMOS technology. It provides user-programmable logic for replacing conventional zero-
power CMOS SSI/MSI gates and flip-flops at a reduced chip count.
The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby
current, the PALCE22V10Z allows battery-powered operation for an extended period.
The PAL device implements the familiar Boolean logic transfer function, the sum of products. The
PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed
to create custom product terms, while the OR array sums selected terms at the outputs.
The product terms are connected to the fixed OR array with a varied distribution from 8 to16 across
the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each
macrocell can be programmed as registered or combinatorial, and active-high or active low. The
output configuration is determined by two bits controlling two multiplexers in each macrocell.
Publication# 16564
Amendment/0
As fast as 5-ns propagation delay and 142.8 MHz f
Low-power EE CMOS
10 macrocells programmable as registered or combinatorial, and active high or active low to
match application needs
Varied product term distribution allows up to 16 product terms per output for complex
functions
Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)
Global asynchronous reset and synchronous preset for initialization
Power-up reset for initialization and register preload for testability
Extensive third-party software and programmer support
24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC
5-ns and 7.5-ns versions utilize split leadframes for improved performance
Rev: E
Issue Date: November 1998
PALCE22V10 and PALCE22V10Z
Families
24-Pin EE CMOS (Zero Power) Versatile PAL Device
PALCE22V10
PALCE22V10Z
®
device built with zero-power, high-speed, electrically-
COM'L: H-5/7/10/15/25,Q-10/15/25 IND: H-10/15/20/25
COM'L: -25
MAX
(external)
IND: -15/25

Related parts for PALCE22V10Q-25PC/4

PALCE22V10Q-25PC/4 Summary of contents

Page 1

DISTINCTIVE CHARACTERISTICS As fast as 5-ns propagation delay and 142.8 MHz f Low-power EE CMOS 10 macrocells programmable as registered or combinatorial, and active high or active low to match application needs Varied product term distribution allows ...

Page 2

BLOCK DIAGRAM CLK OUTPUT OUTPUT OUTPUT RESET LOGIC LOGIC LOGIC MACRO MACRO MACRO CELL CELL CELL I/O I/O I FUNCTIONAL DESCRIPTION The PALCE22V10 allows the systems engineer to implement the design on-chip, ...

Page 3

Variable Input/Output Pin Ratio The PALCE22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to ...

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CLK SP a. Registered/active low CLK SP c. Registered/active high Figure 2. Macrocell Configuration Options Programmable ...

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Note that preset and reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected. Power-Up Reset All flip-flops power logic LOW for predictable system initialization. Outputs of the PALCE22V10 ...

Page 6

The current will go to almost zero (I maintain the states held before the device went into the standby mode. When any input switches, the internal circuitry is fully enabled, and power consumption returns to ...

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LOGIC DIAGRAM CLK ( ( ( ( (6) ...

Page 8

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65 ° +150 ° C Ambient Temperature with Power Applied . . . . . . . . . . ...

Page 9

CAPACITANCE Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . ...

Page 11

CAPACITANCE Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 12

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . ...

Page 13

CAPACITANCE Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

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... (Note 2) V OUT = Max (Note 2) V OUT = 0 25°C (Note Outputs Open (I OUT V = Max (Note 4) CC and I (or I and I ). OZL IH OZH CC PALCE22V10Q-10 (Com’ with CC Min Max 2.4 0.4 2.0 0.8 10 -100 10 -100 -30 -130 = 0mA ...

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... Test Conditions 2 OUT = 2.0 V Parameter Description LOW HIGH External Feedback 1/( Internal Feedback (f CNT ) 1/( (Note 3) No Feedback 1/( can be found using the following equation: CF PALCE22V10Q-10 (Com’l) Typ Unit 5 25° MHz -10 Min Max Unit ...

Page 16

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . ...

Page 17

CAPACITANCE Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 18

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . ...

Page 19

CAPACITANCE Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 20

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . ...

Page 21

CAPACITANCE Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 22

ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . . ...

Page 23

CAPACITANCE Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

Page 24

SWITCHING WAVEFORMS Input, I/ Feedback Combinatorial Output a. Combinatorial output t WH Clock c. Clock width Input t ARW Asserting Asynchronous Preset t AR Registered Output Clock e. Asynchronous reset Notes 1 ...

Page 25

KEY TO SWITCHING WAVEFORMS SWITCHING TEST CIRCUIT Output Specification Closed Open Closed H Z: Open Closed WAVEFORM INPUTS OUTPUTS Must be Will be ...

Page 26

TYPICAL I CHARACTERISTICS 5 25° 150 125 100 I CC (mA The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were ...

Page 27

TYPICAL I CHARACTERISTICS FOR THE PALCE22V10Z- 5 25° 110 (mA *Percent of product terms used. I vs. Frequency Graph for the PALCE22V10Z-15 CC TYPICAL ...

Page 28

... Parameter t Min Pattern Data Retention Time DR N Max Reprogramming Cycles INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR SELECTED /4 DEVICES* * Device Rev Letter PALCE22V10H-15 PALCE22V10H-20H H PALCE22V10H-25 PALCE22V10Q-25I I 28 Test Conditions Max Storage Temperature Normal Programming Conditions 100 k ESD Protection Input 100 k ...

Page 29

ROBUSTNESS FEATURES The PALCE22V10X-X/5 devices have some unique features that make them extremely robust, especially when operating in high-speed design environments. Pull-up resistors on inputs and I/O pins cause unconnected pins to default to a known state. Input clamping circuitry ...

Page 30

INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE22V10Z ESD Input Protection Transition and Detection Clamping Programming Pins only Programming Voltage Detection Typical Input V CC Provides ESD Protection and Clamping Preload Circuitry Typical Output PALCE22V10 and PALCE22V10Z Families Positive Programming ...

Page 31

POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. ...

Page 32

TYPICAL THERMAL CHARACTERISTICS PALCE22V10 Measured at 25°C ambient. These parameters are not tested. Parameter Symbol Parameter Description Thermal impedance, junction to case jc Thermal impedance, junction to ambient ja Thermal impedance, junction to ambient with air flow jma Plastic jc ...

Page 33

CONNECTION DIAGRAMS Top View SKINNYDIP/SOIC CLK ...

Page 34

... Zero Power (30 µA I standby) CC Valid Combinations PALCE22V10H-5 JC PALCE22V10H-7 PC, JC PALCE22V10H-10 PC, JC, SC, PI, JI PALCE22V10Q-10 PC, JC PALCE22V10H-15 PC, JC, PI, JI, SC PALCE22V10Q-15 PC, JC PALCE22V10H-20 PI, JI PALCE22V10H-25 PC, JC, SC, PI, JI PALCE22V10Q-25 PC, JC PALCE22V10Z-15 PI, JI PALCE22V10Z-25 PC, JC, SC, PI, JI Valid Combinations list configurations planned supported in volume for this device ...

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