HDMP-1012 Agilent Technologies, Inc., HDMP-1012 Datasheet

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HDMP-1012

Manufacturer Part Number
HDMP-1012
Description
Manufacturer
Agilent Technologies, Inc.
Datasheet
Low Cost Gigabit Rate
Transmit/Receive Chip Set
Technical Data
Features
Applications
5962-0049E (6/94)
Transparent, Extended
Implemented in a Low Cost
High-Speed Serial Rate 150-
Standard 100K ECL
Reliable Monolithic Silicon
On-chip Phase-Locked Loops
Backplane/Bus Extender
Video, Image Acquisition
Point to Point Data Links
Implement SCI-FI Standard
Implement Serial HIPPI
Ribbon Cable Replacement
Aluminum M-Quad 80
Package
1500 MBaud
Interface
16, 17, 20, or 21 Bits Wide
Bipolar Implementation
- Transmit Clock Generation
- Receive Clock Extraction
Specification
Description
The HDMP-1012 transmitter and
the HDMP-1014 receiver are used
to build a high speed data link for
point to point communication.
The monolithic silicon bipolar
transmitter chip and receiver chip
are each provided in a standard
aluminum M-Quad 80 package.
From the user’s viewpoint, these
products can be thought of as
providing a “virtual ribbon cable”
interface for the transmission of
data. Parallel data loaded into the
Tx (transmitter) chip is delivered
to the Rx (receiver) chip over a
serial channel, which can be
either a coaxial copper cable or
optical link.
The chip set hides from the user
all the complexity of encoding,
multiplexing, clock extraction,
demultiplexing and decoding.
Unlike other links, the phase-
locked-loop clock extraction
circuit also transparently provides
for frame synchronization - the
user is not troubled with the
periodic insertion of frame
synchronization words. In
addition, the dc balance of the
line code is automatically
maintained by the chip set. Thus,
the user can transmit arbitrary
data without restriction. The Rx
chip also includes a state-machine
HDMP-1012 Transmitter
HDMP-1014 Receiver
controller (SMC) that provides a
startup handshake protocol for
the duplex link configuration.
The serial data rate of the T/R link
is selectable in four ranges (see
tables on page 5), and extends
from 120 Mbits/s up to 1.25
Gbits/s. The parallel data interface
is 16 or 20 bit single-ended ECL,
pin selectable. A flag bit is
available and can be used as an
extra 17th or 21st bit under the
user’s control. The flag bit can
also be used as an even or odd
frame indicator for dual-frame
transmission. If not used, the link
performs expanded error
detection.
The serial link is synchronous,
and both frame synchronization
573

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HDMP-1012 Summary of contents

Page 1

... Implement SCI-FI Standard • Implement Serial HIPPI Specification 5962-0049E (6/94) Description The HDMP-1012 transmitter and the HDMP-1014 receiver are used to build a high speed data link for point to point communication. The monolithic silicon bipolar transmitter chip and receiver chip are each provided in a standard aluminum M-Quad 80 package. From the user’ ...

Page 2

... Available line will indicate the data as a Control Word the intention of this data sheet to provide the design engineer all of the information regarding the HDMP-1012/1014 chipset necessary to design this product into their application. To assist you in using this data sheet, the following Table of Contents is provided ...

Page 3

... A) 16/20 BIT SIMPLEX TRANSMISSION MUX Tx CLK B) 32/40 BIT SIMPLEX TRANSMISSION Tx CLK Tx CLK C) 32/40 BIT SIMPLEX TRANSMISSION WITH HIGH CLOCK RATES Tx CLK Rx CLK D) 16/20 BIT DUPLEX TRANSMISSION Tx CLK . . . . E) SIMPLEX BROADCAST TRANSMISSION Figure 1. Various Configurations Using the HDMP-1012/1014. Rx CLK Rx DEMUX CLK Rx CLK Rx CLK Rx CLK Tx CLK Rx CLK Rx CLK . . . . Rx ...

Page 4

... This allows the design to accommodate both ranges for maximum flexibility. This technique is recommended whenever operating near the maximum and minimum of two word rate ranges. The above information also applies to the HDMP-1012/ 1014 chipset when operating in 16 bit mode. ...

Page 5

... Mbits/s for a BER less than 10 -7 BER = 0/0 0/1 420 1/0 210 505 1/1 110 253 100 500 Figure 2: Typical 16-bit Mode Data Rates. HDMP-1012 (Tx), HDMP-1014 (Rx) Typical Operating Rates For 20 Bit Mode + -4 -5 Parallel Word Rate (Mword/sec) DIV1 DIV0 Range 62.5 (max ...

Page 6

... C-FIELD ENCODER DAV* FLAG D0-D19 D-FIELD ENCODER RST* Figure 4. HDMP-1012 Transmitter Block Diagram. HDMP-1012 Tx Block Diagram The HDMP-1012 was designed to accept bit wide parallel data and transmit it over a high speed serial line, while minimizing the user’s necessary interface to the high speed circuitry. In order ...

Page 7

The type of fill frames sent (FF0 or FF1) is determined by the FF input duplex system normally connected to the Rx’s STAT1 pin. The C-Field Encoder, based on the inputs ...

Page 8

... VCO Figure 5. HDMP-1014 Receiver Block Diagram. HDMP-1014 Rx Block Diagram The HDMP-1014 receiver was designed to convert a serial data signal sent from the HDMP-1012 into either 16,17 bit wide parallel data. In doing this, it performs the functions of • Clock Recovery • Data Recovery • Demultiplexing • ...

Page 9

Clock Select The Clock Select accepts the high speed digital signal from the VCO and outputs an internal high speed serial clock. The VCO frequency is divided, based on the DIV1/DIV0 inputs, to the input signal’s frequency range. The Clock ...

Page 10

... D00 - D19 ED, FF DAV*, CAV* FLAG t STRBOUT DOUT HCLK Figure 6. HDMP-1012 (Tx) Timing Diagram. 582 rate. The data must be valid before it’s sampled for the set-up time (t ), and remain valid after s it’s sampled for the hold time (t The set-up and hold times are referenced to STRBIN ...

Page 11

... D00 - D19 LINKRDY* DAV*, CAV* FF, ERROR FLAG STAT1 STAT0 Figure 7. HDMP-1014 (Rx) Timing Diagram. to the data frame’s boundary, while the rising edge is in the center of the data frame. The synchronous outputs, D00- D19, LINKRDY*, DAV*, CAV*, FF, ERROR, and FLAG, are updated for every data frame, ...

Page 12

... BLL Rise Time, Terminated with coupled r t ,BLL BLL Fall Time, Terminated with coupled f VSWR H50 Input VSWR i,H50 VSWR BLL Output VSWR o,BLL Note: 1. BLL outputs are measured with external 150 HDMP-1012 (Tx), HDMP-1014 (Rx) Typical Lock-Up Time DIV1 DIV0 HDMP-1012, msec Note: 1 ...

Page 13

... HDMP-1012 (Tx), HDMP-1014 (Rx) Absolute Maximum Ratings except as specified. Operation in excess of any one of these conditions may result in permanent damage to this device. Symbol V Supply Voltage EE V ECL Input Voltage IN,ECL V H50 Input Voltage IN,BLL I ECL Output Source Current O,ECL T Storage Temperature stg T Junction Temperature ...

Page 14

... STRBIN* 9 HCLKON 10 HCLK 11 HCLK* 12 HGND 13 LOUT 14 LOUT* 15 LOOPEN 16 DOUT 17 DOUT* 18 DIV0 19 DIV1 GND 23 GND 24 Figure 8. HDMP-1012 (Tx) Package Layout, Top View. PIN #1 ID CAP0B 1 CAP0A 2 CAP1A 3 CAP1B 4 GND 5 DIV0 6 DIV1 7 BCLK* 8 BCLK 9 TCLKSEL 10 TCLK* 11 TCLK 12 HGND 13 DIN* 14 DIN 15 LOOPEN 16 ...

Page 15

Tx I/O Definition Name Pin Type CAP0A 2 C Loop Filter Capacitor: CAP0A should be shorted to CAP0B. CAP1A CAP0B 1 should be shorted to CAP1B. A loop filter capacitor of 0.1 F must be CAP1A 3 connected across the ...

Page 16

Tx I/O Definition (cont’d.) Name Pin Type EHCLKSEL 78 I-ECL EHCLK Enable: When active, this input causes the STRBIN inputs to be used for the transmit serial clock, rather than the internal VCO clock. This is useful for generating extremely ...

Page 17

Tx I/O Definition (cont’d.) Name Pin Type INV 25 O-ECL Invert Signal: A high value of INV implies that the current frame is being sent inverted to maintain long-term DC balance. With a buffer, or pulled down with a 1K ...

Page 18

Tx I/O Definition (cont’d.) Name Pin Type STRBOUT 76 O-ECL Frame-rate Data Clock Output: This output is always a frame rate clock derived from STRBIN. With a buffer or pulled down with a 1K resistor to V oscilloscope for examining ...

Page 19

Rx I/O Definition Name Pin Type ACTIVE 25 I-ECL Chip Enable: This input is normally driven by the Rx state machine output. The ACTIVE signal is internally retimed by STRBOUT and presented to the user as the LINKRDY signal. This ...

Page 20

Rx I/O Definition (cont’d.) Name Pin Type ECLGND 32 S ECL Ground: Normally 0 volts. This ground is used for the ECL pad 52 drivers. For best performance it is suggested that coupling of the noisy 53 ECLGND to the ...

Page 21

Rx I/O Definition (cont’d.) Name Pin Type LIN LIN* 18 I-H50 Loop Back Serial Data Input: Use this input when LOOPEN is 17 active. Unlike the DIN, DIN* inputs, this input does not have a cable equalizer. In normal usage, ...

Page 22

Rx I/O Definition (cont’d.) Name Pin Type Power: Normally -5 V +10 594 Signal ...

Page 23

... ALL DIMENSIONS ARE IN MILLIMETERS (INCHES). Figure 10. Mechanical Dimensions of HDMP-1012 and HDMP-1014. dimensions conform to JEDEC plastic QFP specifications and are shown below in Figure 10. The M- Quad 80 package material is aluminum and the leads have been formed into a “Gull-Wing” ...

Page 24

... DATA FIELD 16/20 BITS SERIAL DATA FILL FRAME FRAME K Figure 11. HDMP-1012/1014 (Tx/Rx Pair) Line Code. Data Frame Codes When not in FLAGSEL mode, the FLAG bit is not user controllable and is alternately sent as 0 and 1 by the Tx chip during data frames to provide enhanced error detection. Control and Fill frames ...

Page 25

... HDMP-1012 (Tx), HDMP-1014 (Rx) Data Frame Structure M20SEL Not Asserted (16 bit data mode) Data Status Flag bit True 0 Inverted 0 True 1 Inverted 1 HDMP-1012 (Tx), HDMP-1014 (Rx) Data Frame Structure M20SEL Asserted (20 bit data mode) Data Status Flag bit True 0 Inverted 0 True 1 Inverted 1 Control Frame Codes 18 ...

Page 26

... HDMP-1012 (Tx), HDMP-1014 (Rx) Fill Frame Structure M20SEL Not Asserted (16 bit mode) Fill Frame D-Field 0 1111111 1a 1111111 1b 1111111 HDMP-1012 (Tx), HDMP-1014 (Rx) Fill Frame Structure M20SEL Asserted (20 bit mode) Fill Frame D-Field 0 111111111 1a 111111111 1b 111111111 598 C-Field ...

Page 27

... Tx Operation Principles The HDMP-1012 (Tx) is imple- mented in a high performance silicon bipolar process. The Tx performs the following functions for link operation: • Phase lock to frame rate clock • Clock multiplication • Frame encoding • Multiplexing In normal operation, the Tx phase ...

Page 28

... INTERNAL CLOCKS M20SEL CLOCK GENERATOR MDFSEL LOCK DETECT LOCKED Figure 12. HDMP-1012 (Tx) Phase-Locked Loop. 600 between high and low for data frames. This allows the link to perform more extensive error detection when the extra bit is unused. ACCMSB is the sign of the previously transmitted data. This is used to determine which type of FF1 should be sent ...

Page 29

... The frequency detector disable signal, FDIS, selects which detector to use. If synchronization in a link is not yet established, the HDMP-1012 (Tx) should send out Fill Frame 0 (FF0) or Fill Frame 1 (FF1) to the remote Rx. By setting FDIS=0, the Rx uses 0 0 ...

Page 30

... FDIS FREQ SIN PHASE STRBOUT CLOCK GEN Figure 14. HDMP-1014 (Rx) Phase-Locked Loop. the frequency detector to align its internal clock with the rising edge of FF0/FF1. Once frequency lock is accomplished, FDIS can be set to 1, then the PLL uses only the phase detector for synchronization adjustment and the Rx is ready to receive data ...

Page 31

... Rx chip provides a link handshake protocol enabling the duplex link to transition from frequency acquisition and training mode into data mode. The HDMP-1012/1014 Tx/Rx link uses an explicit frequency acquisition mode at startup that operates on a square-wave training sequence. This makes it possible to use a VCO with a very ...

Page 32

... FF0 1 ERROR RESET 2 Figure 15. HDMP-1014 (Rx) State Machine State Diagram. When the local port is in State the reset state, where both local Tx and Rx parallel interfaces are disabled. The local Tx transmits FF0 continuously, and the local Rx PLL is in the frequency detection mode. When ...

Page 33

... Since the data stream has no DC component, a coupling cap of 0 recommended for the DIN and LIN inputs. Full Duplex Figure 16 shows HDMP-1012/ 1014 in a full duplex configura- tion connecting two bidirectional (parallel) buses. Each end of the link has a Tx and RX pair. The receiver’ ...

Page 34

FF1, causing STAT0 to go high, which asserts the enable data (ED) pin on the Tx. The ED signal is retimed to signify to the host that the Tx is ready to send data (RFD). Other configurations for duplex ...

Page 35

... In both single and double frame modes, the data frame (D0-D19), flag bit (FLAG), and the data/control word available pins (DAV*, CAV*), must appear before the setup time t , and remain valid for the hold s time t . Refer to HDMP-1012 Tx h 607 ...

Page 36

Timing. Since the PLL of the Tx is designed with a very high-gain frequency/phase detector, the relative alignment of the internal clock and STRBIN is very tight, and is insensitive to temperature and other variations. The observed external changes are ...

Page 37

The setup and hold times are referenced to 1/2 frame period of D0-D19 deg, from the edges of STRBIN. The multiplexer delay should be mux considered for timing ...

Page 38

V EE PIN 1 CAP0B CAP0A D1 C2 CAP1A CAP1B HGND TOP VIEW HGND GND GND PIN 1 CAP0B CAP0A D1 C2 CAP1A CAP1B GND TOP ...

Page 39

I-ECL ECL OUTPUT Figure 21. I-ECL and O-ECL Simplified Circuit Schematic. found in the data sheet under I/O Definitions. I-ECL and O-ECL These I/O are designed to interface directly to ...

Page 40

ECL swings directly into 50 . The output impedance is matched to 50 with a VSWR of less than 2:1 to above 2 GHz. This output is ideal for driving the I- H50 input through a 50 cable and ...

Page 41

Likewise, the Vtt plane must also be bypassed equally well. In the positive 5 V supply configuration, the logic outputs are in the PECL (positive ECL) states. Commercial translation chips are available which will translate PECL between TTL and CMOS. ...

Page 42

LOOPEN = 0/1 selects either the normal data or the loop channels the I/O. MDFSEL = 0/1 selects the Tx single or double frame modes. ECHKSEL = 0/1 selects either to lock onto a frame-rate clock at STRBIN or to ...

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