HDMP-2689 Agilent Technologies, Inc., HDMP-2689 Datasheet
HDMP-2689
Specifications of HDMP-2689
Related parts for HDMP-2689
HDMP-2689 Summary of contents
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... Channel specification. It sup- ports SerDes-only mode using a 10-bit data interface with op- tional 8B/10B encoding for fast backplane applications. The HDMP-2689 runs at 2.125 GBd or 1.0625 GBd data rates and provides parallel-to-serial and serial-to-parallel conversion on four independent channels contained in one package. An on- ...
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... Fast Serial Backplanes Fiber Optic Interface (or Copper) HFBR-5720L HFBR-5720L HDMP-2689 HFBR-5720L HFBR-5720L Serial Interface Figure 1. HDMP-2689 Typical Applications. Functional Description Transmitter Description The HDMP-2689 transmitter contains four independent channels and a single TX PLL which generates the serial rate LOS RXAN RXAP ...
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... In0 RDA9 Figure 4. MAC to HDMP-2689 Interconnect. 3 Table 2 contains a summary of the data formats. Note that for the buffer mode (PMX=0), bit a, which corresponds to TDn9, is serialized first. For example, for K28.5 (0011111010), if the MAC’s Out0 through Out9 bits corre- spond to 0011111010, then the HDMP-2689’ ...
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... Figure 6. High Speed Output Pre-Emphasis. 4 TC[A-D] always operates at 106.25 MHz. The default settings for the HDMP-2689 are full rate opera- tion and DDR. Serial Data Outputs Through AC coupling, the high- speed outputs are capable of interfacing directly to copper ...
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... V. In addition, the HDMP-2689 provides a VREF output pin which may be used at the protocol IC in order to differentially detect a high or a low on RDn[9:0]. Alternatively, this voltage may be generated on the PCB using a resistor divider from VDDQ while ignoring the VREF output of the HDMP-2689. ...
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... A (00) must be avoided as it results in unde- fined behavior. The specific configuration and status informa- tion that can be set or read from HDMP-2689 is presented in the section titled Management Interface Registers. This section defines the complete assignment of management registers and specifies which registers are ...
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... When this bit is logic 1, bit 12 of register 27 signals pass (logic 0) or fail (logic 1). To allow link debugging: • Configure the HDMP-2689 for internal loopback (data pro- vided at the parallel input is looped back to the parallel output after traversing the chip) via management interface register 25 bit 13 ...
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Table 1. PMX Encoding Definitions. PMX Mode Description 0 Buffer TX: Inputs are phase adjusted to transmit clock and serialized MSB (a) first. RX: Serial data is byte aligned and presented with first bit (a) as MSB 1 Codec TX: ...
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... TDn[9: CDH CDH Case B. Tx Full Rate DDR Timing Test Conditions GND IH DDQ IL Figure 9. Transmitter Timing Diagram. Table 4. HDMP-2689 Transmitter Section Timing Characteristics 0° 85° 2 DDQ DD Symbol Parameters 1G [1,2] Tx Clock to data skew time; the data must be stable by T ...
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CHAR A TXP/N TXLAT TD[0:9] 10-BIT CHAR B TC Figure 10. Transmitter Latency. Table 5. Receiver Data Rate. Management Register 17 Input Setting Case Full/Half 18.8 ns RCn RDn[9: ...
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... HDMP-2689 Receiver Section Timing Characteristics 0° 85° 2 DDQ Symbol Parameters PWreset Width of reset pulse f lockRX The time that the RX PLL takes to frequency lock to the data after reset B_sync_lock Bit Sync time after f lockRX B_sync_rate Bit Sync time after rate switch ...
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CHAR B RXP/N RD[0] RXLAT RD[0:9] RC Figure 14. Receiver Latency. Table 7. IEEE JTAG 1149.1 Instructions. Instruction Opcode EXTEST 00000_00000 SAMPLE 00000_00010 CLAMP 00000_00100 HIGHZ 00000_01000 BYPASS 11111_11111 Table 8. Format of a Management Frame ...
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... Unit (HDMP-2689) drives Isb (least significant bit) of read register data B Unit (HDMP-2689) releases the MDIO line Note: For more information, see the IEEE 802.3 Part 3 22.2.4.5. "Management Frame Structure." MDIO Timing, Last Bit of Read Register Data, Bus Released by the HDMP-2689. Figure 17. MDIO Timing Diagrams ...
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... Table 10. HDMP-2689 Absolute Maximum Ratings. Sustained operation at or beyond any of these conditions may result in long-term reliability degradation or permanent damage, and is not recommended. Symbol Parameters V I/O supply voltage DDQ V Supply voltage – digital core DD V Analog supply voltage DDA T Storage temperature (not biased) ...
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... TERM [2] V Output High voltage OH [2] V Output Low voltage OL Notes the MAC device I/O supply voltage. DDQ 2. See Figure 12 for measurement conditions. Table 16. HDMP-2689 CMOS I/O Operating Conditions 0° 85° 2 DDQ Symbol Parameters V Input High voltage IH V Input Low voltage ...
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... See Figure 12 for test conditions. 3. SSTL_2 AC Input Signals meet JEDEC Standard No. JESD8-9A test conditions (minimum slew rate 1.0V/ns). See JEDEC Table 3. 4. Note LOS pin description. 5. Measured at default settings, maximum amplitude and medium peaking (11111011). Table 18. HDMP-2689 Transmitter Section Output Jitter Characteristics 0° 85° ...
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Figure 18. Serial Output Eye Diagram. Figure 19. Serial Output Random Jitter with TX pre-emphasis off. 17 ...
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... 2.125 GHz 70311A CLOCK SOURCE 83480A OSCILLOSCOPE CH2 DIVIDE TRIGGER BY 20 CH1 TXnN 106.25 MHz TXnP HDMP-2689 0.1 µF RFCP 100 Ω TDn[9:0] RFCN Balun 0.1 µF TDn[9:0] b) BLOCK DIAGRAM OF DJ MEASUREMENT METHOD Units Min pF CH2 70841B PATTERN GENERATOR* TXnN +K28.5, -K28.5 ...
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... CHAMFER 3.55 14.80 MAX TOP VIEW 1.00 1.50 REF 1.00 1.50 REF BOTTOM VIEW 289 Solder Balls Pin 1 Corner Agilent HDMP-2689 LLLLLLLLL-NN G YYWW B2.3 AAAAAAAAAAA Figure 21. Package Layout and Marking Top View. 19 0.20 (4X) A +0.35 –0.05 B 3.55 30° TYP 14.80 MAX. 17.70 +0.35 –0.05 19.00 7.30 0.80 ± 0.05 A1 BALL PAD CORNER 4 6 ...
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... Figure 22. Guidelines for Decoupling Capacitor Connections. Figure 23. Recommended Decoupling Capacitor Placement. 20 0.01µF 0.1µF VDDA 3 VDDA 3 VDDA 3 VDDA 3 VDDA 3 HDMP-2689 GUIDELINES FOR DECOUPLING CAPACITOR PLACEMENTS/CONNECTIONS VDD VDD VDD VDD VDD VDD 0.01µF (1A/30 OHMS /100 MHz) VDDA _1 0.1µF 0.1µF 10µ ...
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Pin Diagram Transceiver Pinout (Top View) (Rev 1.0) 19mm x 19mm body, 17mm by 17mm array, 289 pins populated, 1mm ball pitch RXAP GNDA RXBP VDDA2 TXAP B RXAN VDDA1 RXBN GNDA TXAN C ...
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Pin List I/O DEFINITION Name Pin Type Signal RSTN F05 I-CMOS Chip Reset (FIFO Clear): Active Low DVAD0 F17 I-CMOS Device Address Input: 3 Bit input address with DVAD2 as MSB. Full address is the Device Address followed by the ...
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Pin List, continued I/O DEFINITION Name Pin Type Signal RDD0 K15 O-SSTL2 Receive Data Pins, Channel D: Parallel data on this bus is valid on the rising and falling edges of RCD. See Table 2 for RDD1 L16 interpretation of ...
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Pin List, continued I/O DEFINITION Name Pin Type Signal TDC0 T09 I-SSTL2 Data Inputs: Parallel data on this bus is clocked in by TCC. See timing diagram in Figure 9. See Table 2 for interpretation TDC1 U10 of this bus ...
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Pin List, continued I/O DEFINITION Name Pin Type Signal GNDIN D01, E14, Receiver Ground: Supply used for input receiver. H13, M06, M12, N08 N10 GNDD E01, E17, S Dirty Ground: Supply used by all the N-drivers on the digital pad ...
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Management Interface Registers Notes: All registers from not mentioned below are reserved and should not be accessed. RO means read only (any value written will be discarded). RW means the value can be read or written. Reserved ...
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Management Interface Registers, continued Reg 20 Rx Loss of Signal 15 RX Loss of Signal (reset to 0) 14:0 Reserved Register 20 is the RX loss of signal equivalent to the LOSn pins, for channels A through D, ...
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... India, Australia, New Zealand: (65) 6755 1939 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (65) 6755 2044 Taiwan: (65) 6755 1843 Data subject to change. Copyright © 2004 Agilent Technologies, Inc. Obsoletes 5988-8120EN February 25, 2004 5988-9185EN Default Mode 0 Reserved RW ...