SAB-C501G-L24N Siemens Semiconductor Group, SAB-C501G-L24N Datasheet
SAB-C501G-L24N
Specifications of SAB-C501G-L24N
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SAB-C501G-L24N Summary of contents
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Microcomputer Components 8-Bit CMOS Microcontroller C501 Data Sheet 04.97 ...
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C501 Data Sheet Revision History : Previous Releases : Page Page Subjects (changes since last revision) (previous (new version) version) general C501G-1E OTP version included 4 4 Ordering information resorted and C501G-1E types added 5 5 Table with literature hints ...
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... P-DIP-40, P-LCC-44, and P-MQFP-44 package • Temperature ranges : Power Saving Modes T2 Figure 1 C501G Functional Units Semiconductor Group T SAB-C501 : 0 ˚ ˚ SAF-C501 : – 40 ˚ ˚C A RAM 256 CPU USART ROM (C501-1R) ...
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... The term C501 refers to all versions within this specification unless otherwise noted. Further, the term C501 refers to all versions which are available in the different temperature ranges, marked with SAB-C501... or SAF-C501.... . Ordering Information Type Ordering Code Package SAB-C501G-LN Q67120-C969 SAB-C501G-LP Q67120-C968 SAB-C501G-LM Q67127-C970 SAB-C501G-L24N Q67120-C1001 SAB-C501G-L24P Q67120-C999 SAB-C501G-L24M Q67127-C1014 SAB-C501G-L40N Q67120-C1002 SAB-C501G-L40P Q67120-C1000 SAB-C501G-L40M Q67127-C1009 ...
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Note: Versions for extended temperature range – 40 ˚C to 110 ˚C (SAH-C501G) on request. The ordering number of ROM types (DXXX extensions) is defined after program release (verification) of the customer. Additional Literature For further information about the C501 ...
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T2/P1.0 T2EX/P1.1 RESET RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 Figure 3 Pin Configuration P-DIP-40 Package (top view) Semiconductor Group 1 2 P1.2 3 P1.3 4 P1.4 5 P1.5 6 P1 C501 11 ...
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P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V CC N.C. P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 Figure 4 Pin Configuration P-MQFP-44 Package (top view) XTAL1 XTAL2 RESET ALE/PROG PSEN Figure 5 Logic Symbol Semiconductor Group ...
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Table 1 Pin Definitions and Functions Symbol Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 P1.0 – P1.7 2–9 1– Input O = Output Semiconductor Group I/O*) Function 40–44, I/O Port 1 1– quasi-bidirectional ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 P3.0 – P3.7 11, 10–17 13– Input O ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 XTAL2 20 18 XTAL1 21 19 P2.0 – P2.7 24–31 21– Input O = Output Semiconductor Group I/O*) Function 14 – XTAL2 Output of ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 PSEN 32 29 RESET 10 9 ALE/PROG EA Input O = Output Semiconductor Group I/O*) Function 26 O ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-44 P-DIP-40 P-MQFP-44 P0.0 – P0.7 43–36 39– N.C. 1, 12, – 23 Input O = Output Semiconductor ...
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Functional Description The C501 is fully compatible to the standard 8051 microcontroller family compatible with the 80C32/52/82C52. While maintaining all architectural and operational characteristics of the 8051microcontroller family, the C501 incorporates some enhancements in the timer 2 unit. ...
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CPU The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
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Memory Organization The C501 CPU manipulates data and operands in the following four address spaces: – Kbyte of internal/external program memory – Kbyte of external data memory – 256 bytes of internal data memory ...
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... The 27 special function registers (SFRs) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-2 are 0 (e. ..., are bitaddressable. The SFRs of the C501 are listed in table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks of the C501 ...
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... Pow. Sav. PCON 2) Power Control Register Modes 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved Semiconductor Group Address Contents after ...
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... CD H TH2 PSW ACC means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Semiconductor Group Bit 6 Bit 5 Bit 4 Bit ...
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Timer / Counter 0 and 1 Timer/counter 0 and 1 can be used in four operating modes as listed in table 4. Table 4 Timer/Counter 0 and 1 Operating Modes Mode Description 0 8-bit timer/counter with a divide-by-32 prescaler 1 ...
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Timer 2 Timer 16-bit timer/counter with an up/down count feature. It can operate either as timer event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in table ...
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Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 6. The possible baudrates can be calculated using the formulas given in table 7. Table ...
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Interrupt System The C501 provides 6 interrupt sources with two priority levels. Figure 9 gives a general overview of the interrupt sources and illustrates the request and control flags. Timer 0 Overflow Timer 1 Overflow Timer 2 Overflow P1.1/ T2EX ...
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Table 8 Interrupt Sources and their Corresponding Interrupt Vectors Source (Request Flags) IE0 TF0 IE1 TF1 TF2 + EXF2 A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low- priority interrupt. ...
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Power Saving Modes Two power down modes are available, the Idle Mode and Power Down Mode. The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If the Power Down mode ...
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OTP Operation The C501-1E is programmed by usng a modified Quick-Pulse Programming from older methods in the value used for V number of the ALE/PROG pulses. The C501-1E contains two signature bytes that can be read and used by a ...
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... For programming of the security bits, the 25 pulse programming sequence must be repeat using the “Program security bit“ levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bit can still be programmed. Note that the EA/V ...
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MHz Figure 10 C501-1E OTP Memory Programming Configuration ALE/PROG 1 ALE/PROG 0 Figure 11 C501-1E ALE/PROG Waveform Semiconductor Group Port 1 C501-1E RESET Port 0 P3.6 P3.7 EA/ ALE/PROG XTAL2 PSEN ...
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MHz Figure 12 C501-1E OTP Memory Verification Semiconductor Group Port 1 C501-1E RESET P3.6 Port 0 P3.7 EA/ XTAL2 ALE/PROG PSEN XTAL1 P2 MCS03235 ...
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Absolute Maximum Ratings Ambient temperature under bias ( Storage temperature ( T ) .......................................................................... – 150 C stg V Voltage on pins with respect to ground ( CC Voltage on any pin with respect to ground ( ...
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... IO I – – 4 – 36 – 8 – 56 – 12 – for the SAB-C501 for the SAF-C501 Unit Test Condition V – 0.1 V – – 0.3 V – 0.1 V – 0.5 V – 0 0.5 V – 1 3.2 mA ...
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... TL I – – – – – 36 – – for the SAB-C501 for the SAF-C501 Unit Test Condition V – 0.1 V – – 0.1 V – 0.1 V – 0.5 V – 0 0.5 V – 1 ...
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... CC XTAL1 driven with CLCH CHCL EA = Port0 = RESET all other pins are disconnected. CC used (appr (Idle mode) is measured with all output pins disconnected and with all peripherals disabled; CC XTAL1 driven with CLCH CHCL RESET = Port0 = ...
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... PLIV t 0 – PXIX t *) – 63 PXIZ – PXAV t – 302 AVIV t 0 – AZPL 33 for the SAB-C501 Limit Values Variable Clock 3.5 MHz to 12 MHz CLCL min. max – 40 – CLCL t – 40 – CLCL t – 53 – CLCL t – 4 – ...
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AC Characteristics for C501-L / C501-1R / C501-1E (cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid ...
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... PLIV t 0 – PXIX t *) – 32 PXIZ – PXAV t – 148 AVIV t 0 – AZPL 35 for the SAB-C501 Limit Values Variable Clock 3.5 MHz to 24 MHz CLCL min. max – 40 – CLCL t – 25 – CLCL t – 25 – CLCL t – 4 – 87 ...
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AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 (cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid ...
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... PLIV t 0 – PXIX t *) – 20 PXIZ – PXAV t – 65 AVIV t – 5 – AZPL 37 for the SAB-C501 Limit Values Variable Clock 3.5 MHz to 40 MHz CLCL min. max – 15 – CLCL t – 15 – CLCL t – 15 – CLCL t – 4 – 45 CLCL t – ...
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AC Characteristics for C501-L40 / C501-1R40 (cont’d) External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in ...
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ALE PSEN Port 0 Port 2 Figure 13 Program Memory Read Cycle Semiconductor Group t LHLL t t AVLL PLPH t LLPL t LLIV t PLIV t AZPL t LLAX Instr.IN t AVIV A8 - A15 39 ...
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ALE PSEN RD t AVLL from Port DPL t AVWL Port 2 Figure 14 Data Memory Read Cycle Semiconductor Group t LLDV t t LLWL RLRH t RLDV t LLAX2 t RLAZ Data IN ...
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ALE PSEN WR t AVLL from Port DPL t AVWL Port 2 Figure 15 Data Memory Write Cycle V - 0.5V CC 0.7 V 0.2 0.45V Figure 16 External Clock Drive at XTAL2 ...
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ROM Verification Characteristics for C501-1R ROM Verification Mode 1 Parameter Address to valid data ENABLE to valid data Data float after ENABLE Oscillator frequency P1.0 - P1.7 P2.0 - P2.4 Port 0 P2.7 ENABLE Address: P1 ...
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OTP Programming and Verification Characteristics 10 Parameter Programming supply voltage Programming supply current Oscillator frequency Address setup to ALE/PROG low Address hold after ALE/PROG Data setup to ALE/PROG ...
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P1.0 - P1.7 P2.0 - P2.4 Port 0 t DVGL t AVGL ALE/PROG t GLGH t SHGL EA EHSH P2.7 ENABLE Figure 18 C501-1E OTP Memory Program/Read Cycle Semiconductor Group Programming Address Data t GHDX t GHAX ...
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Inputs during testing are driven at measurements are made at Figure 19 AC Testing: Input, Output Waveforms V +0.1 V Load V Load -0 Load For timing purposes a port pin ...
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Package Outlines Plastic Package, P-DIP-40 for C501G-L / C501G-1R (Plastic Dual in-Line Package) Figure 22 P-DIP-40 Package Outlines Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Semiconductor Group 46 C501 Dimensions ...
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Plastic Package, P-LCC-44 – SMD for C501G-L / C501G-1R / C501G-1E (Plastic Leaded Chip-Carrier) Figure 23 P-LCC-44 Package Outlines Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted ...
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Plastic Package, P-MQFP-44 – SMD for C501G-L / C501G-1R (Plastic Metric Quad Flat Package) Figure 24 P-MQFP-44 Package Outlines Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted ...