CS492405-CL Cirrus Logic, Inc., CS492405-CL Datasheet

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CS492405-CL

Manufacturer Part Number
CS492405-CL
Description
CS492405-CLCirrus Logic [Multi-Channel Digital Audio Decoders]
Manufacturer
Cirrus Logic, Inc.
Datasheet

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Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS4923/4/5/6/7/8 features
— Optional Virtual 3D Output
— Simulated Surround and Programmable Effects
— Real Time Autodetection of Dolby Digital
— Flexible 6-channel master or slave output
CS4923/4/5/6/7/8/9 features
— IEC60958/61937 transmitter for compressed-
— Dedicated 8 kilobyte input buffer
— DAC clock via analog phase-locked loop
— Dedicated byte wide or serial host interface
— Multiple compressed data input modes
— PES layer decode for A/V synchronization
— 96-kHz-capable PCM I/O, master or slave
— Optional external memory and auto-boot
— +3.3-V CMOS low-power, 44-pin package
CS4923/4/5/6 features
— Capable of Dolby Digital
— Dolby bass manager and crossover filters
— Dolby Surround Pro Logic
CS4925/7: MPEG-2 Multi-Channel Decoder
CS4926/8: DTS Multi-Channel Decoder
CS4929: AAC 2-Channel (Low Complexity)
and MPEG-2 Stereo Decoder
DTS
data or linear-PCM output
®
, MPEG Multi-Channel and PCM
Multi-Channel Digital Audio Decoders
CMPREQ,
LRCLKN2
STCCLK2
LRCLKN1
CMPCLK,
SDATAN1
SDATAN2
CMPDAT,
SCLKN1,
SCLKN2
CLKSEL
CLKIN
FILT2
®
Compressed
Data Input
RESET
Interface
Interface
Digital
Audio
Clock Manager
Group A Performance
Input
FILT1
®
PLL
Decoding
EMAD7:0,
VA
DATA7:0,
GPIO7:0
RAM Input
AGND
Controller
Framer
Shifter
Buffer
Input
Buffer
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
CS
GPIO11
EMOE,
R/W,
DGND[3:1]
RD,
®
Program
Program
Memory
Memory
DSP Processing
ROM
RAM
,
GPIO10
Parallel or Serial Host Interface
EMWR,
WR,
24-Bit
DS,
STC
Copyright
Memory
Memory
VD[3:1]
ROM
RAM
Data
Data
SCDOUT,
SCDIO,
Description
The CS4923/4/5/6/7/8 is a family of multi-channel digital
audio decoders, with the exception of the CS4929 as the
only stereo digital audio decoder. The CS4923/4/5/6 are
designed for Dolby Digital and MPEG-2 Stereo decoding. In
addition the CS4925 adds MPEG-2 multi-channel decoding
capability and the CS4926 provides DTS decoding. The
CS4927 is an MPEG-2 multi-channel decoder and the
CS4928 is a DTS multi-channel decoder. The CS4929 is an
AAC 2-channel and MPEG-2 stereo decoder. Each one of
the CS4923/4/5/6/7/8/9 provides a complete and flexible
solution for multi-channel (or stereo in the case of the
CS4929) audio decoding in home A/V receiver/amplifiers,
DVD movie players, out-board decoders, laser-disc players,
HDTV sets, head-end decoders, set-top boxes, and similar
products.
Cirrus Logic’s Crystal Audio Division provides a complete set
of audio decoder and auxiliary audio DSP application
programs for various applications. For all complementary
analog and digital audio I/O, Crystal Audio also provides a
complete set of high-quality audio peripherals including:
multimedia CODECs, stereo A/D and D/A converters and
IEC60958 interfaces. Of special note, the CS4226 is a
complementary CODEC providing a digital receiver, stereo
A/D converters, and six 20-bit DACs in one package.
ORDERING INFORMATION
GPIO9
PSEL,
(All Rights Reserved)
CS4923xx-CL 44-pin PLCC (xx = ROM revision)
CRD4923
CDB4923
SCCLK
A0,
Output
Buffer
Cirrus Logic, Inc. 1999
RAM
SCDIN
A1,
CS4923/4/5/6/7/8/9
INTREQ
ABOOT,
Formatter
Output
Reference design with CS4226
Evaluation board
EXTMEM,
GPIO8
DD
DC
MCLK
SCLK
LRCLK
AUDATA[2.0]
XMT958
DS262F2
AUG ‘99
1

Related parts for CS492405-CL

CS492405-CL Summary of contents

Page 1

... PLL STC FILT1 VA AGND DGND[3:1] VD[3:1] This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 1999 (All Rights Reserved) CS4923/4/5/6/7/8/9 Reference design with CS4226 Evaluation board A1, ABOOT, EXTMEM, INTREQ GPIO8 ...

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... Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions ...

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I C Serial Host Interface .................................................................................................. 39 2 6.4 Write ......................................................................................................... 39 2 6.4 Read ......................................................................................................... 39 6.5 External Memory .............................................................................................................. 41 6.5.1 External Memory and Autoboot ...................................................................... 43 7. DIGITAL INPUT & OUTPUT ...

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CHARACTERISTICS AND SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; all voltages with respect Parameter DC power supplies: Input current, any pin except supplies Digital input voltage Ambient operating temperature (power applied) Storage temperature WARNING: ...

Page 5

SWITCHING CHARACTERISTICS—RESET ( VA 3.3 V 5%; Inputs: Logic 0 = DGND, Logic Parameter RESET minimum pulse width low All bidirectional pins high-Z after RESET low Configuration bits setup before ...

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SWITCHING CHARACTERISTICS—CMPDAT, CMPCLK ( VA 3.3 V 5%; Inputs: Logic 0 = DGND, Logic Parameter Serial compressed data clock CMPCLK period CMPDAT setup before CMPCLK high CMPDAT hold after CMPCLK ...

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SWITCHING CHARACTERISTICS—CLKIN ( VA 3.3 V 5%; Inputs: Logic 0 = DGND, Logic Parameter CLKIN period for internal DSP clock mode CLKIN high time for internal DSP clock mode CLKIN ...

Page 8

SWITCHING CHARACTERISTICS—INTEL ( VA 3.3 V 5%; Inputs: Logic 0 = DGND, Logic Parameter Address setup before CS and RD low or CS and WR low Address hold time after ...

Page 9

A1:0 T DATA7:0 T ias CS T icdr WR RD A1:0 T DATA7:0 T ias CS T icdw RD WR DS262F2 iah T idhr T idd T idis T T irpw ird Figure 5. Intel Parallel Host Mode Read Cycle ...

Page 10

SWITCHING CHARACTERISTICS—MOTOROLA ( VA 3.3 V 5%; Inputs: Logic 0 = DGND, Logic Parameter Address setup before CS and DS low Address hold time after CS and DS low Delay ...

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A1:0 DATA7:0 T mas CS T mrwsu R/W DS Figure 7. Motorola Parallel Host Mode Read Cycle A1:0 T mas DATA7:0 CS R/W DS Figure 8. Motorola Parallel Host Mode Write Cycle DS262F2 T mah T mdhr T mdd T ...

Page 12

SWITCHING CHARACTERISTICS—SPI CONTROL PORT ( VA 3.3 V 5%; Inputs: Logic 0 = DGND, Logic Parameter SCCLK clock frequency CS falling to SCCLK rising Rise time of SCCLK line Fall ...

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CS t css t scl SCCLK t sch SCDIN t cdisu t cdih SCDOUT INTREQ R/W MSB MSB t scdov t scdov t scrh Figure ...

Page 14

SWITCHING CHARACTERISTICS— VA 3.3 V 5%; Inputs: Logic 0 = DGND, Logic Parameter SCCLK clock frequency Bus free time between transmissions Start-condition hold time (prior to first clock ...

Page 15

A6 A5 SCDIO t buf t sud 1 0 SCCLK t hdst t low t hdd t high INTREQ A0 ACK MSB R/W t scsdv sca 2 Figure 10. ...

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SWITCHING CHARACTERISTICS—DIGITAL AUDIO INPUT ( VA 3.3 V 5%; Inputs: Logic 0 = DGND, Logic Parameter SCLKN1(2) period for both Master and Slave mode SCLKN1(2) duty cycle for Master and ...

Page 17

Figure 11. Digital Audio Input, Data and Clock Timing DS262F2 MASTER MODE SCLKN1 SCLKN2 T lrds LRCLKN1 LRCLKN2 T T sdsum sdhm SDATAN1 SDATAN2 SLAVE MODE SCLKN1 SCLKN2 T lrts LRCLKN1 LRCLKN2 T T sdsus sdhs SDATAN1 SDATAN2 CS4923/4/5/6/7/8/9 T ...

Page 18

SWITCHING CHARACTERISTICS—DIGITAL AUDIO OUTPUT ( VA 3.3 V 5%; measurements performed under static conditions.) A Parameter MCLK period MCLK duty cycle SCLK period for Master or Slave mode SCLK duty cycle for Master or Slave ...

Page 19

MCLK (Input) SCLK (Output) MCLK (Output) SCLK (Output) SCLK LRCLK AUDATA2:0 SCLK LRCLK AUDATA2:0 Figure 12. Digital Audio Output, Data and Clock Timing DS262F2 T mclk T sdmi T mclk T sdmo MASTER MODE T sclk T lrds T adsm ...

Page 20

... As discussed above, compressed audio can be packed in IEC61937, PES, or elementary formats depending on the decoder environment. Each for- mat is supported by a separate download of appli- cation code. Consult the relevant Application Code CS4923/4/5/6/7/8/9 Revision D CS492305 CS492405 CS492505 CS492604 CS492705 CS492804 CS492906 Table 1. Silicon Revisions will ...

Page 21

User’s Guide to determine which formats are sup- ported by a particular application. A brief descrip- tion of each format is presented below. Elementary - an elementary bitstream consists only of compressed audio data (e.g., strictly the Dolby Digital bitstream); ...

Page 22

The ‘ANXXX’ notation denotes the application note number under which the respective user’s guide was released. 2.2.1 Hardware Documentation CS4923/4/5/6/7/8/9 Family Data Sheet - This document describes the electrical characteristics of the device from timing to base ...

Page 23

TYPICAL CONNECTION DIAGRAMS Six typical connection diagrams have been presented to illustrate using the device with the different communication modes available. They are as follows: 2 Figure 13 Control 2 Figure 14 Control with External ...

Page 24

Termination Requirements The CS4923/4/5/6/7/8/9 incorporates open drain pins which must be pulled high for proper operation. INTREQ (pin 20) is always an open drain pin which requires a pull-up for proper 2 operation. When in the I C serial ...

Page 25

Supply (+3.3VD) NOTE: A capacitor pair ( and 0.1 uF) must be supplied for each power pin. NOTE: +3.3VA is simply +3.3VD after fil tering through the ferrite bead. Pin 32 must be referenced to +3.3VA + ...

Page 26

Supply (+3.3VD) SYSTEM CONTROL LER OCTAL F/ F OCTAL F/ F A[15:8] Q[7:0] Q[7:0] D[7:0] D[7:0] A[7:0] D[7:0] 26 ...

Page 27

Supply (+3.3VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +3.3VA is simply +3.3VD after filt ering through the ferrite bead. Pin 32 must be referenced to +3.3VA + 1 ...

Page 28

Supply (+3.3VD) SYSTEM CONTROL LER / OCTAL F/ F OCTAL F/ F A[15:8] Q[7:0] Q[7:0] D[7:0] D[7:0] A[7:0] D[7:0] 28 NOTE: A ...

Page 29

Supply (+3.3VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +3.3VA is simply +3.3VD after filt ering through the ferrite bead. Pin 32 must be referenced to +3.3VA + + ...

Page 30

Supply (+3.3VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +3.3VA is simply +3.3VD after filt ering through the ferrite bead. Pin 32 must be referenced to +3.3VA + + ...

Page 31

POWER The CS492X requires a 3.3V digital power supply for the digital logic within the DSP and a 3.3V analog power supply for the internal PLL. There are three digital power pins, VD1, VD2 and VD3, along with three ...

Page 32

CLOCKING Revision D of the CS4923/4/5/6/7/8/9 also incorporates a programmable phase locked loop (PLL) clock synthesizer. The PLL takes an input reference clock and produces all the internal clocks required to run the internal DSP and to provide master ...

Page 33

CONTROL Control of the CS4923/4/5/6/7/8/9 can be accomplished through one of four methods. The 2 CS492X supports I C communication. In addition the CS492X supports both a Motorola and Intel byte wide parallel host control mode. Only one of ...

Page 34

CS4923/4/5/6/7/8/9 Hardware User’s Guide. Application configuration is described in the application code user’s guide for the code being used. 6.2 Parallel Host Interface The byte wide parallel host interface of the CS492X supports application code download, communication ...

Page 35

Host Message (HOSTMSG) Register, A[1:0] = 00b 7 6 HOSTMSG7 HOSTMSG6 HOSTMSG5 HOSTMSG7–0 Host data to and from the DSP. A read or write of this register operates handshake bits between the internal DSP and the external host. This register ...

Page 36

Motorola Parallel Host Mode Motorola parallel host mode is accomplished with CS, DS, R/W, A[1:0], and DATA[7:0]. Table 6 shows the pin name, pin description and pin number of each signal on the CS4923/4/5/6/7/8/9. In Motorola host interface mode, ...

Page 37

SPI Write When writing to the device in SPI, the same protocol can be used for sending a byte, a word or an entire download image as long as transfers occur on byte boundaries. Figure 19 illustrates the relative ...

Page 38

SCCLK SCDIN AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W CS SCCLK SCDIN AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W SCDOUT CS INTREQ Notes: 1. INTREQ is guaranteed to stay low until the rising edge of SCCLK for the ...

Page 39

I C Serial Host Interface 2 For I C communications the CS4923/4/5/6/7/8/9 always acts as a slave. Serial I with the CS4923/4/5/6/7/8/9 is accomplished with 3 communication lines: SCCLK, SCDIO and INTREQ. Table 8 shows the mnemonic, pin ...

Page 40

I2C Start SCCLK SCDIO AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W ACK D7 I2C Start SCCLK SCDIO AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W ACK D7 INTREQ Note 1 Notes: 1. The ACK for the address byte is ...

Page 41

Following the address byte the host must clock out an acknowledge from the part. After the address byte, the host should clock out data from the device one byte at a time until INTREQ is no longer low. The host ...

Page 42

EMAD[7:0] CS4923/4/5/6/7/8 EXTMEM EMOE EMAD7:0 42 3.3V 8 ADDR[7: 3.3V 8 BIT D Q '574 8 BIT '574 ...

Page 43

Although the memory can use more address bits, typically only 16 bits of address space are used. For this reason the memory incorporates a 2 latch memory architecture. The two latch external memory architecture is required for the CS4926 or ...

Page 44

DIGITAL INPUT & OUTPUT The CS4923/4/5/6/7/8/9 supports a wide variety of data input and output mechanisms through various input and output ports. Hardware availability is entirely dependent on whether the software application code being used supports the required mode. ...

Page 45

LRCK SCLK SDATA LRCK SCLK SDATA MSB LRCLK SCLK SDATA LSB LRCLK SCLK SDATA MSB LSB MSB M Clocks M Clocks Per Channel Per Channel DS262F2 Left MSB LSB MSB Figure 24. Format Left LSB MSB Figure ...

Page 46

Digital Audio Input Port The digital audio input port, or DAI, is used for both compressed and PCM digital audio data input. In addition this port supports a special clocking mode in which a clock can be input to ...

Page 47

In parallel host mode, the CS4923/4/5/6/7/8/9 can accept PCM data written through the byte-wide host interface to address 10b (A1 high, A0 low). In this mode, there is a close connection between the CS4923/4/5/6/7/8/9 application code and the host processor ...

Page 48

Serial digital audio data bit placement and sample alignment is fully configurable CS4923/4/5/6/7/8/9 including left justified, right justified, delay bits or no delay bits, variable sample word ...

Page 49

PIN DESCRIPTIONS VD1 DGND1 XMT958 WR,DS,EMWR,GPIO10 RD,R/W,EMOE,GPIO11 A1, SCDIN A0, SCCLK DATA7,EMAD7,GPIO7 DATA6,EMAD6,GPIO6 DATA5,EMAD5,GPIO5 DATA4,EMAD4,GPIO4 VD2 DGND2 DATA3,EMAD3,GPIO3 DATA2,EMAD2,GPIO2 DATA1,EMAD1,GPIO1 DATA0,EMAD0,GPIO0 CS SCDIO, SCDOUT,PSEL,GPIO9 ABOOT, INTREQ EXTMEM, GPIO8 SDATAN1 VA—Analog Positive Supply: Pin 34 Analog positive supply for clock ...

Page 50

FILT2—Phase Locked Loop Filter: Pin 32 Connects to an external filter for the on-chip phase-locked loop. This pin does not meet Cirrus Logic’s ESD tolerance of 2000 V using the human body model. This pin will tolerate ESD of 1000 ...

Page 51

WR, DS, EMWR, GPIO10—Host Write Strobe or Host Data Strobe or External Memory Write Enable or General Purpose Input & Output Number 10: Pin 4 In Intel parallel host mode, this pin serves as the active-low data-write-input strobe. In Motorola ...

Page 52

AUDATA1—Digital Audio Output 1: Pin 40 PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT AUDATA0—Digital Audio Output 0: Pin 41 PCM multi-format digital-audio ...

Page 53

LRCLKN1—PCM Audio Input Sample Rate Clock: Pin 26 Bidirectional digital-audio frame clock that is an output in master mode and an input in slave mode. LRCLKN1 typically is run at the sampling frequency. In slave mode, LRCLKN1 operates asynchronously from ...

Page 54

PACKAGE DIMENSIONS 44L PLCC PACKAGE DRAWING DIM MIN A 0.165 A1 0.090 B 0.013 D 0.685 D1 0.650 D2 0.590 E 0.685 E1 0.650 E2 0.590 e 0.040 INCHES MAX 0.180 0.120 0.021 0.695 ...

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Notes • ...

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