STAC9704T Hynix Semiconductor, STAC9704T Datasheet
STAC9704T
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STAC9704T Summary of contents
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SigmaTel, Inc. Integrating Mixed-Signal Solutions GENERAL DESCRIPTION: SigmaTel’s STAC9704/ general purpose 18-bit, full duplex, audio codec that conforms to the analog component specification of AC’97 (Audio Codec ’97 Component Specification rev. 1.03). The STAC9704/07 incorporates SigmaTel’s proprietary Sigma-Delta ...
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... ORDERING INFORMATION: PART PACKAGE NUMBER STAC9704T 48-pin TQFP 7mm x 7mm x 1.4mm STAC9707T 48-pin TQFP 7mm x 7mm x 1.4mm SigmaTel reserves the right to change specifications without notice. TEMPERATURE SUPPLY RANGE RANGE + DVdd = 3.3V – 5V, AVdd = + DVdd = 3.3V AVdd = 3.3V ...
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SigmaTel, Inc Table of Contents General Description Ordering Information 1. PIN/SIGNAL Descriptions 1.1 Digital I/O 1.2 Analog I/O 1.3 Filter and Voltage References 10 1.4 Power and Ground Signals 11 2. AC-Link 11 2.1 Clocking 12 2.2 Reset 12 3. ...
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SigmaTel, Inc Table of Contents – Tables Table 1 – Package Dimensions Table 2 – Pin Designation Table 3 – Digital Signal List Table 4 – Analog Signal List Table 5 – Filtering and Voltage References Table 6 –Power Signal ...
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SigmaTel, Inc Figure 1 – Package Outline SigmaTel e STAC9704 pin TQFP 14 2 Table 2 - Pin Designation PIN SIGNAL PI SIGNAL # NAME N # NAME DVdd1 PHONE 1 13 ...
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SigmaTel, Inc. Figure 2. STAC9704 Block Diagram 4 stereo sources Power Management PCM out DACs 48Kss DAC Digital AC-link Interface DAC SYNC BIT_CLK Registers PCM in ADCs SDATA_OUT bits ADC SDATA_IN RESET ADC 48Kss The STAC9704/7 block ...
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SigmaTel, Inc. Figure 3 - Connection Diagram – See Appendix A for an alternative connection diagram when using separate supplies. See Appendix B for specific connection requirements prior to operation 0.1uF 0.1uF 10uF 25 38 ...
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SigmaTel, Inc PIN/SIGNAL DESCRIPTIONS 1.1 Digital I/O These signals connect the STAC9704/7 to its AC’97 controller counterpart and an external crystal. Table 3. Digital Signal List SIGNAL NAME TYPE RESET # I XTL_IN I XTL_OUT O SYNC I ...
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SigmaTel, Inc. 1.2 Analog I/O These signals connect the STAC9704/7 to analog sources and sinks, including microphones and speakers. Table 4. Analog Signal List SIGNAL NAME TYPE PC-BEEP I PHONE I From telephony subsystem speakerphone (or DLP - Down Line ...
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SigmaTel, Inc. LNLVL_OUT_L O LNLVL_OUT_R O * Note: any unused input pins should have a capacitor (1 uF suggested) to ground. 1.3 Filter and Voltage References These signals are connected to resistors, capacitors, or specific voltages. Table 5. Filtering and ...
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SigmaTel, Inc. 1.4 Power and Ground Signals Table 6. Power Signal List STAC9704/7 SIGNAL NAME TYPE STAC9704 AVdd1 I Analog Vdd = 5.0V AVdd2 I Analog Vdd = 5.0V AVss1 I Analog Gnd AVss2 I Analog Gnd DVdd1 I Digital ...
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SigmaTel, Inc. 2.1 Clocking STAC9704/7 derives its clock internally from an externally connected 24.576 MHz crystal or an oscillator through the XTAL_IN pin. Synchronization with the AC’97 controller is achieved through the BIT_CLK pin at 12.288 MHz (half of crystal ...
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SigmaTel, Inc. PCM Playback 2 output slots PCM Record data 2 input slots Control 2 output slots Status 2 input slots Synchronization of all AC-link data transactions is signaled by the AC’97 controller. STAC9704/7 drives the serial bit clock onto ...
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SigmaTel, Inc. 3.1.1 AC-link Audio Output Frame (SDATA_OUT) The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the STAC9704/7 DAC inputs, and control registers. Each audio output frame supports ...
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SigmaTel, Inc. Figure 7: Start of an Audio Output Frame STAC9701 samples SYNC assertion here SYNC BIT_CLK valid SDATA_OUT Frame End of previous audio frame SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions stuffed ...
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SigmaTel, Inc. 3.1.1.2 Slot 2: Command Data Port The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle. (as indicated by Slot 1, bit ...
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SigmaTel, Inc. Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the STAC9704 the "Codec Ready" state or not. If the “Codec Ready” bit this indicates ...
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SigmaTel, Inc. Figure 9: Start of an Audio Input Frame STAC9704 samples SYNC assertion here SYNC BIT_CLK Codec SDATA_IN Ready End of previous audio frame SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned ...
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SigmaTel, Inc. 3.1.2.2 Slot 2: Status Data Port The status data port delivers 16-bit control register read data. Bit (19:4) Control Register Read Data Bit (3 :0) RESERVED If Slot 2 is tagged "invalid" by STAC9704/7, then the entire slot ...
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SigmaTel, Inc. Figure 10. STAC9704/7 Powerdown Timing SYNC BIT_CLK slot2 SDATA_OUT per frame slot2 SDATA_IN per frame Note: BIT_CLK not to scale BIT_CLK and SDATA_IN are transitioned low immediately (within the maximum specified time) following the decode of the write ...
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SigmaTel, Inc. Cold Reset - a cold reset is achieved by asserting RESET# for the minimum specified time. By driving RESET# low, BIT_CLK, and SDATA_IN will be activated, or re-activated as the case may be, and all STAC9704/7 control registers ...
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SigmaTel, Inc. 4. STAC9704/7 MIXER The STAC9704/7 mixer is designed to the AC’97 specification to manage the playback and record of all digital and analog audio sources in the PC environment. These include: System Audio: digital PCM input and output ...
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SigmaTel, Inc. Table 8. Mixer functional connections SOURCE FUNCTION PC_Beep PC beep pass thru PHONE speakerphone or DLP in MIC1 desktop microphone MIC2 second microphone LINE_IN external audio source CD audio from CD-ROM VIDEO audio from TV tuner or video ...
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SigmaTel, Inc. 4.1 Mixer Input The mixer provides recording and playback of any audio sources or output mix of all sources. The STAC9704/7 supports the following input sources: any mono or stereo source mono or stereo mix of all sources ...
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SigmaTel, Inc. 4.4 Mixer Registers: Table 9. Mixer Registers REG # NAME D15 D14 D13 D12 D11 D10 00h Reset X SE4 SE3 SE2 SE1 SE0 02h Master Volume Mute X X ML4 ML3 ML2 04h LNLVL Volume Mute X ...
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SigmaTel, Inc. 4.4.1 Reset Register (Index 00h) Writing any value to this register performs a register reset, which causes all registers to revert to their default values. Reading this register returns the ID code of the part. 4.4.2 Play Master ...
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SigmaTel, Inc. Table 11: PC_BEEP Register MUTE PV3…PV0 0 0000 0 1111 1 xxxx 4.4.4 Analog Mixer Input Gain Registers (Index 0Ch - 18h) These registers control the gain/attenuation for each of the analog inputs. Each step corresponds to approximately ...
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SigmaTel, Inc. Table 13: Record Select Control Registers SR2…SR0 RIGHT RECORD SOURCE SL2…SL0 LEFT RECORD SOURCE STAC9704/7 Mic CD In (right) Video In ...
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SigmaTel, Inc. 4.4.6 Record Gain Registers (Index 1Ch) The 1Ch register adjusts stereo input record gain. corresponds to 0F0Fh and 000Fh respectively. The MSB of the register is the mute bit. When this bit is set to 1, the level ...
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SigmaTel, Inc. 4.4.8 3D Control Register (Index 22h) This register is used to control the 3D stereo enhancement function, Sigmatel Surround 3D (SS3D), built into the AC'97 component. Note the register bits, DP1 – DP0, are used to control the ...
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SigmaTel, Inc. Table 17: Powerdown Status Register BIT REF VREF’ nominal level ANL Analog mixers, etc. ready DAC DAC section ready to playback data ADC ADC section ready to playback data 5. LOW POWER MODES The STAC9704/7 is ...
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SigmaTel, Inc. PR6 Figure 12: Example of STAC9704/7 Powerdown/Powerup flow PR0=1 PR1=1 ADCs off DACs off Normal PR0 PR1 PR1=0 PR0=0 & & ADC=1 DAC=1 Default Ready =1 The above figure illustrates one example procedure complete powerdown ...
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SigmaTel, Inc. 6. TESTABILITY The STAC9704/7 has two test modes. One is for ATE in-circuit test and the other is restricted for SigmaTel’s internal use. STAC9704/7 enters the ATE in circuit test mode if SDATA_OUT is sampled high at the ...
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SigmaTel, Inc TIMING CHARACTERISTICS ( AVdd = DVdd = 5.0V or 3.3V 5%, AVss=DVss+0V; 50pF external load) ambient 7.1 Cold Reset Figure 14: Cold Reset RESET# BIT_CLK Table 19 : Cold Reset PARAMETER RESET# active ...
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SigmaTel, Inc. Table 20: Warm Reset PARAMETER SYNC active high pulse width SYNC inactive to BIT_CLK startup delay 7.3 Clocks Figure 16: Clocks Tclk_high BIT_CLK Tclk_period SYNC Tsync_high Table 21: Clocks PARAMETER SYMBOL BIT_CLK frequency BIT_CLK period Tclk_period BIT_CLK output ...
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SigmaTel, Inc. 7.4 Data Setup and Hold (50pF external load) Figure 17: Data Setup and Hold BIT_CLK SDATA_IN SDATA_OUT Thold SYNC Table 22: Data Setup and Hold PARAMETER SYMBOL Setup to falling edge of BIT_CLK Hold from falling edge of ...
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SigmaTel, Inc. 7.5 Signal Rise and Fall Times - (50pF external load; from 10% to 90% of Vdd) Figure 18: Signal Rise and Fall Times BIT_CLK Triseclk SDATA_IN Trisedin Table 23: Signal Rise and Fall Times PARAMETER SYMBOL BIT_CLK rise ...
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SigmaTel, Inc. Table 24: AC-link Low Power Mode Timing PARAMETER End of Slot 2 to BIT_CLK, SDATA_IN low 7.7 ATE Test Mode Figure 20: ATE Test Mode RESET# SDATA_OUT SDATA_IN, BIT_CLK Table 25: ATE Test Mode PARAMETER Setup to trailing ...
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SigmaTel, Inc. 8. ELECTRICAL SPECIFICATIONS: 8.1 Absolute Maximum Ratings: Voltage on any pin relative to Ground Operating Temperature Storage Temperature Soldering Temperature Output Current per Pin 8.2 Recommended Operating Conditions Table 26. Operating Conditions PARAMETER Power Supplies + 3.3V Digital ...
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SigmaTel, Inc. 8.3 Power Consumption Table 27. Power Consumption PARAMETER Digital Supply Current + 5V Digital + 3.3V Digital Analog Supply Current + 5V Analog + 3.3V Analog Power Down Status in Sequence PR0 +5V Analog Supply Current PR1 +5V ...
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SigmaTel, Inc. 8.5 STAC9704 Analog Performance Characteristics DVdd = 3.3V 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz; 0dB = 1 Vrms, 10K ohm/ 50pF load, Testbench Characterization BW – 20kHz, 0dB settings on ...
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SigmaTel, Inc. Vrefout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift DAC Offset Voltage Deviation from Linear Phase External Load Impedance Mute Attenuation (Vrms input) Notes: 1. With +20 dB Boost on, 1.0Vrms with Boost off 2. 1 ...
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SigmaTel, Inc. 8.6 STAC9707 Analog Performance Characteristics DVdd = 3.3V 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz; 0dB = 1 Vrms, 10K ohm/ 50pF load, Testbench Characterization BW – 20kHz, 0dB settings on ...
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SigmaTel, Inc. Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance Input Capacitance Vrefout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift DAC Offset Voltage Deviation from Linear Phase External Load Impedance Mute Attenuation (0 dB) Notes: 1. ...
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SigmaTel, Inc. Appendix A SPLIT INDEPENDENT POWER SUPPLY OPERATION In PC applications, one power supply input to the STAC9704/7 may be derived from a supply regulator (as shown in Figure 3) and the other directly from the PCI power supply ...
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SigmaTel, Inc. Appendix B +5.0V/+3.3V POWER SUPPLY OPERATION NOTES The STAC9704 is capable of operating from a single 5V supply connected to both DVdd and AVdd. Even though the STAC9704 has digital switching levels of 0.2Vdd to 0.5Vdd (See AC ...
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SigmaTel, Inc. - NOTES - 47 STAC9704/7 10/02/98 ...
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SigmaTel, Inc. - NOTE - 48 STAC9704/7 10/02/98 ...
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SigmaTel, Inc. For more information, please contact: SigmaTel, Inc. 6101 W. Courtyard Dr., Bldg. 1, Suite 100 Austin, Texas 78730 Tel (512) 343-6636, Fax (512) 343-6199 email: sales@sigmatel.com Homepage: www.sigmatel.com 49 STAC9704/7 10/02/98 ...