HDMP-1546 Agilent Technologies, Inc., HDMP-1546 Datasheet

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HDMP-1546

Manufacturer Part Number
HDMP-1546
Description
Manufacturer
Agilent Technologies, Inc.
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
HDMP-1546
Manufacturer:
HP
Quantity:
5 510
696
Fibre Channel Transceiver Chip
Technical Data
Features
• ANSI X3.230-1994 Fibre
• Supports Full Speed
• Compatible with “Fibre
• Low Power Consumption,
• Transmitter and Receiver
• Auto Frequency Lock
• Small Package Profile
• 10-Bit Wide Parallel TTL
• Single +3.3 V Power Supply
Applications
• 1062.5 MBd Fibre Channel
• FC Interface for Disk Drives
• Mass Storage System I/O
• Work Station/Server I/O
• High Speed Proprietary
• High Speed Backplane
Channel Compatible (FC-0)
(1062.5 MBd) Fibre Channel
Channel 10-Bit Interface”
Specification
630 mW
Functions Incorporated onto
a Single IC
Compatible I/Os
Interface
and Arrays
Channel
Channel
Interface
Interface
HDMP-1536, 10x10 mm QFP
HDMP-1546, 14x14 mm QFP
Description
The HDMP-1536/46 transceiver
is a single silicon bipolar
integrated circuit packaged in a
plastic QFP package. It provides
a low-cost, low-power physical
layer solution for 1062.5 MBd
Fibre Channel or proprietary link
interfaces. It provides complete
FC-0 functionality for copper
transmission, incorporating both
the Fibre Channel FC-0 transmit
and receive functions into a
single device.
This chip is used to build a high-
speed interface (as shown in
Figure 1) while minimizing board
space, power, and cost. It is
compatible with both the ANSI
X3.230-1994/AM 1 - 1996
document and the “Fibre Channel
10-bit Interface” specification.
The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a high-
speed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or
equivalent. This parallel data is
latched into the input register of
the transmitter section on the
rising edge of the 106.25 MHz
reference clock (used as the
transmit byte clock).
HDMP-1536 Transceiver
HDMP-1546 Transceiver
The transmitter section’s PLL
locks to this user supplied 106.25
MHz byte clock. This clock is
then multiplied by 10, to generate
the 1062.5 MHz serial signal
clock used to generate the high-
speed output. The high-speed
outputs are capable of interfacing
directly to copper cables for
electrical transmission or to a
separate fiber-optic module for
optical transmission.
The receiver section accepts a
serial electrical data stream at
1062.5 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high-speed serial
clock and data. The serial data is
5965-8113E (4/97)

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HDMP-1546 Summary of contents

Page 1

... Transmitter and Receiver Functions Incorporated onto a Single IC • Auto Frequency Lock • Small Package Profile HDMP-1536, 10x10 mm QFP HDMP-1546, 14x14 mm QFP • 10-Bit Wide Parallel TTL Compatible I/Os • Single +3.3 V Power Supply Applications • 1062.5 MBd Fibre Channel Interface • FC Interface for Disk Drives and Arrays • ...

Page 2

... PROTOCOL DEVICE BYTSYNC REFCLK ENBYTSYNC -LCKREF Figure 1. Typical Application Using the HDMP-15x6. DATA BYTE TX[0-9] TX TXCAP0 PLL/CLOCK TXCAP1 GENERATOR REFCLK -LCKREF RXCAP0 RXCAP1 RBC0 RBC1 DATA BYTE RX[0-9] BYTE SYNC BYTSYNC Figure 2. HDMP-15x6 Transceiver Block Diagram. HDMP-15x6 TRANSMITTER SECTION PLL PLL RECEIVER SECTION ...

Page 3

... Fibre Channel specification, which uses an 8B/10B encoding scheme with special reserve characters for link management purposes. In order to accomplish this task, the HDMP-1536/46 incorporates the following: • TTL Parallel I/Os • High Speed Phase Lock Loops • Clock Generation/Recovery Circuitry • ...

Page 4

An optional -LCKREF pin is available for users who want to gain full control during the frequency acquisition process. Asserting this pin will force the Rx PLL to fully phase ...

Page 5

... HDMP-1536/46 (Transmitter Section) Timing Characteristics [ + 3. 3. Symbol Parameter t Setup Time setup t Hold Time hold [2] t_txlat Transmitter Latency Notes: 1. Device tested and characterized under T 2. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the rising edge of the first bit transmitted) ...

Page 6

... HDMP-1536/46 (Receiver Section) Timing Characteristics Symbol [2,3] b_sync Bit Sync Time t Time Data Valid Before Rising Edge of RBC valid_before t Time Data Valid After Rising Edge of RBC valid_after t RBC Duty Cycle duty [4] t Rising Edge Time Difference ...

Page 7

Absolute Maximum Ratings except as specified. Operation in excess of any one of these conditions may result in permanent A damage to this device. Symbol V Supply Voltage CC V TTL Input Voltage IN,TTL V HS_IN ...

Page 8

... Differential HS_OUT Output (Dout+ Minus Dout-). 200.0 ps/div b. Single-Ended HS_OUT Output (Dout+). Eye Diagrams of the High-Speed Serial Outputs from the HDMP-1536/46 as Captured on the HP 83480A Digital Communications Analyzer. Tested with PRBS = 2 Figure 7. Transmitter DOUT Eye Diagrams. Parameter conditions specified, with T ...

Page 9

... OUTPUT) -DOUT VARIABLE DELAY TTL 125 MHz b. Block Diagram of DJ Measurement Method. Parameter HDMP-1536 HDMP-1546 conditions specified, with T monitored at approximately 20 higher than and subtracting the power dissipated outside the chip at the high speed bias resistors 3.45 volts. CC resistors and receiver TTL outputs driving 10 pF loads. ...

Page 10

I/O Type Definitions I/O Type I-TTL Input TTL, Floats High When Left Open O-TTL Output TTL HS_OUT High Speed Output, ECL Compatible HS_IN High Speed Input C External Circuit Node S Power Supply or Ground Pin Input Capacitance Symbol C ...

Page 11

... Rzz.zz = DIE REVISION S = SUPPLIER CODE YYWW = DATE CODE (YY = YEAR WORK WEEK) COUNTRY = COUNTRY OF MANUFACTURE (MARKED ON BACK OF DEVICE) Figure 11. HDMP-1536/46 (TRx) Package Layout and Marking, Top View. *Note: Pin 26 is designated as a “no connect” pin and should be left unconnected. 706 48 RXCAP0 ...

Page 12

TRx I/O Definition Name Pin Type BYTSYNC 47 O-TTL Byte Sync Output: An active high output. Used to indicate detection of either a comma character or a K28.5 special character (0011111XXX only active when ENBYTSYNC is enabled. -DIN ...

Page 13

TRx I/O Definition (cont’d.) Name Pin Type RX[0] 45 O-TTL RX[1] 44 RX[2] 43 RX[3] 41 RX[4] 40 RX[5] 39 RX[6] 38 RX[7] 36 RX[8] 35 RX[9] 34 RXCAP0 48 C RXCAP1 49 TX[0] 2 I-TTL TX[1] 3 TX[2] 4 ...

Page 14

... The PLL capacitors are placed physically close to the appropriate pins on the HDMP- 1536/46. Keeping the lines short will prevent them from picking up stray noise from surrounding lines or components. ...

Page 15

... Part Number A1 A2 HDMP-1536 10.00 13.20 HDMP-1546 14.00 17.20 Tolerance 0.10 0.25 Figure 13. Mechanical Dimensions of HDMP-1536/46. 710 Details Plastic 85% Tin, 15% Lead 300-800 m HDMP-1536 HDMP-1546 0.10 mm max ...

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