SAK-C167SR-LM Siemens Semiconductor Group, SAK-C167SR-LM Datasheet
SAK-C167SR-LM
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SAK-C167SR-LM Summary of contents
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Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller C167SR Data Sheet 06.95 Advance Information ...
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Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other rights of third par- ties are concerned, liability is only assumed for components, ...
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C167SR Revision History: Previous Releases: Page Subjects (changes compared to C167) 31 Register PICON added HYS, ILS IHS RST RWH RWL changed. P6L ...
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... Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 144-Pin MQFP Package (EIAJ) This document describes the SAB-C167SR-LM, the SAF-C167SR-LM and the SAK-C167SR-LM. For simplicity all versions are referred to by the term C167SR throughout this document. Semiconductor Group 16 bit Division ( bit) ...
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C167SR Revision History: Previous Releases: Page Subjects (changes compared to C167) 31 Register PICON added HYS, ILS IHS RST RWH RWL changed. P6L ...
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... IO-capabilities. It also provides on-chip high-speed RAM and clock generation via PLL. Figure 1 Logic Symbol Ordering Information Type Ordering Code SAB-C167SR-LM Q67121-C952 SAF-C167SR-LM Q67121-C953 SAK-C167SR-LM C Semiconductor Group C167SR Package Function P-MQFP-144-1 16-bit microcontroller with 2 2 KByte RAM Temperature range ˚C ...
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Pin Configuration (top view) Figure 2 Semiconductor Group C167SR 4 C167SR ...
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Pin Definitions and Functions Symbol Pin Input (I) Number Output (O) P6 I/O P6 ... ... P8 I/O P8 I/O ... ...
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Pin Definitions and Functions Symbol Pin Input (I) Number Output (O) P5 P5. P2 I/O ...
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Pin Definitions and Functions Symbol Pin Input (I) Number Output (O) P3 70, I/O P3.13 80, I/O P3. ...
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Pin Definitions and Functions Symbol Pin Input (I) Number Output (O) WR WRL READY 97 I ALE PORT0: I/O P0L.0 - 100 - P0L.7, 107 P0H.0 - 108, P0H.7 111-117 Semiconductor Group (cont’d) ...
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Pin Definitions and Functions Symbol Pin Input (I) Number Output (O) PORT1: I/O P1L.0 - 118 - P1L.7, 125 P1H.0 - 128 - P1H.7 135 132 I 133 I 134 I 135 I XTAL1 138 I XTAL2 137 O RSTIN ...
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Pin Definitions and Functions Symbol Pin Input (I) Number Output (O) V 17, 46, – CC 56, 72, 82, 93, 109, 126, 136, 144 V 18, 45, – SS 55, 71, 83, 94, 110, 127, 139, 143 Semiconductor Group (cont’d) ...
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Functional Description The architecture of the C167SR combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the ...
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Memory Organization The memory space of the C167SR is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire ...
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Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask ...
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The CPU disposes of an actual register context consisting wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be ...
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Interrupt System With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the C167SR is capable of reacting very fast to the occurence of non- deterministic events. The architecture ...
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Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 ...
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Source of Interrupt or PEC Service Request CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete ADCIR A/D Overrun ...
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The C167SR also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...
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Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences channels with a maximum resolution of 400 ns (at 20-MHz system clock). The CAPCOM units are typically used to handle high speed I/O ...
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CAPCOM2 Figure 5 CAPCOM Unit Block Diagram Semiconductor Group *) 20 C167SR ...
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PWM Module The Pulse Width Modulation Module can generate up to four PWM output signals using edge- aligned or center-aligned PWM. In addition the PWM module can generate PWM burst signals and single shot outputs. The frequency range of the ...
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The state of this latch may be used to clock timer T5 may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and ...
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Figure 7 Block Diagram of GPT2 Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a ...
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A/D Converter For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and ...
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In asynchronous mode 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit ...
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Instruction Set Summary The table below lists the instructions of the C167SR in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and ...
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Instruction Set Summary (cont’d) Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Semiconductor ...
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Special Function Registers Overview The following table lists all SFRs which are implemented in the C167SR in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the ...
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Special Function Registers Overview Name Physical 8-Bit Address Address CC3 FE86 43 H CC3IC b FF7E BF H CC4 FE88 44 H CC4IC b FF80 C0 H CC5 FE8A 45 H CC5IC b FF82 C1 H CC6 FE8C 46 H ...
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Special Function Registers Overview Name Physical 8-Bit Address Address CC17IC b F162 CC18 FE64 32 H CC18IC b F164 CC19 FE66 33 H CC19IC b F166 CC20 FE68 34 H CC20IC ...
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Special Function Registers Overview Name Physical 8-Bit Address Address CCM0 b FF52 A9 H CCM1 b FF54 AA H CCM2 b FF56 AB H CCM3 b FF58 AC H CCM4 b FF22 91 H CCM5 b FF24 92 H CCM6 ...
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Special Function Registers Overview Name Physical 8-Bit Address Address ODP2 b F1C2 ODP3 b F1C6 ODP6 b F1CE ODP7 b F1D2 ODP8 b F1D6 ONES ...
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Special Function Registers Overview Name Physical 8-Bit Address Address PP3 F03E PSW b FF10 88 H PT0 F030 PT1 F032 PT2 F034 PT3 F036 PW0 ...
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Special Function Registers Overview Name Physical 8-Bit Address Address SSCEIC b FF76 BB H SSCRB F0B2 SSCRIC b FF74 BA H SSCTB F0B0 SSCTIC b FF72 B9 H STKOV FE14 0A H STKUN FE16 ...
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Special Function Registers Overview Name Physical 8-Bit Address Address T6IC b FF68 F050 T78CON b FF20 90 H T7IC b F17A T7REL F054 F052 ...
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... Absolute Maximum Ratings Ambient temperature under bias ( SAB-C167SR-LM............................................................................................................ ˚C SAF-C167SR-LM ....................................................................................................... – ˚C SAK-C167SR-LM..................................................................................................... – 125 ˚C Storage temperature ( T )........................................................................................ – 150 ˚ Voltage on pins with respect to ground ( CC Voltage on any pin with respect to ground ( Input current on any pin during overload condition .................................................. – Absolute sum of all input currents during overload condition ...
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... ˚C for SAB-C167SR- – ˚C for SAF-C167SR- – 125 ˚C for SAK-C167SR-LM A Parameter Input low voltage (TTL) Input low voltage (Special Threshold) Input high voltage, all except RSTIN and XTAL1 (TTL) Input high voltage RSTIN ...
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Parameter 4) Port 6 active current PORT0 configuration current XTAL1 input current 5) Pin capacitance (digital inputs/outputs) Power supply current Idle mode supply current Power-down mode supply current Notes 1) This specification is not valid for outputs which are switched ...
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Figure 8 Supply/Idle Current as a Function of Operating Frequency Semiconductor Group 39 C167SR ...
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... ˚C for SAB-C167SR- – ˚C for SAF-C167SR- – 125 ˚C for SAK-C167SR- 0.1 V; AREF CC Parameter Analog input voltage range Sample time Conversion time Total unadjusted error Internal resistance of reference voltage source ...
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Notes 1) V may exceed AIN AGND AREF cases will be X000 or X3FF H 2) During the sample time the input capacitance internal resistance of the analog source must allow the capacitance to reach its final ...
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Testing Waveforms AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’. Timing measurements are made at Figure 9 Input Output Waveforms For timing purposes a port pin is no ...
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AC Characteristics Definition of Internal Timing The internal operation of the C167SR is controlled by the internal CPU clock CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) ...
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Phase Locked Loop When pin P0.15 (P0H.7) is high (‘1’) during reset the on-chip phase locked loop is enabled and provides the CPU clock. The PLL multiplies the input frequency by 4 (i.e. f fourth transition of the PLL circuit ...
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... ˚C for SAB-C167SR- – ˚C for SAF-C167SR- – 125 ˚C for SAK-C167SR-LM A Parameter Oscillator period High time Low time Rise time Fall time 1) T For temperatures above 2) The clock input signal must reach the defined levels ...
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... ˚C for SAB-C167SR- – ˚C for SAF-C167SR- – 125 ˚C for SAK-C167SR- (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 (for Port 6, CS) = 100 ALE cycle time = 6 TCL + 2 Parameter ...
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Parameter Symbol RD to valid data in t (with RW-delay valid data in (no RW-delay) t ALE low to valid data in Address to valid data Data hold after RD rising edge t Data ...
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Parameter Symbol RdCS to Valid Data In t (no RW delay) t RdCS, WrCS Low Time (with RW delay) t RdCS, WrCS Low Time (no RW delay) Data valid to WrCS t t Data hold after RdCS Data float after ...
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ALE CSx A23-A16 (A15-A8) BHE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 14-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group ...
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ALE t 38 CSx A23-A16 (A15-A8) BHE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 14-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group ...
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ALE CSx A23-A16 (A15-A8) BHE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 14-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group ...
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ALE t 38 CSx A23-A16 (A15-A8) BHE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 14-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group ...
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... ˚C for SAB-C167SR- – ˚C for SAF-C167SR- – 125 ˚C for SAK-C167SR- (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 (for Port 6, CS) = 100 ALE cycle time = 4 TCL + 2 Parameter ...
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Parameter Symbol ALE rising edge after RD Address hold after RD ALE falling edge low to Valid Data hold after RD, WR ALE falling edge to t RdCS, ...
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ALE CSx A23-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 15-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group t ...
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ALE t 38 CSx A23-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 15-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor ...
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ALE CSx A23-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 15-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group t ...
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ALE t 38 CSx A23-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 15-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor ...
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... ˚C for SAB-C167SR- – ˚C for SAF-C167SR- – 125 ˚C for SAK-C167SR- (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 (for Port 6, CS) = 100 pF L Parameter CLKOUT cycle time CLKOUT high time ...
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Running cycle t 32 CLKOUT ALE Command RD, WR Sync READY Async 3) READY Figure 16 CLKOUT and READY Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). ...
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... ˚C for SAB-C167SR- – ˚C for SAF-C167SR- – 125 ˚C for SAK-C167SR- (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 (for Port 6, CS) = 100 pF L Parameter HOLD input setup time to CLKOUT ...
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CLKOUT t 61 HOLD HLDA 1) BREQ CSx (On P6.x) Other Signals Figure 17 s External Bu Arbitration, Releasing the Bus Notes 1) The C167SR will complete the currently running bus cycle before granting bus access. 2) This is the ...
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CLKOUT HOLD HLDA t 62 BREQ CSx (On P6.x) Other Signals Figure 18 External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the ...