GE28F320W18BD60 Intel Corporation, GE28F320W18BD60 Datasheet
GE28F320W18BD60
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GE28F320W18BD60 Summary of contents
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Intel Wireless Flash Memory (W18) 28F320W18, 28F640W18, 28F128W18 Product Features High Performance Read-While-Write/ Erase — Burst frequency at 66 MHz — Initial Access Read Speed — Burst-Mode Read Speed — Page-Mode Read Speed ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © 2003, Intel Corporation. *Other names and brands may be claimed as the property of others. 2 ...
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Contents 1.0 Introduction ...............................................................................................................................9 1.1 Document Purpose ...............................................................................................................9 1.2 Nomenclature .......................................................................................................................9 1.3 Conventions..........................................................................................................................9 2.0 Device Description ................................................................................................................10 2.1 Product Overview ...............................................................................................................10 2.2 Package Diagram ...............................................................................................................12 2.3 Signal Descriptions .............................................................................................................14 2.4 Memory Map and Partitioning .............................................................................................15 3.0 Device Operations .................................................................................................................18 3.1 ...
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Contents 7.1.3 Lock-Down............................................................................................................. 40 7.1.4 Block Lock Status .................................................................................................. 41 7.1.5 Lock During Erase Suspend .................................................................................. 41 7.1.6 Status Register Error Checking ............................................................................. 41 7.1.7 WP# Lock-Down Control ....................................................................................... 42 7.2 Protection Register ............................................................................................................. 42 7.2.1 Reading the Protection Register............................................................................ ...
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Appendix C Mechanical Specifications Appendix D Ordering Information Datasheet .................................................................................95 .........................................................................................100 Contents 5 ...
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Contents Revision History Date of Revision 09/13/00 01/29/01 06/12/01 6 Version -001 Initial Release Deleted 16-Mbit density Revised ADV#, Section 2.2 Revised Protection Registers, Section 4.16 Revised Program Protection Register, Section 4.18 Revised Example in First Access Latency Count, Section ...
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Date of Revision 04/05/02 10/10/02 11/12/02 01/14/03 03/21/03 12/17/03 Datasheet Version New Sections Organization Added 16 Word Burst Feature Added Burst Suspend Section Revised Block Locking State Diagram Revised Active Power Section Revised Automatic Power Savings Section Revised Power-Up/Down Operation ...
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Contents 8 Datasheet ...
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Introduction 1.1 Document Purpose This datasheet contains information about the 1.8 Volt Intel family. Section 1.0 provides a flash memory overview. memory functionality. product offerings. Packaging specifications and order information can be found in Appendix D, respectively. 1.2 Nomenclature ...
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Intel Wireless Flash Memory (W18) • Signal names are in all CAPS (see • Voltage applied to the signal is subscripted, for example, V Throughout this document, references are made to top, bottom, parameter, and partition. To clarify these ...
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Although each partition has burst-read, write, and erase capabilities, simultaneous operation is limited to write or erase ...
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Intel Wireless Flash Memory (W18) 2.2 Package Diagram The W18 device is available in a 56-ball VF BGA and µBGA Chip SCale Package with 0.75 mm ball pitch, or the 88-ball (80 active balls) QUAD+ SCSP package. ballout for ...
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Figure 2. 88-Ball (80 Active Balls) QUAD+ Ballout S-CS1# K F1-CE Legend: Global NOTES: 1. Unused upper address balls can be treated as NC (for 128Mbit, A[25:23] are not ...
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Intel Wireless Flash Memory (W18) 2.3 Signal Descriptions Table 1 describes ball usage. Table 1. Signal Descriptions Symbol Type A[22:0] I ADDRESS INPUTS: For memory addresses. 32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit: A[22:0] DATA INPUTS/OUTPUTS: Inputs data ...
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Table 1. Signal Descriptions Symbol Type OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal may be tied VSSQ Pwr directly to VSS. DON’T USE: Do not use this pin. This pin should not be ...
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Intel Wireless Flash Memory (W18) Table 2. Bottom Parameter Memory Map Size Blk # (KW 1F8000-1FFFFF 32 39 100000-107FFF 32 38 0F8000-0FFFFF 32 31 0C0000-0C7FFF 32 30 0B8000-0BFFFF 32 23 080000-087FFF 32 22 ...
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Table 3. Top Parameter Memory Map Size Blk # 32 Mbit (KW 1FF000-1FFFFF 4 63 1F8000-1F8FFF 32 62 1F0000-1F7FFF 32 56 1C0000-1C7FFF 32 55 1B8000-1BFFFF 32 48 18000-187FFF 32 47 178000-17FFFF 32 40 140000-147FFF 32 39 138000-13FFFF 32 ...
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Intel Wireless Flash Memory (W18) 3.0 Device Operations This section provides an overview of device operations. The 1.8 Volt Intel family includes an on-chip WSM to manage block erase and program algorithms. Its CUI allows minimal processor overhead with ...
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Access to the modes listed above is independent of V device in a read mode. At initial power-up or after reset, the device defaults to asynchronous read- array mode. Asserting CE# enables device read operations. The device internally decodes upper ...
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Intel Wireless Flash Memory (W18) If RST# is asserted during an erase or program operation, the operation aborts and the memory contents at the aborted block or address are invalid. See on page 80 for detailed information regarding reset ...
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Table 5. Command Codes and Descriptions (Sheet Device Operation Code Command FFh Read Array Read Status 70h Register 90h Read Identifier Read 98h Read Query Clear Status 50h Register Word Program 40h Setup 10h Alternate Setup Program ...
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Intel Wireless Flash Memory (W18) Table 5. Command Codes and Descriptions (Sheet Device Operation Code Command Protection Protection C0h Program Setup Configuration 60h Setup Configuration Set 03h Configuration Register NOTE: Do not use unassigned commands. Intel ...
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Table 6. Bus Cycle Definitions Operation Command Read Array/Reset Read Identifier Read Read Query Read Status Register Clear Status Register Block Erase Word Program Program and EFP Erase Program/Erase Suspend Program/Erase Resume Lock Block Lock Unlock Block Lock-Down Block Protection ...
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Intel Wireless Flash Memory (W18) 3.3 Command Sequencing When issuing a 2-cycle write sequence to the flash device, a read operation is allowed to occur between the two write cycles. The setup phase of a 2-cycle write sequence places ...
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Read Operations 4.1 Read Array The Read Array command places (or resets) the partition in read-array mode and is used to read data from the flash memory array. Upon initial device power-up, or after reset (RST# transitions from V ...
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Intel Wireless Flash Memory (W18) Table 7. Device Identification Codes (Sheet Item Protection Register Lock Status Protection Register NOTES: 1. The address is constructed from a base address plus an offset. For example, to read the ...
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Table 8. Status Register Definitions DWS ESS Table 9. Status Register Descriptions Bit Name DWS 0 = Device WSM is Busy 7 Device WSM Status 1 = Device WSM is Ready ESS 0 = Erase in ...
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Intel Wireless Flash Memory (W18) 4.5 Clear Status Register The Clear Status Register command clears the status register and leaves all partition output states unchanged. The WSM can set all status register bits and clear bits SR[7:6,2,0]. Because bits ...
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Figure 6. Word Program Flowchart Start Write 40h, Word Address Write Data Word Address Read Status Register 0 SR[ Full Program Status Check (if desired) Program Complete Read Status Register 1 SR[ SR[ ...
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Intel Wireless Flash Memory (W18) The 12-V V mode enhances programming performance during the short time period typically PP found in manufacturing processes; however not intended for extended use.12 V may be applied to V during program ...
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Setup After receiving the EFP Setup (30h) and EFP Confirm (D0h) command sequence, SR[7] transitions from indicating that the WSM is busy with EFP algorithm startup. A delay before checking SR[7] is required to ...
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Intel Wireless Flash Memory (W18) The verification phase concludes when the interfacing programmer writes to a different block address; data supplied must be FFFFh. Upon completion of the verify phase, the device enters the EFP exit phase. 5.3.5 Exit ...
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Figure 7. Enhanced Factory Program Flowchart EFP Setup Start V = 12V PP Unlock Block Write 30h Address = WA 0 Write D0h Address = WA 0 EFP setup time Read Status Register EFP Setup Done? SR[7]=1=N Check V & ...
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Intel Wireless Flash Memory (W18) 6.0 Program and Erase Operations 6.1 Program/Erase Suspend and Resume The Program Suspend and Erase Suspend commands halt an in-progress program or erase operation. The command can be issued at any device address. The ...
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Figure 8. Program Suspend / Resume Flowchart Start Program Suspend Write B0h Any Address Read Status Write 70h Same Partition Read Status Register Read Array Write FFh Susp Partition Read Array Data ...
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Intel Wireless Flash Memory (W18) Figure 9. Erase Suspend / Resume Flowchart Start Erase Write B0h Any Address Read Write 70h Same Partition Read Status Register SR SR Read Read or Program? Read Array No ...
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After writing the Erase Confirm command, the selected partition is placed in read status register mode and reads performed to that partition return the current status data. The address given during the Erase Confirm command does not need to be ...
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Intel Wireless Flash Memory (W18) Figure 10. Block Erase Flowchart Start Write 20h Block Address Write D0h and Block Address Read Status Register 0 SR[ Full Erase Status Check (if desired) Block Erase Complete Read Status Register ...
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The product does not support simultaneous program and erase operations. Attempting to perform operations such as these results in a command sequence error. Only one partition can be programming or erasing while another partition is reading. However, one partition may ...
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Intel Wireless Flash Memory (W18) Figure 11. Block Locking State Diagram Power-Up/Reset Notes: 1. [a,b,c] represents [WP#, D1, D0 Don’t Care indicates block Lock-down status ‘0’, Lock-down has not been issued to 3. ...
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Down command should be issued prior asserting WP# will put that block back to the locked-down state. When WP# is deasserted, locked-down blocks are changed to the locked state and can then be unlocked by the Unlock Block command. 7.1.4 ...
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Intel Wireless Flash Memory (W18) complete, possible errors during the erase cannot be detected from the status register because of the previous locking command error. A similar situation occurs if a program operation error is nested within an erase ...
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Note: The individual bits of the user segment of the protection register are OTP, not the register in total. The user may program each OTP bit individually, one at a time, if desired. After the protection register is locked, however, ...
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Intel Wireless Flash Memory (W18) 7.2.3 Locking the Protection Register PR-LK.0 is programmed Intel to protect the unique device number. PR-LK.1 can be programmed by the user to lock the user portion (upper 64 bits) of ...
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Figure 14. Protection Register Locking 7.3 VPP Protection ® The 1.8 Volt Intel factory programming, it also includes a low-cost, backward-compatible 12 V programming feature.(See “Factory Programming” on page improve factory program performance as explained in (EFP)” on page 30. ...
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Intel Wireless Flash Memory (W18) 8.0 Set Configuration Register The Set Configuration Register command sets the burst order, frequency configuration, burst length, and other parameters. A two-bus cycle command sequence initiates this operation. The configuration register data is placed ...
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Table 13. Configuration Register Definitions Read First Access Latency Res’d Mode Count RM R LC2 LC1 LC0 Table 14. Configuration Register Descriptions Bit Name RM 15 Read Mode 14 R LC2-0 13-11 First Access Latency ...
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Intel Wireless Flash Memory (W18) 8.1 Read Mode (CR[15]) All partitions support two high-performance read configurations: synchronous burst mode and asynchronous page mode (default). CR[15] sets the read configuration to one of these modes. Status register, query, and identifier ...
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Latency Count Settings Table 15. Latency Count Settings for AVQV CHQV Latency Count 2 Settings Frequency < 39 Table 16. Latency Count Setting for AVQV CHQV Latency Count 2 Settings Frequency < 40 ...
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Intel Wireless Flash Memory (W18) Figure 18. Example: Latency Count Setting at 3 CLK (C) CE# (E) ADV# (V) A (A) MAX-0 DQ (D/Q) 15-0 8.3 WAIT Signal Polarity (CR[10]) If the WT bit is cleared (CR[10]=0), then WAIT ...
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Table 18. WAIT Signal Conditions CONDITION CE CE OE# Synchronous Array Read Synchronous Non-Array Read All Asynchronous Read and all Write 8.5 Data Hold (CR[9]) The Data Output Configuration bit (CR[9]) determines whether a ...
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Intel Wireless Flash Memory (W18) Figure 19. Data Output Configuration with WAIT Signal Delay CLK [C] WAIT (CR WAIT (CR CLK DQ 15-0 Data Hold WAIT (CR WAIT (CR ...
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Table 19. Sequence and Burst Length 4-Word Start Burst Addr. CR[2:0]=0 (Dec) 01b Linear 0 0-1-2-3 1 1-2-3-0 2 2-3-0-1 3 3-0-1 0-1-2-3 1 1-2-3-4 2 2-3-4-5 3 3-4-5 ...
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Intel Wireless Flash Memory (W18) 8.8 Clock Edge (CR[6]) Configuring the valid clock edge enables a flexible memory interface to a wide range of burst CPUs. Clock configuration sets the device to start a burst cycle, output data, and ...
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Power Consumption ® 1.8 Volt Intel Wireless Flash memory devices have a layered approach to power savings that can significantly reduce overall system power consumption. The APS feature reduces power consumption when the device is selected but idle. If ...
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Intel Wireless Flash Memory (W18) 9.4.1 System Reset and RST# The use of RST# during system reset is important with automated program/erase devices because the system expects to read from the flash memory when it comes out of reset. ...
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Thermal and DC Characteristics 10.1 Absolute Maximum Ratings Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. Warning: These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended, and extended exposure beyond the ...
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Intel Wireless Flash Memory (W18) Table 21. Extended Temperature Operation (Sheet Symbol Main and Parameter Blocks Block Erase Main Blocks Cycles Parameter Blocks NOTES: 1. See Section 10.3 specifications. 2. VPP is normally V extended temperatures ...
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Table 22. DC Current Characteristics (Sheet (1) Sym Parameter Asynchronous Page Mode f=13 MHz Synchronous CLK = 40 MHz Average I V CCR CC Read Synchronous CLK = 54 MHz Average Synchronous I V CCR CC CLK ...
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Intel Wireless Flash Memory (W18) Table 22. DC Current Characteristics (Sheet (1) Sym Parameter I PPS V Standby PP (I PPWS V Program Suspend Erase Suspend PPES I V Read ...
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Table 23. DC Voltage Characteristics (Sheet CCQ (1) Sym Parameter Note V Output High OH V – 0 Lock-Out 7 PPLK Lock LKO Lock TBD ILKOQ CCQ NOTE: ...
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Intel Wireless Flash Memory (W18) 11.0 AC Characteristics 11.1 Read Operations – .13 m Lithography Table 24. Read Operations— .13 m Lithography (Sheet Sym Parameter Asynchronous Specifications R1 t Read Cycle Time AVAV R2 t ...
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Table 24. Read Operations— .13 m Lithography (Sheet Sym Parameter Synchronous Specifications R301 t Address Valid Setup to CLK AVCH R302 t ADV# Low Setup to CLK VLCH R303 t CE# Low Setup to CLK ELCH ...
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Intel Wireless Flash Memory (W18) 11.2 Read Operations – .18 m Lithography Table 25. Read Operations — .18 m Lithography (Sheet Sym Parameter Asynchronous Specifications R1 t Read Cycle Time AVAV R2 t Address to ...
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Table 25. Read Operations — .18 m Lithography (Sheet Sym Parameter Synchronous Specifications R301 t Address Valid Setup to CLK AVCH R302 t ADV# Low Setup to CLK VLCH R303 t CE# Low Setup to CLK ...
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Intel Wireless Flash Memory (W18) Figure 20. Asynchronous Read Operation Waveform V IH Address [ CE# [ OE# [ WE# [ High Z ...
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Figure 21. Latched Asynchronous Read Operation Waveform V IH A[MAX:2] [ A[1:0] [ R105 V IH ADV# [ CE# [ OE# [ ...
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Intel Wireless Flash Memory (W18) Figure 22. Page-Mode Read Operation Waveform V IH A[MAX:2] [ A[1:0] [ R105 V IH ADV# [ CE# [ OE# ...
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Figure 23. Single Synchronous Read-Array Operation Waveform V IH CLK [ Address [ R105 V IH ADV# [ CE# [ OE# [ ...
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Intel Wireless Flash Memory (W18) Figure 24. Synchronous 4-Word Burst Read Operation Waveform V IH CLK [ Address [ R105 V IH ADV# [ CE# [ ...
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Figure 25. WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform V IH CLK [ Address [ R105 V IH ADV# [ CE# [ OE# [G] ...
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Intel Wireless Flash Memory (W18) Figure 26. WAIT Signal in Synchronous Non-Read Array Operation Waveform V IH CLK [ Address [ R105 V IH ADV# [ CE# [E] V ...
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Figure 27. Burst Suspend CLK Address [A] R101 R105 R105 ADV# CE# [E] OE# [G] R12 WAIT [T] WE# [W] DATA [D/Q] NOTE: 1. During Burst Suspend Clock signal can be held high or low Datasheet Intel R304 R305 R1 ...
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Intel Wireless Flash Memory (W18) 11.3 AC Write Characteristics Table 26. AC Write Characteristics # Sym Parameter RST# High Recovery to WE PHWL PHEL (CE#) Low CE# (WE#) Setup to WE# (CE ...
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Table 27. AC Write Characteristics # Sym RST# High Recovery to WE# (CE#) Low PHWL PHEL CE# (WE#) Setup to WE# (CE#) Low ELWL WLEL WE# (CE#) ...
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Intel Wireless Flash Memory (W18) Figure 28. Write Operations Waveform V IH CLK [ Note Address [ R105 V IH ADV# [ CE# (WE#) [E(W ...
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Figure 29. Asynchronous Read to Write Operation Waveform Address [A] CE# [E} OE# [G] WE# [W] Data [D/Q] RST# [P] Figure 30. Asynchronous Write to Read Operation Address [A] CE# [E} WE# [W] OE# [G] Data [D/Q] RST # [P] ...
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Intel Wireless Flash Memory (W18) Figure 31. Synchronous Read to Write Operation R301 CLK [C] R101 Address [A] R105 R105 R102 ADV# [V] CE# [E] OE# [G] WE# WAIT [T] Data [D/Q] Figure 32. Synchronous Write To Read Operation ...
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Erase and Program Times Table 28. Erase and Program Times Operation Symbol Parameter Erasing and Suspending W500 tERS/PB Erase Time W501 t ERS/MB W600 t Suspend SUSP/P Latency W601 t SUSP/E Programming W200 tPROG/W Program W201 tPROG/PB Time W202 ...
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Intel Wireless Flash Memory (W18) 11.5 Reset Specifications Table 29. Reset Specifications # Symbol P1 t RST# Low to Reset during Read PLPH RST# Low to Reset during Block Erase P2 t PLRH RST# Low to Reset during Program ...
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AC I/O Test Conditions Figure 34. AC Input/Output Reference Waveform V CCQ Input 0V NOTE: Input timing begins, and output timing ends Worst case speed conditions are when V Figure 35. Transient Equivalent Testing Load Circuit NOTE: ...
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Intel Wireless Flash Memory (W18) 11.7 Device Capacitance T = +25 ° MHz A Symbol Output Capacitance OUT C CE# Input Capacitance CE § Sampled, not 100% tested. 82 § Parameter Typ Input ...
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Appendix A Write State Machine States This table shows the command state transitions based on incoming commands. Only one partition can be actively programming or erasing at a time. Figure 37. Write State Machine — Next State Table (Sheet 1 ...
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Intel Wireless Flash Memory (W18) Figure 37. Write State Machine — Next State Table (Sheet Lock, Unlock, Current Chip Lock-down, (8) State CR setup (60H) Lock/CR Ready Setup Lock/CR Setup Ready (Lock Error) Setup OTP Busy ...
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Illegal commands are those not defined in the command set. 3. All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition results in undermined data when a partition address is read. ...
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Appendix B Common Flash Interface This appendix defines the data structure or “database” returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical ...
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B.2 Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or “database.” The structure sub-sections and address locations are summarized below. Table 33. Query Structure Offset 00000h 00001h (2) Block ...
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Intel Wireless Flash Memory (W18) Table 35. CFI Identification Offset Length 10h 3 2 13h 2 15h 2 17h 19h 2 Table 36. System Interface Information Offset Length 1Bh 1 1Ch 1 1Dh 1 1Eh 1 1Fh 1 20h ...
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B.5 Device Geometry Definition Table 37. Device Geometry Definition Offset Length 27h 1 28h 2 2Ah 2 2Ch 1 2Dh 4 31h 4 35h 4 Address –B 27: --16 28: --01 29: --00 2A: --00 2B: --00 2C: --02 2D: ...
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Intel Wireless Flash Memory (W18) B.6 Intel-Specific Extended Query Table Table 38. Primary Vendor-Specific Extended Query (1) Length Offset P = 39h (P+0)h 3 (P+1)h (P+2)h (P+3)h 1 (P+4)h 1 (P+5)h 4 (P+6)h (P+7)h (P+8)h (P+9)h 1 (P+A)h 2 ...
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Table 39. Protection Register Information (1) Length Offset P = 39h (P+E)h 1 (P+F)h 4 (P+10)h (P+11)h (P+12)h Table 40. Burst Read Information for Non-muxed Device (1) Length Offset P = 39h (P+13)h 1 (P+14)h 1 (P+15)h 1 (P+16)h 1 ...
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Intel Wireless Flash Memory (W18) Partition Region 1 Information (1) Offset P = 39h Bottom Top (P+1A)h (P+1A)h Number of identical partitions within the partition region (P+1B)h (P+1B)h (P+1C)h (P+1C)h (P+1D)h (P+1D)h (P+1E)h (P+1E)h (P+1F)h (P+1F)h (P+20)h (P+20)h Partition ...
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Partition Region 2 Information (1) Offset P = 39h Bottom Top (P+30)h (P+28)h Number of identical partitions within the partition region (P+31)h (P+29)h (P+32)h (P+2A)h (P+33)h (P+2B)h (P+34)h (P+2C)h (P+35)h (P+2D)h (P+36)h (P+2E)h Partition Region 2 Erase Block Type 1 ...
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Intel Wireless Flash Memory (W18) Partition and Erase-block Region Information Address 52: 53: 54: 55: 56: 57: 58: 59: 5A: 5B: 5C: 5D: 5E: 5F: 60: 61: 62: 63: 64: 65: 66: 67: 68: 69: 6A: 6B: 6C: 6D: ...
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Appendix C Mechanical Specifications C.1 W18 – .18 m Lithography 64-Mb BGA*CSP Package Drawing and Dimensions Figure 38 ...
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Intel Wireless Flash Memory (W18) Figure 39. 32-Mb VFBGA Package Drawing Ball A1 Corner View - Bump Side Down A2 Figure 40. 128-Mb VFBGA Package Drawing Ball ...
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Table 42. 32-Mbit and 128-Mbit VFBGA Package Dimensions Dimension Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width 32Mb Package Body Length32Mb Package Body Width 128Mb Package Body Length 128Mb Pitch Ball (Lead) Count 32Mb Ball ...
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Intel Wireless Flash Memory (W18) C.2 W18 – .13 m Lithography 32-, 64- and 128-Mb VF BGA*CSP Package Drawing Figure 41. B all A 1 Corner Top V iew ...
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Figure 42. 128Mbit QUAD+ Package Drawing A1 Index Mark Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball ...
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Intel Wireless Flash Memory (W18) Appendix D Ordering Information Figure 43. VF BGA and µBGA Ordering Information Package 0. BGA ...