MC68HC908AZ60ACFU Freescale Semiconductor, Inc, MC68HC908AZ60ACFU Datasheet

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MC68HC908AZ60ACFU

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MC68HC908AZ60ACFU
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Freescale Semiconductor, Inc
Datasheet

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MC68HC908AZ60A
MC68HC908AS60A
MC68HC908AZ60E
Data Sheet
M68HC08
Microcontrollers
MC68HC908AZ60A
Rev. 6
05/2006
freescale.com

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MC68HC908AZ60ACFU Summary of contents

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MC68HC908AZ60A MC68HC908AS60A MC68HC908AZ60E Data Sheet M68HC08 Microcontrollers MC68HC908AZ60A Rev. 6 05/2006 freescale.com ...

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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2006. All rights reserved. ...

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MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

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List of Chapters Chapter 1 General Description ...

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List of Chapters Chapter 24 Keyboard Module (KBI ...

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Table of Contents 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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EEPROM-1 Nonvolatile Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 22.7 Port ...

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MSCAN08 Transmitter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents MC68HC908AS60 and MC68HC908AZ60 A.1 Changes from the MC68HC908AS60 and MC68HC908AZ60 (non-A suffix devices 381 A.1.1 Specification . . . . . . . . . . . . . . ...

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Chapter 1 General Description 1.1 Introduction The MC68HC908AS60A, MC68HC908AZ60A, and MC68HC908AZ60E are members of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available ...

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General Description • Master Reset Pin and Power-On Reset • 16-Bit, 2-Channel Timer Interface Module (TIMB) (AZ only) • 5-Bit Keyboard Interrupt Module (64-Pin QFP only) • MSCAN Controller Implements CAN 2.0b Protocol as Defined in BOSCH Specification September 1991 ...

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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 62 BYTES USER FLASH — 60 kBYTES USER RAM — 2048BYTES USER EEPROM — 1024 BYTES MONITOR ROM — 256 BYTES USER FLASH VECTOR SPACE — 52 BYTES ...

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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 62 BYTES USER FLASH — 60 kBYTES USER RAM — 2048BYTES USER EEPROM — 1024 BYTES MONITOR ROM — 256 BYTES USER FLASH VECTOR SPACE — 52 BYTES ...

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Pin Assignments Figure 1-3 shows the MC68HC908AZ60A pin assignments. PTC4 1 IRQ 2 RST 3 PTF0/TACH2 4 PTF1/TACH3 5 PTF2/TACH4 6 PTF3/TACH5 7 PTF4/TBCH0 8 CANRx 9 CANTx 10 PTF5/TBCH1 11 PTF6 12 PTE0/TxD 13 PTE1/RxD 14 PTE2/TACH0 15 ...

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General Description Figure 1-4 shows the MC68HC908AS60A 64-pin QFP pin assignments. PTC4 1 IRQ 2 RST 3 PTF0/TACH2 4 PTF1/TACH3 5 PTF2/TACH4 6 PTF3/TACH5 7 PTF4 8 BDRxD 9 BDTxD 10 PTF5 11 PTF6 12 PTE0/TxD 13 PTE1/RxD 14 PTE2/TACH0 ...

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Figure 1-5 shows MC68HC908AS60A 52-pin PLCC pin assignments. PTC4 8 IRQ 9 RST 10 PTF0/TACH2 11 PTF1/TACH3 12 PTF2/TACH4 13 PTF3/TACH5 14 BDRxD 15 BDTxD 16 PTE0/TxD 17 PTE1/RxD 18 PTE2/TACH0 19 PTE3/TACH1 20 Figure 1-5. MC68HC908AS60A (52-Pin PLCC) MC68HC908AZ60A ...

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General Description The following pin descriptions are just a quick reference. For a more detailed representation, see 1.4.1 Power Supply Pins (V V and V are the power supply and ground pins. The MCU operates from a single power supply. ...

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Analog Power Supply Pin ( the power supply pin for the analog portion of the Clock Generator Module (CGM). See DDA Chapter 10 Clock Generator Module 1.4.6 Analog Ground Pin ( the ground connection for ...

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General Description 1.4.15 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) Port 8-bit special function port that shares two of its pins with the Timer Interface Module A (TIMA), four of its pins with the Serial Peripheral Interface module (SPI), ...

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Pin Name PTA7–PTA0 PTB7/ATD7–PTB0/ATD0 PTC5–PTC0 PTD7 PTD6/ATD14/TACLK ADC Channel PTD5/ATD13 ADC Channel PTD4/ATD12/TBCLK ADC Channel PTD3/ATD11–PTD0/ATD8 ADC Channels PTE7/SPSCK PTE6/MOSI PTE5/MISO PTE4/SS PTE3/TACH1 PTE2/TACH0 PTE1/RxD PTE0/TxD PTF6 PTF5/TBCH1–PTF4/TBCH0 PTF3/TACH5 PTF2/TACH4 PTF1/TACH3 MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 ...

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General Description Table 1-1. External Pins Summary (Continued) Pin Name PTF0/TACH2 PTG2/KBD2–PTG0/KBD0 PTH1/KBD4 –PTH0/KBD3 DDA V SSA V DDAREF A /V VSS REFL V REFH OSC1 OSC2 CGMXFC IRQ RST CANRx CANTx BDRxD BDTxD 1. ...

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Table 1-2. Clock Signal Naming Conventions Clock Signal Name CGMXCLK CGMOUT Bus Clock SPSCK TACLK TBCLK Module ADC CAN COP CPU FLASH EEPROM RAM SPI SCI TIMA TIMB PIT SIM IRQ BRK LVI CGM MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data ...

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... MC68HC908AS60ACFU (64-Pin QFP) MC68HC908AS60AVFU (64-Pin QFP) MC68HC908AS60AMFU (64-Pin QFP) MC68HC908AS60ACFN (52-Pin PLCC) MC68HC908AS60AVFN (52-Pin PLCC) MC68HC908AS60AMFN (52-Pin PLCC) MC68HC908AZ60ACFU (64-Pin QFP) MC68HC908AZ60AVFU (64-Pin QFP) MC68HC908AZ60AMFU (64-Pin QFP) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Table 1-4. MC Order Numbers Temperature Range – ...

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Chapter 2 Memory Map 2.1 Introduction The CPU08 can address 64K bytes of memory space. The memory map, shown in • 60K Bytes of FLASH EEPROM • 2048 Bytes of RAM • 1024 Bytes of EEPROM with Protect Option • ...

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Memory Map MC68HC908AZ60A $0000 ↓ $003F $0040 ↓ I/O REGISTERS 16 BYTES $004F $0050 ↓ $044F $0450 FLASH-2 ↓ 176 BYTES $04FF $0500 CAN CONTROL AND MESSAGE BUFFERS ↓ 128 BYTES $057F $0580 FLASH-2 ↓ 128 BYTES $05FF $0600 ↓ ...

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MC68HC908AZ60A $FE03 SIM BREAK FLAG CONTROL REGISTER (SBFCR) $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 CONFIGURATION WRITE-ONCE REGISER (CONFIG-2) $FE0A $FE0B $FE0C $FE0D $FE0E BREAK STATUS AND CONTROL REGISTER (BSCR) $FE0F $FE10 EEPROM-1EEDIVH NONVOLATILE REGISTER(EE1DIVHNVR) $FE11 EEPROM-1EEDIVL NONVOLATILE REGISTER(EE1DIVLNVR) $FE12 $FE13 ...

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Memory Map MC68HC908AZ60A $FF75 $FF76 $FF77 $FF78 $FF79 $FF7A EEPROM-2 EE DIVIDER HIGH REGISTER (EE2DIVH) $FF7B EEPROM-2 EE DIVIDER LOW REGISTER (EE2DIVL) $FF7C EEPROM-2 EEPROM NONVOLATILE REGISTER (EE2NVR) $FF7D EEPROM-2 EEPROM CONTROL REGISTER (EE2CR) $FF7E $FF7F EEPROM-2 EEPROM ARRAY CONFIGURATION ...

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I/O Section Addresses $0000–$004F, shown in Addr. Register Name Read: Port A Data Register $0000 (PTA) Write: Read: Port B Data Register $0001 (PTB) Write: Read: Port C Data Register $0002 (PTC) Write: Read: Port D Data Register $0003 ...

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Memory Map Addr. Register Name Read: SPI Control Register $0010 (SPCR) Write: Read: SPI Status and Control $0011 Register (SPSCR) Write: Read: SPI Data Register $0012 (SPDR) Write: Read: SCI Control Register 1 $0013 (SCC1) Write: Read: SCI Control Register ...

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Addr. Register Name Read: Keyboard Interrupt Enable $0021 Register (KBIER) Write: Read: Timer A Counter Register $0022 High (TACNTH) Write: Read: Timer A Counter Register $0023 Low (TACNTL) Write: Read: Timer A Modulo Register $0024 High (TAMODH) Write: Read: Timer ...

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Memory Map Addr. Register Name Read: Timer A Channel 4 Status $0032 and Control Register (TASC4) Write: Read: Timer A Channel 4 Register $0033 High (TACH4H) Write: Read: Timer A Channel 4 Register $0034 Low (TACH4L) Write: Read: Timer A ...

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Addr. Register Name Read: Timer B Modulo Register $0043 High (TBMODH) Write: Read: Timer B Modulo Register $0044 Low (TBMODL) Write: Read: Timer B CH0 Status and $0045 Control Register (TBSC0) Write: Read: Timer B CH0 Register $0046 High (TBCH0H) ...

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Memory Map 2.3 Additional Status and Control Registers Selected addresses in the range $FE00 to $FFCB contain additional Status and Control registers as shown in Figure 2-3. A noted exception is the COP Control Register (COPCTL) at address $FFFF. Addr. ...

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Addr. Register Name Read: UNUSED EEPROM-1 Array Configura- $FE1F tion Register (EE1ACR) Write: $FF70 Read: EEDIVS- EE2DIV Hi Nonvolatile Register (EE2DIVHNVR) Write: $FF71 Read: EE2DIV Lo Nonvolatile Register (EE2DIVLNVR) Write: $FF7A EE2DIV Divider High Register Read: EEDIVS- (EE2DIVH) Write: $FF7B ...

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Memory Map 2.4 Vector Addresses and Priority Addresses in the range $FFCC to $FFFF contain the user-specified vector locations. The vector addresses are shown in Table MC68HC908AS60A and the MC68HC908AZ60A as shown in the table recommended that all ...

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Table 2-1. Vector Addresses (Continued) Address $FFED $FFEE $FFEF $FFF0 $FFF1 $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE Highest Priority $FFFF MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor Vector MC68HC908AZ60A ...

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Memory Map MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

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Chapter 3 Random-Access Memory (RAM) 3.1 Introduction This chapter describes the 2048 bytes of random-access memory (RAM). 3.2 Functional Description Addresses $0050 through $044F and $0A00 through $0DFF are RAM locations. The location of the stack RAM is programmable with ...

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Random-Access Memory (RAM) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

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Chapter 4 FLASH-1 Memory 4.1 Introduction This chapter describes the operation of the embedded FLASH-1 memory. This memory can be read, programmed and erased from a single external supply. The program and erase operations are enabled through the use of ...

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FLASH-1 Memory 4.3 FLASH-1 Control and Block Protect Registers The FLASH-1 array has two registers that control its operation, the FLASH-1 Control Register (FL1CR) and the FLASH-1 Block Protect Register (FL1BPR). 4.3.1 FLASH-1 Control Register The FLASH-1 Control Register (FL1CR) ...

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FLASH-1 Block Protect Register The FLASH-1 Block Protect Register (FL1BPR) is implemented as a byte within the FLASH-1 memory and therefore can only be written during a FLASH programming sequence. The value in this register determines the starting location ...

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FLASH-1 Memory Decreasing the value in FL1BPR by one increases the protected range by one page (128 bytes). However, programming the block protect register with $FE protects a range twice that size, 256 bytes, in the corresponding array. $FE means ...

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FLASH-1 Mass Erase Operation Use this step-by-step procedure to erase the entire FLASH-1 memory to read as logic 1: 1. Set both the ERASE bit and the MASS bit in the FLASH-1 Control Register (FL1CR). 2. Read the FLASH-1 ...

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FLASH-1 Memory 4.6 FLASH-1 Page Erase Operation Use this step-by-step procedure to erase a page (128 bytes) of FLASH-1 memory to read as logic 1: 1. Set the ERASE bit and clear the MASS bit in the FLASH-1 Control Register ...

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Write to any FLASH-1 address within the row address range desired with any data. 4. Wait for time NVS 5. Set the HVEN bit. 6. Wait for time PGS 7. Write data byte to the ...

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FLASH-1 Memory Algorithm for programming a row (64 bytes) of FLASH memory NOTE: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing PGM bit (step 7 ...

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Low-Power Modes The WAIT and STOP instructions will place the MCU in low power consumption standby modes. 4.8.1 WAIT Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of ...

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FLASH-1 Memory MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

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Chapter 5 FLASH-2 Memory 5.1 Introduction This chapter describes the operation of the embedded FLASH-2 memory. This memory can be read, programmed and erased from a single external supply. The program and erase operations are enabled through the use of ...

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FLASH-2 Memory 5.3 FLASH-2 Control and Block Protect Registers The FLASH-2 array has two registers that control its operation, the FLASH-2 Control Register (FL2CR) and the FLASH-2 Block Protect Register (FL2BPR). 5.3.1 FLASH-2 Control Register The FLASH-2 Control Register (FL2CR) ...

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Address: $FF81 Bit 7 Read: BPR7 Write: Figure 5-2. FLASH-2 Block Protect Register (FL2BPR) The FLASH-2 Block Protect Register (FL2BPR) controls the block protection for the FLASH-2 array. However, FL2BPR is implemented within the FLASH-1 memory array and therefore, the ...

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FLASH-2 Memory Decreasing the value in FL2BPR by one increases the protected range by one page (128 bytes). However, programming the block protect register with $FE protects a range twice that size, 256 bytes, in the corresponding array. $FE means ...

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FLASH-2 Mass Erase Operation Use this step-by-step procedure to erase the entire FLASH-2 memory to read as logic 1: 1. Set both the ERASE bit and the MASS bit in the FLASH-2 Control Register (FL2CR). 2. Read the FLASH-2 ...

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FLASH-2 Memory 5.6 FLASH-2 Page Erase Operation Use this step-by-step procedure to erase a page (128 bytes) of FLASH-2 memory to read as logic 1: 1. Set the ERASE bit and clear the MASS bit in the FLASH-2 Control Register ...

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Wait for time NVS 5. Set the HVEN bit. 6. Wait for time PGS 7. Write data byte to the FLASH-2 address to be programmed. 8. Wait for time PROG 9. Repeat step ...

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FLASH-2 Memory Algorithm for programming a row (64 bytes) of FLASH memory NOTE: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing PGM bit (step 7 ...

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Low-Power Modes The WAIT and STOP instructions will place the MCU in low power consumption standby modes. 5.8.1 WAIT Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of ...

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FLASH-2 Memory MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

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Chapter 6 EEPROM-1 Memory 6.1 Introduction This chapter describes the 512 bytes of electrically erasable programmable read-only memory (EEPROM) residing at address range $0800 to $09FF. There are 1024 bytes of EEPROM available on the MC68HC908AS60A and MC68HC908AZ60A which are ...

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EEPROM-1 Memory Addr. Register Name Read: EEDIVS- EE1DIV Nonvolatile $FE10 Register High Write: (1) (EE1DIVHNVR) Reset: Read: EE1DIV Nonvolatile $FE11 Register Low Write: (1) (EE1DIVLNVR) Reset: Read: EEDIVS- EE1 Divider Register High $FE1A Write: (EE1DIVH) Reset: Read: EE1 Divider Register ...

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Functional Description The 512 bytes of EEPROM-1 are located at $0800-$09FF and can be programmed or erased without an additional external high voltage supply. The program and erase operations are enabled through the use of an internal charge pump. ...

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EEPROM-1 Memory 6.4.3 EEPROM-1 Program/Erase Protection The EEPROM has a special feature that designates the 16 bytes of addresses from $08F0 to $08FF to be permanently secured. This program/erase protect option is enabled by programming the EEPRTCT bit in the ...

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EEPROM-1 Programming and Erasing The unprogrammed or erase state of an EEPROM bit is a logic 1. The factory default for all bytes within the EEPROM-1 array is $FF. The programming operation changes an EEPROM bit from logic 1 ...

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EEPROM-1 Memory 6.4.5.2 EEPROM-1 Programming The unprogrammed or erase state of an EEPROM bit is a logic 1. Programming changes the state to a logic 0. Only EEPROM bytes in the non-protected blocks and the EE1NVR register can be programmed. ...

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EEPROM-1 Erasing The programmed state of an EEPROM bit is logic 0. Erasing changes the state to a logic 1. Only EEPROM-1 bytes in the non-protected blocks and the EE1NVR register can be erased. Use the following procedure to ...

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EEPROM-1 Memory 6.5 EEPROM-1 Register Descriptions Four I/O registers and three nonvolatile registers control program, erase and options of the EEPROM-1 array. 6.5.1 EEPROM-1 Control Register This read/write register controls programming/erasing of the array. Address: $FE1D Bit 7 Read: UNUSED ...

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AUTO — Automatic Termination of Program/Erase Cycle When AUTO is set, EEPGM is cleared automatically after the program/erase cycle is terminated by the internal timer. (See note D for 6.4.5.2 EEPROM-1 Memory Characteristics Automatic clear of EEPGM is ...

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EEPROM-1 Memory EEBP[3:0] — EEPROM-1 Block Protection Bits These bits prevent blocks of EEPROM-1 array from being programmed or erased EEPROM-1 array block is protected 0 = EEPROM-1 array block is unprotected Block Number (EEBPx) EEBP0 EEBP1 EEBP2 ...

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EEPROM-1 Nonvolatile Register The contents of this register is loaded into the EEPROM-1 array configuration register (EE1ACR) after a reset. This register is erased and programmed in the same way as an EEPROM byte. (See Control Register for individual ...

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EEPROM-1 Memory EEDIVSECD — EEPROM-1 Divider Security Disable This bit enables/disables the security feature of the EE1DIV registers. When EE1DIV security feature is enabled, the state of the registers EE1DIVH and EE1DIVL are locked (including EEDIVSECD bit). The EE1DIVHNVR and ...

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These two registers are protected from erase and program operations if the EEDIVSECD is set to logic 1 in the EE1DIVH (see EEPROM-1 Timebase Divider Register) or programmed to a logic 1 in the EE1DIVHNVR. Once EEDIVSECD in the EE1DIVHNVR ...

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EEPROM-1 Memory MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

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Chapter 7 EEPROM-2 Memory 7.1 Introduction This chapter describes the 512 bytes of electrically erasable programmable read-only memory (EEPROM) residing at address range $0600 to $07FF. There are 1024 bytes of EEPROM available on the MC68HC908AS60A and MC68HC908AZ60A which are ...

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EEPROM-2 Memory Addr. Register Name Read: EEDIVS- EE2DIV Nonvolatile $FF70 Register High Write: (EE2DIVHNVR)* Reset: Read: EE2DIV Nonvolatile $FF71 Register Low Write: (EE2DIVLNVR)* Reset: Read: EEDIVS- EE2 Divider Register High $FF7A Write: (EE2DIVH) Reset: Read: EE2 Divider Register Low $FF7B ...

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Functional Description The 512 bytes of EEPROM-2 are located at $0600-$07FF and can be programmed or erased without an additional external high voltage supply. The program and erase operations are enabled through the use of an internal charge pump. ...

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EEPROM-2 Memory 7.4.3 EEPROM-2 Program/Erase Protection The EEPROM has a special feature that designates the 16 bytes of addresses from $06F0 to $06FF to be permanently secured. This program/erase protect option is enabled by programming the EEPRTCT bit in the ...

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EEPROM-2 Programming and Erasing The unprogrammed or erase state of an EEPROM bit is a logic 1. The factory default for all bytes within the EEPROM-2 array is $FF. The programming operation changes an EEPROM bit from logic 1 ...

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EEPROM-2 Memory 7.4.5.2 EEPROM-2 Programming The unprogrammed or erase state of an EEPROM bit is a logic 1. Programming changes the state to a logic 0. Only EEPROM bytes in the non-protected blocks and the EE2NVR register can be programmed. ...

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EEPROM-2 Erasing The programmed state of an EEPROM bit is logic 0. Erasing changes the state to a logic 1. Only EEPROM-2 bytes in the non-protected blocks and the EE2NVR register can be erased. Use the following procedure to ...

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EEPROM-2 Memory 7.5 EEPROM-2 Register Descriptions Four I/O registers and three nonvolatile registers control program, erase and options of the EEPROM-2 array. 7.5.1 EEPROM-2 Control Register This read/write register controls programming/erasing of the array. Address: $FF7D Bit 7 Read: UNUSED ...

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AUTO — Automatic Termination of Program/Erase Cycle When AUTO is set, EEPGM is cleared automatically after the program/erase cycle is terminated by the internal timer. (See note D for 7.4.5.2 EEPROM-2 Memory Characteristics Automatic clear of EEPGM is ...

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EEPROM-2 Memory EEBP[3:0] — EEPROM-2 Block Protection Bits These bits prevent blocks of EEPROM-2 array from being programmed or erased EEPROM-2 array block is protected 0 = EEPROM-2 array block is unprotected Block Number (EEBPx) EEBP0 EEBP1 EEBP2 ...

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EEPROM-2 Nonvolatile Register The contents of this register is loaded into the EEPROM-2 array configuration register (EE2ACR) after a reset. This register is erased and programmed in the same way as an EEPROM byte. (See Control Register for individual ...

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EEPROM-2 Memory EEDIVSECD — EEPROM-2 Divider Security Disable This bit enables/disables the security feature of the EE2DIV registers. When EE2DIV security feature is enabled, the state of the registers EE2DIVH and EE2DIVL are locked (including EEDIVSECD bit). The EE2DIVHNVR and ...

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These two registers are protected from erase and program operations if the EEDIVSECD is set to logic 1 in EE2DIVH or programmed to a logic 1 in EE2DIVHNVR. Once EEDIVSECD in the EE2DIVHNVR is programmed to 0 and after a ...

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EEPROM-2 Memory MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev Freescale Semiconductor ...

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Chapter 8 Central Processor Unit (CPU) 8.1 Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction ...

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Central Processor Unit (CPU 8.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 Read: Write: Reset: 8.3.2 Index Register The ...

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Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least ...

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Central Processor Unit (CPU) 8.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following ...

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Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00 Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the ...

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Central Processor Unit (CPU) 8.7 Instruction Set Summary Table 8-1 provides a summary of the M68HC08 instruction set. Table 8-1. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr ADC opr,X Add with ...

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Table 8-1. Instruction Set Summary (Sheet Source Operation Form Branch if Higher or Same BHS rel (Same as BCC) BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT #opr BIT opr ...

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Central Processor Unit (CPU) Table 8-1. Instruction Set Summary (Sheet Source Operation Form CLR opr CLRA CLRX CLRH Clear CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X Compare A with M ...

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Table 8-1. Instruction Set Summary (Sheet Source Operation Form JMP opr JMP opr JMP opr,X Jump JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr ...

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Central Processor Unit (CPU) Table 8-1. Instruction Set Summary (Sheet Source Operation Form PULA Pull A from Stack PULH Pull H from Stack PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL ...

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Table 8-1. Instruction Set Summary (Sheet Source Operation Form SWI Software Interrupt TAP Transfer A to CCR TAX Transfer TPA Transfer CCR to A TST opr TSTA TSTX Test for Negative or Zero TST ...

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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...

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Chapter 9 System Integration Module (SIM) 9.1 Introduction This chapter describes the system integration module (SIM), which supports external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all MCU activities. A block ...

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System Integration Module (SIM) RESET PIN LOGIC SIM RESET STATUS REGISTER Register Name SIM Break Status Register (SBSR) SIM Reset Status Register (SRSR) SIM Break Flag Control Register (SBFCR) Table 9-1. I/O Register Address Summary Register Address MC68HC908AZ60A • MC68HC908AS60A ...

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Table 9-2 shows the internal signal names used in this chapter. Signal Name CGMXCLK CGMVCLK CGMOUT IAB IDB PORRST IRST R/W 9.2 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and ...

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System Integration Module (SIM) 9.2.2 Clock Startup from POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase ...

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Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles ...

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System Integration Module (SIM) 9.3.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM ...

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Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register SRSR) and ...

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System Integration Module (SIM) 9.4.3 SIM Counter and Reset States External reset has no effect on the SIM counter. See free-running after all reset states. See internal reset recovery sequences. 9.5 Program Exception Control Normal, sequential program execution can be ...

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YES (AS MANY INTERRUPTS AS EXIST ON CHIP) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO YES IRQ1 INTERRUPT? NO STACK CPU REGISTERS. LOAD ...

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System Integration Module (SIM) MODULE INTERRUPT I BIT IAB SP – 4 IDB CCR R/W 9.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When ...

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The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. To maintain compatibility with the M68HC05, M6805 and M146805 Families the H register ...

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System Integration Module (SIM) 9.6.1 Wait Mode In wait mode, the CPU clocks are inactive while one set of peripheral clocks continue to run. shows the timing for wait mode entry. A module that is active during wait mode can ...

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Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time ...

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System Integration Module (SIM) 9.7 SIM Registers The SIM has three memory mapped registers. 9.7.1 SIM Break Status Register The SIM break status register contains a flag to indicate that a break caused an exit from wait mode. Address: $FE00 ...

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ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (opcode fetches only Last reset caused by an opcode fetch ...

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System Integration Module (SIM) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 126 Freescale Semiconductor ...

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Chapter 10 Clock Generator Module (CGM) 10.1 Introduction The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, from which the system clocks are derived. ...

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Clock Generator Module (CGM) OSC1 CGMRDV CGMRCLK V DDA PHASE DETECTOR LOCK DETECTOR LOCK CGMVDV MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 128 CLOCK SELECT CIRCUIT BCS CGMXFC V SS VRS7–VRS4 VOLTAGE LOOP CONTROLLED FILTER OSCILLATOR PLL ANALOG ...

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Register Name Read: PLL Control Register (PCTL) Write: Reset: Read: PLL Bandwidth Control Register (PB- Write: WC) Reset: Read: PLL Programming Register (PPG) Write: Reset: Table 10-1. I/O Register Address Summary Register Address 10.3.1 Crystal Oscillator Circuit The crystal oscillator ...

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Clock Generator Module (CGM) 10.3.2.1 Circuits The PLL consists of these circuits: • Voltage-controlled oscillator (VCO) • Modulo VCO frequency divider • Phase detector • Loop filter • Lock detector The operating range of the VCO is programmable for a ...

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Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking ...

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Clock Generator Module (CGM) 10.3.2.4 Programming the PLL Use this 9-step procedure to program the PLL. (Please also reference Figure 10-1). Variable f BUSDES f VCLKDES f CGMRCLK f CGMVCLK f BUS f NOM f CGMVRS 1. Choose the desired ...

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Using the value 4.9152 MHz for f multiplier controls the frequency range of the PLL. 8. Calculate the VCO center-of-range frequency, f midpoint between the minimum and maximum frequencies attainable by the PLL. × CGMVRS ...

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Clock Generator Module (CGM) factor L is programmed This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as ...

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I/O Signals The following paragraphs describe the CGM input/output (I/O) signals. 10.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 10.4.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the ...

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Clock Generator Module (CGM) 10.5 CGM Registers Three registers control and monitor operation of the CGM: • PLL control register (PCTL) • PLL bandwidth control register (PBWC) • PLL programming register (PPG) 10.5.1 PLL Control Register The PLL control register ...

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CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. See Selector Circuit. Reset and the STOP instruction clear the ...

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Clock Generator Module (CGM) In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode ...

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Table 10-3. VCO Frequency Multiplier (N) Selection MUL7:MUL6:MUL5:MUL4 0000 0001 0010 0011 1101 1110 1111 The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1). VRS7–VRS4 — VCO Range ...

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Clock Generator Module (CGM) Software can select the CGMVCLK divided by two as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit. ...

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MHz, the acquisition time is the time taken for the frequency to reach 1 MHz ±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a –100 kHz ...

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Clock Generator Module (CGM) Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause ...

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In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. (See 10.3.2.3 Manual and Automatic PLL Bandwidth , is required to ascertain that the PLL is within the tracking mode entry ...

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Clock Generator Module (CGM) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 144 Freescale Semiconductor ...

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Chapter 11 Configuration Register (CONFIG-1) 11.1 Introduction This chapter describes the configuration register (CONFIG-1), which contains bits that configure these options: • Resets caused by the LVI module • Power to the LVI module • LVI enabled during stop mode ...

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Configuration Register (CONFIG-1) LVIRST — LVI Reset Enable Bit LVIRST enables the reset signal from the LVI module. (See 1 = LVI module resets enabled 0 = LVI module resets disabled LVIPWR — LVI Power Enable Bit LVIPWR enables the ...

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Chapter 12 Configuration Register (CONFIG-2) 12.1 Introduction This chapter describes the configuration register (CONFIG-2). This register contains bits that configure these options: • Configures the device to either the MC68HC08AZxx emulator or the MC68HC08ASxx emulator • Disables the CAN module ...

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Configuration Register (CONFIG-2) AZxx — AZxx Emulator Enable Bit AZxx enables the MC68HC08AZxx emulator configuration. This bit will be 0 out of reset MC68HC08AZxx emulator enabled 0 = MC68HC08ASxx emulator enabled AZxx bit is reset by a POWER-ON-RESET ...

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Chapter 13 Break Module (BRK) 13.1 Introduction The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. 13.2 Features • Accessible I/O Registers during Break Interrupts • CPU-Generated ...

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Break Module (BRK) IAB[15:0] Figure 13-1. Break Module Block Diagram Register Name Read: Break Address Register High (BRKH) Write: Reset: Read: Break Address Register Low (BRKL) Write: Reset: Read: Break Status and Control Register Write: (BSCR) Reset: Table 13-1. I/O ...

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Flag Protection During Break Interrupts The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. 13.3.2 CPU During Break Interrupts The CPU starts a break interrupt by: • Loading ...

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Break Module (BRK) 13.5.1 Break Status and Control Register The break status and control register contains break module enable and status bits. Address: $FE0E Bit 7 Read: BRKE Write: Reset: 0 Figure 13-3. Break Status and Control Register (BSCR) BRKE ...

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Chapter 14 Monitor ROM (MON) 14.1 Introduction This chapter describes the monitor ROM (MON). The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. 14.2 Features Features of the monitor ROM include: • ...

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Monitor ROM (MON) 1 MC145407 + 10 μ μ DB- NOTE: Position A — Bus clock = CGMXCLK ÷ CGMVCLK ÷ 4 Position B — Bus clock = ...

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Entering Monitor Mode Table 14-1 shows the pin conditions for entering monitor mode For V , 28.1.4 5.0 Volt DC Electrical HI Enter monitor mode by either • ...

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Monitor ROM (MON) 14.3.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 14-2 and Figure 14-3.) The data transmit and receive rate can be anywhere up to 28.8 kBaud. Transmit and ...

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Commands The monitor ROM uses these commands: • READ, read memory • WRITE, write memory • IREAD, indexed read • IWRITE, indexed write • READSP, read stack pointer • RUN, run user program A sequence of IREAD or IWRITE ...

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Monitor ROM (MON) Table 14-5. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Command ...

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Table 14-8. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data Returned None Opcode $28 Command Sequence 14.3.6 MC68HC908AS60A Baud Rate With a 4.9152-MHz crystal and the PTC3 pin at logic 1 during reset, data is transferred ...

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Monitor ROM (MON) 14.3.7 MC68HC908AZ60A Baud Rate The MC68HC908AZ60A features a monitor mode which is optimised to operate with either a 4.9152 MHz crystal clock source (or multiples of 4.9152 MHz MHz crystal (or multiples of 4 ...

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V DD 4096 + 32 CGMXCLK CYCLES RST FROM HOST PA0 FROM MCU NOTE Echo delay (2 bit times Data return delay (2 bit times Wait 1 bit time before sending next byte. If ...

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Monitor ROM (MON) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 162 Freescale Semiconductor ...

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Chapter 15 Computer Operating Properly (COP) 15.1 Introduction The COP module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by periodically clearing the ...

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Computer Operating Properly (COP) CGMXCLK STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH COPCTL WRITE COPD FROM CONFIG-1 RESET COPCTL WRITE COPL FROM CONFIG-1 15.3.1 CGMXCLK CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal ...

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Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 15.3.7 COPD The COPD signal reflects the state of the COP disable bit (COPD) ...

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Computer Operating Properly (COP) 15.7.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period ...

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Chapter 16 Low-Voltage Inhibit (LVI) 16.1 Introduction This chapter describes the low-voltage inhibit module (LVI47, Version A), which monitors the voltage on the V pin and can force a reset when the V DD 16.2 Features Features of the LVI ...

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Low-Voltage Inhibit (LVI CPU CLOCK V > LVI LOW V DD TRIP DD DETECTOR V < LVI DD TRIP Addr. Register Name $FE0F LVI Status Register (LVISR) 16.3.1 Polled LVI Operation In applications that can operate at V ...

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LVI Status Register The LVI status register flags V DD Address: $FE0F Bit 7 Read: LVIOUT Write: Reset: 0 Figure 16-3. LVI Status Register (LVISR) LVIOUT — LVI Output Bit This read-only flag becomes set when the V CGMXCLK ...

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Low-Voltage Inhibit (LVI) 16.6.2 Stop Mode With the LVISTOP and LVIPWR bits in the configuration register programmed to a logic 1, the LVI module will be active after a STOP instruction. Because CPU clocks are disabled during stop mode, the ...

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Chapter 17 External Interrupt Module (IRQ) 17.1 Introduction This chapter describes the nonmaskable external interrupt (IRQ) input. 17.2 Features Features include: • Dedicated External Interrupt Pin (IRQ) • Hysteresis Buffer • Programmable Edge-Only or Edge- and Level-Interrupt Sensitivity • Automatic ...

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External Interrupt Module (IRQ) ACK VECTOR FETCH DECODER IRQ Addr. Register Name $001A IRQ Status/Control Register (ISCR) The external interrupt pin is falling-edge triggered and is software- configurable to be both falling-edge and low-level triggered. The MODE bit in the ...

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YES MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 Freescale Semiconductor FROM RESET I BIT SET? NO YES INTERRUPT? NO STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI YES INSTRUCTION? NO RTI ...

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External Interrupt Module (IRQ) 17.4 IRQ Pin A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, ...

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IRQ Status and Control Register The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR has these functions: • Shows the state of the IRQ interrupt flag • Clears the IRQ interrupt ...

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External Interrupt Module (IRQ) MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 176 Freescale Semiconductor ...

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Chapter 18 Serial Communications Interface (SCI) 18.1 Introduction The SCI allows asynchronous communications with peripheral devices and other MCUs. 18.2 Features The SCI module’s features include: • Full Duplex Operation • Standard Mark/Space Non-Return-to-Zero (NRZ) Format • 32 Programmable Baud ...

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Serial Communications Interface (SCI) Generic Pin Names Full Pin Names 18.4 Functional Description Figure 18-1 shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The ...

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Register Name Read: SCI Control Register 1 (SCC1) Write: Reset: Read: SCI Control Register 2 (SCC2) Write: Reset: Read: SCI Control Register 3 (SCC3) Write: Reset: Read: SCI Status Register 1 (SCS1) Write: Reset: Read: SCI Status Register 2 (SCS2) ...

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Serial Communications Interface (SCI) 18.4.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in START BIT 0 BIT 1 BIT START BIT BIT 0 BIT 1 18.4.2 Transmitter Figure 18-4 shows the structure of the SCI ...

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PRE- BAUD ÷ 4 SCALER DIVIDER SCP1 SCP0 SCR1 SCR2 SCR0 PEN PTY Register Name Read: SCI Control Register 1 (SCC1) Write: Reset: Read: SCI Control Register 2 (SCC2) Write: Reset: Read: SCI Control Register 3 (SCC3) Write: Reset: Figure ...

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Serial Communications Interface (SCI) Register Name Read: SCI Status Register 1 (SCS1) Write: Reset: Read: SCI Data Register (SCDR) Write: Reset: Read: SCI Baud Rate Register (SCBR) Write: Reset: Figure 18-5. SCI Transmitter I/O Register Summary (Continued) Table 18-3. SCI ...

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Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If ...

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Serial Communications Interface (SCI) SCP1 SCP0 ÷ PRE- 4 SCALER CGMXCLK RxD BKF RPF M WAKE ILTY PEN PTY Figure 18-6. SCI Receiver Block Diagram MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6 184 INTERNAL BUS SCR1 SCR2 SCR0 ...

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Register Name Read: SCI Control Register 1 (SCC1) Write: Reset: Read: SCI Control Register 2 (SCC2) Write: Reset: Read: SCI Control Register 3 (SCC3) Write: Reset: Read: SCI Status Register 1 (SCS1) Write: Reset: Read: SCI Status Register 2 (SCS2) ...

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Serial Communications Interface (SCI) 18.4.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control ...

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To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. 18-5 summarizes the results of the start bit verification samples. RT3, RT5, and RT7 Samples 000 001 010 011 100 101 ...

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Serial Communications Interface (SCI) To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. summarizes the results of the stop bit samples. RT8, RT9, and RT10 Samples 000 001 010 011 100 ...

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For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in when the count of the transmitting ...

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Serial Communications Interface (SCI) The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 18.4.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers ...

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Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate ...

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Serial Communications Interface (SCI) 18.7 I/O Signals Port E shares two of its pins with the SCI module. The two SCI I/O pins are: • PTE0/SCTxD — Transmit data • PTE1/SCRxD — Receive data 18.7.1 PTE0/SCTxD (Transmit Data) The PTE0/SCTxD ...

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Address: $0013 Bit 7 Read: LOOPS Write: Reset: 0 Figure 18-11. SCI Control Register 1 (SCC1) LOOPS — Loop Mode Select Bit This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the SCI, ...

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Serial Communications Interface (SCI Idle character bit count begins after start bit PEN — Parity Enable Bit This read/write bit enables the SCI parity function. (See inserts a parity bit in the most significant bit position. (See 1 ...

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Address: $0014 Bit 7 Read: SCTIE Write: Reset: 0 Figure 18-12. SCI Control Register 2 (SCC2) SCTIE — SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Setting the SCTIE ...

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Serial Communications Interface (SCI) RE — Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit Receiver enabled ...

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R8 — Received Bit 8 When the SCI is receiving 9-bit characters the read-only ninth bit (bit 8) of the received character received at the same time that the SCDR receives the other 8 bits. When ...

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Serial Communications Interface (SCI) Address: $0016 Bit 7 Read: SCTE Write: Reset: 1 Figure 18-14. SCI Status Register 1 (SCS1) SCTE — SCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the ...

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OR — Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIE ...

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Serial Communications Interface (SCI) FE — Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 ...

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