SAA5264PS/M3/0764 Cirrus Logic, Inc., SAA5264PS/M3/0764 Datasheet
SAA5264PS/M3/0764
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SAA5264PS/M3/0764 Summary of contents
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Features Provides Analog Transmission Line Interface for T1 and E1 Applications Drop-in Replacement for CS61574 with the Following Enhancements: Lower Power Consumption - Transmitter Short-Circuit - Current Limiting Greater Transmitter Immunity - to Line Reflections Software Selection Between 75 - ...
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ABSOLUTE MAXIMUM RATINGS Parameter DC Supply (referenced to RGND=TGND=0V) Input Voltage, Any Pin Input Current, Any Pin Ambient Operating Temperature Storage Temperature WARNING:Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not ...
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ANALOG SPECIFICATIONS Parameter Transmitter AMI Output Pulse Amplitudes E1, 75 E1, 120 T1, (FCC Part 68) T1, DSX-1 Load Presented To Transmitter Output Jitter Added During Remote Loopback 10Hz - 8kHz 8kHz - 40kHz 10Hz - 40kHz Broad Band Power ...
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ANALOG SPECIFICATIONS Parameter Receiver RTIP/RRING Input Impedance Sensitivity Below DSX (0dB = 2.4V) Loss of Signal Threshold Data Decision Threshold T1, DSX-1 T1, DSX-1 T1, (FCC Part 68) and E1 (Note 22) Allowable Consecutive Zeros before LOS Receiver Input Jitter ...
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T1 SWITCHING CHARACTERISTICS GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Parameter Crystal Frequency TCLK Frequency ACLKI Frequency RCLK Duty Cycle Rise Time, All Digital Outputs Fall Time, All Digital ...
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SWITCHING CHARACTERISTICS Inputs: Logic 0 = 0V, Logic 1 = RV+) Parameter SDI to SCLK Setup Time SCLK to SDI Hold Time SCLK Low Time SCLK High Time SCLK Rise and Fall Time CS to SCLK Setup Time SCLK to ...
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Figure 3. Transmit Clock and Data Switching Characteristics SCLK t cdh t dc SDI LSB CONTROL CS SCLK t cdv SDO CLKE = 1 LEN0/1/2, TAOS, RLOOP, LLOOP, RLOOP, LLOOP, RCODE, TCODE Figure 6. Extended ...
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THEORY OF OPERATION CS61577 Enhancements Relative to CS61574 Existing designs using the CS61574 can be con- verted to the higher performance, pin-compatible CS61577 with no changes to the PCB, external component or system software. The CS61577 provides higher performance and ...
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TPOS TNEG CS61577 CS62180B FRAMER CIRCUIT RPOS RNEG ATTENUATOR TCODE TDATA AMI B8ZS, REPEATER HDB3, OR CODER MUX RDATA BPV AIS P SERIAL PORT 5 CONTROL TPOS TNEG CS62180B FRAMER CIRCUIT RPOS RNEG ATTENUATOR DS155PP2 HARDWARE MODE ...
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Transmitter The transmitter takes digital input data and drives appropriately shaped bipolar pulses onto a transmission line through a 1:2 trans- former. The transmit data (TPOS & TNEG or TDATA) is supplied synchronously and sampled on the ...
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Percent of nominal peak 269 ns voltage 120 110 244 ns 100 194 -10 -20 219 ns 488 ns Figure 9. Mask of the Pulse at the 2048 kbps Interface Transmit All Ones Select ...
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RTIP RRING put from the phase selector feeds the clock and data recovery circuits which generate the recov- ered clock and sample the incoming signal at appropriate intervals to recover the data. Data sampling will continue at ...
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MODE CLKE (pin 5) (pin 28) DATA CLOCK LOW RPOS RCLK X (<0.2V) RNEG RCLK RPOS RCLK HIGH LOW RNEG RCLK (>(V+) - 0.2V) SDO SCLK RPOS RCLK HIGH HIGH RNEG RCLK (>(V+) - 0.2V) SDO SCLK MIDDLE X RDATA ...
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Minimum Attenuation Limit 10 62411 Requirements Maximum 40 Attenuation Limit 100 Frequency in Hz Figure 12. Typical Jitter Transfer Function The FIFO in the jitter attenuator is designed to prevent overflow ...
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Simultaneous selection of local and remote loop- back modes is not valid (see Reset). In the Extended Hardware Mode the transmitted data is looped before the AMI/B8ZS/HDB3 en- coder/decoder during remote loopback so that the transmitted signal matches the received ...
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CS SCLK SDI R Address/Command Byte SDO Serial Interface In the Host Mode, pins 23 through 28 serve as a microprocessor/microcontroller interface. One on-board register can be written to via the SDI pin or read from via the ...
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Writing a "1" to either "Clear LOS" or "Clear DPM" over the serial interface has three effects: 1) The current interrupt on the serial interface will be cleared. (Note that simply reading the register bits will not clear the inter- ...
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In either mode, a reset will set all reg- isters to 0 and force the oscillator to its center frequency before initiating calibration. A reset will also set LOS high. Power Supply The device operates from a single ...
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PIN DESCRIPTIONS ACLKI TCLK TPOS TNEG MODE RNEG RPOS RCLK XTALIN XTALOUT TGND DS155PP2 Hardware Mode ACLKI TAOS 1 28 TCLK LLOOP 2 27 TPOS RLOOP 26 3 TNEG LEN2 4 25 MODE LEN1 5 24 RNEG LEN0 6 23 ...
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ACLKI TCLK TPOS TNEG MODE RNEG RPOS RCLK XTALIN XTALOUT TGND 20 Host Mode ACLKI CLKE 1 28 TCLK SCLK 2 27 TPOS TNEG SDO 4 25 MODE SDI 5 24 RNEG INT 6 23 RPOS RGND ...
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Power Supplies RGND - Ground, Pin 22. Power supply ground for all subcircuits except the transmit driver; typically 0 Volts. RV+ - Power Supply, Pin 21. Power supply for all subcircuits except the transmit driver; typically +5 Volts. TGND - ...
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LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended Hardware Modes) Determines the shape and amplitude of the transmitted pulse to accommodate several cable types and lengths. See Table 3 for information on line ...
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TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes) Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined by TCLK. In the Host Mode, simultaneous selection of RLOOP & ...
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TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16. The AMI signal is driven to the line through these pins. The transmitter output is designed to drive a 25 load between TTIP and TRING. A transformer is required ...
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D SEATING PLANE e1 B1 NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED ...
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APPLICATIONS + 28 Control & 12 Monitor 11 RV+ Frame Format Encoder/ Decoder XTL 10 Frequency MHz 1.544 (T1) CXT6176 2.048 (E1) CXT8192 Line Interface Figures A1-A3 show typical T1 and E1 line inter- face application circuits. Table A1 shows ...
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Control & 27 Monitor 12 11 Frame Format Encoder/ Decoder XTL 10 Figure A2. 120 + Control 26 & 27 Monitor 12 11 Frame Format Encoder/ Decoder XTL 10 Figure A3. 75 DS155PP2 +5V ...
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Transformers Recommended transmitter and receiver trans- former specifications are shown in Table A2. The transformers in Table A3 have been tested and recommended for use with the CS61577. Refer to the "Telecom Transformer Selection Guide" for detailed schematics which show ...
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Interfacing The CS61577 With the CS62180B T1 Transceiver To interface with the CS62180B, connect the de- vices as shown in Figure A5. In this case, the line interface and CS62180B are in host mode con- trolled by a microprocessor serial ...
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Notes • ...
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Line Interface Evaluation Board Features Socketed Line Interface Device All Required Components for Complete Line Interface Evaluation Configuration by DIP Switch or Serial Interface LED Status Indicators for Alarm Conditions Support for Host, Hardware, and Extended Hardware Modes Mode Select ...
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POWER SUPPLY As shown on the evaluation board schematic in Figure 1, power is supplied to the evaluation board from an external +5 Volt supply connected to the two binding posts labeled +5V and GND. Transient suppressor D10 protects the ...
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GND (0V) RNEG (BPV) RCLK TCLK TPOS (TDATA) RPOS (RDATA) R1 51.1 RV+ ACLKI R15 TNEG 100 S2 RCODE TCODE LEN0/INT LEN1/SDI LEN2/SD0 RLOOP/CS LLOOP/SCLK TAOS/CLKE INT SDI SDO CS SCLK D8 D9 JP1 1N914 S1 RESET R4 221k ...
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Performance Monitor alarm. The LED labeled LOS illuminates when the line interface receiver has detected a loss of signal. Extended Hardware Mode In the Extended Hardware operating mode, the line interface is configured using DIP switch S2. The digital control ...
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The evaluation board supports 100 T1, 75 coax E1, and 120 eration. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 are supplied from the factory with a 1:2 transmit transformer that may be used for all T1 and E1 applications. The ...
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A letter at the intersection of a row and column in Table 2 indicates that the selected transformer is supported for use with the device. The transformer is installed in the evaluation board with pin 1 positioned to match ...
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TRANSFORMER 1,2 (Turns Ratio) PE-65351 (1:2CT) Schott 12930 (1:2CT) PE-65388 (1:1.15) Schott 12931 (1:1.15) PE-65389 (1:1:1.26) Schott 12932 (1:1:1.26) PE-64951 (dual 1:2CT) Schott 11509 (dual 1:2CT) PE-65565 (dual 1:1.15 & 1:2CT) Schott 12531 (dual 1:1.15 & 1:2CT) PE-65566 (dual 1:1:1.26 ...
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LINE INTERFACE EVALUATION BOARD Figure 2. Silk Screen Layer (NOT TO SCALE) DS40DB3 ...
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Figure 3. Top Ground Plane Layer (NOT TO SCALE) DS40DB3 LINE INTERFACE EVALUATION BOARD 39 ...
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LINE INTERFACE EVALUATION BOARD Figure 4. Bottom Trace Layer (NOT TO SCALE) DS40DB3 ...
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Notes • ...
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Notes • ...
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Notes • ...
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TM Smart Analog is a Trademark of Crystal Semiconductor Corporation ...