PEB3086FV1.4 Infineon Technologies AG, PEB3086FV1.4 Datasheet
PEB3086FV1.4
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PEB3086FV1.4 Summary of contents
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ISDN Subscriber Access PEB/PEF 3086 Version 1 ata S he ...
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... Edition 2000-08-03 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 8/3/00. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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ISDN Subscriber Access PEB/PEF 3086 Version 1 ata S he ...
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PEB/PEF 3086 Revision History: Previous Version: Page Subjects (major changes since last revision) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.5.2.3 C/I Codes (LT- ...
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Table of Contents 3.9.5 Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 ...
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Table of Contents 4.3.1 ACFG1 - Auxiliary Configuration Register 192 4.3.2 ACFG2 - Auxiliary Configuration Register ...
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Table of Contents 4.6.5 MODEB - Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Logic Symbol of the ISAC- ...
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List of Figures Figure 40 State Transition Diagram (LT- Figure ...
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List of Figures Figure 74 Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 Comparison of the ISAC-SX with the previous version ISAC- Table 2 ISAC-SX Pin Definitions and Functions . . . . . . . . . . . . . ...
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Overview The ISDN Subscriber Access Controller ISAC-SX integrates a D-channel HDLC controller and a four wire S/T interface used to link voice/data terminals to the ISDN the successor of the ISAC-S PEB 2086 in 3.3 V technology. ...
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Table 1 Comparison of the ISAC-SX with the previous version ISAC-S: Operating modes Supply voltage Technology Package Transceiver Transformer ratio for the transmitter receiver Test Functions Microcontroller Interface Command structure of the register access (SCI) Crystal Buffered 7.68 MHz output ...
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IOM-2 IOM-2 Interface Monitor channel programming C/I channels Layer 1 state machine Layer 1 state machine in software Support of IDSL (144kBit/s) Provided D-channel HDLC support D-channel FIFO size FW download support HDLC support (B-channel) FIFO size (B-channel) Reset Signals ...
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Reset Sources Interrupt Output Signals Data Sheet ISAC-SX PEB 3086 RES Input Watchdog C/I Code Change EAW Pin Software Reset INT low active (open drain) by default, reprogrammable to high active (push-pull) 17 PEB 3086 PEF 3086 Overview ISAC-S PEB ...
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ISDN Subscriber Access Controller ISAC-SX Version 1.3 1.1 Features • Full duplex S/T interface transceiver according to ITU-T I.430 • Successor of ISAC-S PEB 2086 in 3.3V technology • 8-bit parallel microcontroller interface, Motorola and Siemens/Intel bus ...
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Auxiliary Interface with general purpose I/O pins and LED drivers • Two programmable timers • Watchdog timer • Software Reset • Multiframe Synchronization • Test loops • Sophisticated power management for restricted power mode • Power supply 3.3 V ...
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Logic Symbol The logic symbol gives an overview of the ISAC-SX functions. It must be noted that not all functions are available simultaneously, but depend on the selected mode. Pins which are marked with a “ * “ are ...
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Typical Applications The ISAC-SX is designed for the user area of the ISDN basic access, especially for subscriber terminal equipment and for exchange equipment with S interface. Figure 2 illustrates the general application fields of the ISAC-SX. S TE(1) ...
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Pin Configuration BCL / SCLK DU DD FSC DCL VSS VSS VDD MODE0 MODE1 / EAW ACL AUX7 AUX6 AUX5 AUX4 AUX3 Figure 3 Pin Configuration of the ISAC-SX Data Sheet P-MQFP-64 P-TQFP- ...
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Table 2 ISAC-SX Pin Definitions and Functions Pin No. Symbol Input (I) Output (O) MQFP-64 Open Drain TQFP-64 (OD) Host Interface ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 15 AD6 I/O SDR I 16 AD7 I/O SDX R/W I ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 41 ALE INT OD (O) 5 RES I 38 AMODE I IOM-2 Interface 52 FSC ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 49 BCL/SCLK I/O (OD I/O (OD) 29 SDS1 O 28 SDS2 O Auxiliary Interface 30 ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 63 AUX4 I/O (OD) 62 AUX5 I/O (OD) 61 AUX6 I/O (OD) Data Sheet Function • Auxiliary Port 4 (input/output) ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 60 AUX7 I/O (OD) Miscellaneous 43 SX1 O 44 SX2 O 47 SR1 I 48 SR2 I 35 XTAL1 I ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 58 MODE1 I EAW I 59 ACL O 27 C768 O 6 RSTO n.c. ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD 17, – SS 34, 37, 54 – SSA Data Sheet Function Digital ground (0 V) ...
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Description of Functional Blocks 3.1 General Functions and Device Architecture Figure 4 shows the architecture of the ISAC-SX containing the following functions: • S/T-interface transceiver supporting the modes TE, LT-T, LT-S, NT and Intelligent NT • Different host interface ...
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I/O- and Auxiliary Interrupt Interface Lines 8-bit parallel Figure 4 Functional Block Diagram of the ISAC-SX Data Sheet Description of Functional Blocks Peripheral Devices IOM-2 Interface IOM-2 Handler B-channel D-channel MON HDLC HDLC Handler RX/TX RX/TX FIFOs FIFOs Host Interface ...
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Microcontroller Interfaces The ISAC-SX supports a serial or a parallel microcontroller interface. For applications where no controller is connected to the ISAC-SX microcontroller interface programming is done via the IOM-2 MONITOR channel from a master device. In such applications ...
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Serial Control Interface (SCI) The serial control interface (SCI) is compatible to the SPI interface of Motorola or Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCL, SDX, SDR and CS. Data is transferred via the ...
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Programming Sequences The basic structure of a read/write access to the ISAC-SX registers via the serial control interface is shown in Figure write sequence: header SDR 7 read sequence: header SDR 7 SDX Figure 6 Serial Control Interface Timing ...
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Header 40 : Non-interleaved A-D-A-D Sequences H The non-interleaved A-D-A-D sequence gives direct read/write access to the complete address range and can have any length. In this mode SDX and SDR can be connected together allowing data transmission on one ...
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Header 41 : Non-interleaved A-D-D-D Sequence H This sequence allows in front of the A-D-D-D write access a non-interleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. The termination condition of ...
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Parallel Microcontroller Interface The 8-bit parallel microcontroller interface with address decoding on chip allows easy and fast microcontroller access. The parallel interface of the ISAC-SX provides three types of selected via pin ALE. The bus operation modes with corresponding ...
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Indirect Address Mode MODE2:AMOD=1 Address Figure 7 Direct/Indirect Register Address Mode Data Sheet Description of Functional Blocks Direct Address Mode MODE2:AMOD=0 Data Address AD0-7 A0-7 8Fh 8Eh Address DATA 01h ADDRESS 00h 39 PEB 3086 PEF 3086 ...
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Interrupt Structure Special events in the device are indicated by means of a single interrupt output, which requests the host to read status information from the device or transfer data from/to the device. Since only one interrupt request pin ...
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All seven interrupt bits in the ISTA register point at interrupt sources in the D-channel HDLC Controller (ICD), B-channel HDLC controller (ICB), Monitor- (MOS) and C/I- (CIC) handler, the transceiver (TRAN), the synchronous transfer (ST) and the auxiliary interrupts (AUXI). ...
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Reset Generation Figure 9 shows the organization of the reset generation of the device. . 125µs t 250µs C/I Code Change (Exchange Awake) 125µs t 250µs EAW (Subscriber Awake) 125µs t 250µs Watchdog Software Reset 125µs t 250µs Register ...
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Table 6 Reset Source Selection RSS2 RSS1 C/I Code Bit 1 Bit 0 Change • C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/I0) generates ...
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BCL clock cycles. The address range of the registers which will be reset at each SRES bit is listed in 3.2.5 Timer Modes The ISAC-SX provides two timers which can be used ...
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Timer 1 The host controls the timer 1 by setting bit CMDRD.STI to start the timer and by writing register TIMR1 to stop the timer. After time period T1 an interrupt (AUXI.TIN1) is generated continuously if CNT single ...
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Activation Indication via Pin ACL The activated state of the S-interface is directly indicated via pin ACL (Activation LED). An LED with pre-resistance may directly be connected to this pin and a low level is driven on ACL as ...
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S/T-Interface The layer-1 functions for the S/T interface of the ISAC-SX are: – line transceiver functions for the S/T interface according to the electrical specifications of ITU-T I.430; – conversion of the frame structure between IOM-2 and S/T interface; ...
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ISAC- ISAC-SX TR LT-T 1) The maximum line attenuation tolerated by the ISAC- kHz. TR ISAC-SX TE1 .... ISAC-SX TE1 Figure 15 Wiring Configurations in User Premises Data Sheet 1) ...
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S/T-Interface Coding Transmission over the S/T-interface is performed at a rate of 192 kbit/s. 144 kbit/s are used for user data (B1+B2+D), 48 kbit/s are used for framing and maintenance information. Line Coding The following figure illustrates the line ...
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Figure 17 Frame Structure at Reference Points S and T (ITU I.430) – F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N – ...
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S/T-Interface Multiframing According to ITU recommendation I.430 a multiframe provides extra layer 1 capacity in the TE-to-NT direction by using an extra channel between the TE and NT (Q-channel). The Q bits are defined to be the bits in ...
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TE Mode After multiframe synchronization has been established, the Q data will be inserted at the upstream (TE NT) F bit position in each 5th S/T frame (see A When synchronization is not achieved or lost, each received F transmitted ...
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Multiframe Synchronization (M-Bit) The ISAC-SX offers the capability to control the start of the multiframe from external signals, so applications which require synchronization between different S-interfaces are possible. Such an application is the connection of DECT base stations to ...
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Sample Time FSC DCL FSC detected XTAL SX1 / SX2 MBIT Counter reset The sample time of the MBIT input is related to the rising edge of FSC at the beginning frame -- min ...
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(NT -> TE FSC DD ( MBIT (o) Figure 21 Frame Relationship LT-T mode (M-Bit output) Data Sheet ...
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Data Transfer and Delay between IOM-2 and S/T TE mode In the state F7 (Activated the internal layer-1 statemachine is disabled and XINF of register TR_CMD is programmed to ’011’ the B1, B2, D and E bits ...
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-> -> FSC Mapping of B-Channel Timeslots Mapping of a 4-bit group of D-bits on S and IOM depends on ...
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-> -> FSC Figure 24 Data Delay between IOM-2 and S/T Interface with 8 IOM Channels (LT-S/NT mode only) E ...
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Transmitter Characteristics The full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter which is realized as a symmetrical current limited voltage source ( mA). The equivalent circuit of the transmitter is shown in max The ...
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Receiver Characteristics The receiver consists of a differential input stage, a peak detector and a set of comparators. Additional noise immunity is achieved by digital oversampling after the comparators. A simplified equivalent circuit of the receiver is shown in ...
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S/T Interface Circuitry For both, receive and transmit direction a 1:1 transformer is used to connect the ISAC- SX transceiver to the 4 wire S/T interface. Typical transformer characteristics can be found in the chapter on electrical characteristics. The ...
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Protection Circuit for Transmitter SX1 SX2 Figure 29 External Circuitry for Transmitter Figure 29 illustrates the secondary protection circuit recommended for the transmitter. The external resistors (5 ... 10 pulse mask on the one hand and in order to meet ...
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Protection Circuit for Receiver Figure 30 illustrates the external circuitry used in combination with a symmetrical receiver. Protection of symmetrical receivers is rather simple. Note capacitors are optional for noise reduction Figure 30 External Circuitry for ...
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Level Detection Power Down If MODE1.CFS is set to ’0’, the clocks are also provided in power down state, whereas if CFS is set to ’1’ only the analog level detector is active in power down state. All clocks, ...
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Test Functions The ISAC-SX provides test and diagnostic functions for the S/T interface: – The internal local loop (internal Loop A) is activated by a C/I command ARL or by setting the bit LP_A (Loop Analog) in the TR_CMD ...
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S/T interface according to the modified AMI code are initiated via a C/I command written in CIX0 register (see Two kinds of test signals may be transmitted by the ISAC-SX: – The ...
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Clock Generation Figure 33 shows the clock system of the ISAC-SX. The oscillator is used to generate a 7.68 MHz clock signal (f XTAL (8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames. ...
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Table 9 Clock Modes TE LT-T Selected via pin: MODE0=0 pin:MODE1=0 MODE0=1 FSC o:8 kHz i:8 kHz (DIS_TR=0) i:8 kHz (DIS_TR=1) *2) DCL o:1536 kHz i:1536 kHz (DIS_TR=0) (from SCLK) i:1536/768 kHz or 4096 kHz (DIS_TR=1) (from ext. PLL) *2) ...
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Note input output; For all input clocks typical values are given although other clock frequencies may be used, too. 1) The modes TE, LT-T and LT-S can directly be selected by strapping the pins MODE1 and ...
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Description of the Receive PLL (DPLL) The receive PLL performs phase tracking between the F/L transition of the receive signal and the recovered clock. Phase adjustment is done by adding or subtracting 0 XTAL period to or ...
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Oscillator Clock Output C768 The ISAC-SX derives its system clocks from an external clock connected to XTAL1 (while XTAL2 is not connected) or from a 7.68 MHz crystal connected across XTAL1 and XTAL2. At pin C768 a buffered 7.68 ...
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Control of Layer-1 The layer-1 activation/ deactivation can be controlled by an internal state machine via the IOM-2 C/I0 channel or by software via the microcontroller interface directly. In the default state the internal layer-1 state machine of the ...
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State machines are the key to understanding the transceiver part of the ISAC-SX. They include all information relevant to the user and enable him to understand and predict the behaviour of the ISAC-SX. The state diagram notation is given in ...
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Leave for the state “F6 synchronized” after INFO 2 has been recognized on the S/T- interface. – Leave for the state “F7 activated” after INFO 4 has been recognized on the S/T- interface. – Leave for any unconditional state ...
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Pending Act. TIM RSY TIM i4 F5 Unsynchronized i0*TO1 Synchronized Lost Framing ...
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SSP SCP SSP TMA SCP TIM Test Mode Figure 39 State Transition Diagram of Unconditional Transitions (TE, LT-T) 3.5.1.2 States (TE, LT-T) F3 Pending Deactivation State after deactivation from the S/T interface by info 0. ...
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F4 Pending Activation The ISAC-SX transmits info 1 towards the network, waiting for info 2. F5 Unsynchronized Any signal except info detected on the S/T interface. F6 Synchronized The receiver has synchronized and detects info 2. Info ...
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C/I Codes (TE, LT-T) Command Activation Request with priority class 8 Activation Request with priority class 10 Activation Request Loop ARL Deactivation Indication Reset Timing Test mode SSP Test mode SCP Note: In the activated states (AI8, AI10 or ...
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Indication Deactivation Request from F6 Power up Activation request Activation request loop ARL Illegal Code Violation Activation indication loop Activation indication with priority class 8 Activation indication with priority class 10 Deactivation confirmation Data Sheet Abbr. Code Remark DR6 0101 ...
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Infos on S/T (TE, LT-T) Receive Infos on S/T (Downstream) Name info 0 info 2 info 4 info X Transmit Infos on S/T (Upstream) Name info 0 info 1 info 3 Test info 1 Test info 2 Data Sheet ...
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State Machine LT-S Mode 3.5.2.1 State Transition Diagram (LT-S) RST TIM RES Reset i0 * RES DC Any State DC RSY ARD G2 Lost Framing S ARD = AR or ARL ...
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States (LT-S) G1 deactivated The transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. The clocks are deactivated if MODE1-CFS is set to 1. Activation is ...
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Unconditional States Test mode - SSP Single alternating pulses are sent on the S/T-interface. Test mode - SCP Continuous alternating pulses are sent on the S/T-interface. 3.5.2.3 C/I Codes (LT-S) Command Abbr. Deactivation DR Request Reset RES Send Single Pulses ...
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Indication Abbr. Timing TIM Reset RES Receiver not RSY Synchronous Activation Request AR Illegal Code CVR Ciolation Activation Indication AI Deactivation DI Indication 3.5.2.4 Infos on S/T (LT-S) Receive Infos on S/T (Downstream) I0 INFO 0 detected I0 Level detected ...
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State Machine NT Mode 3.5.3.1 State Transition Diagram (NT) RST TIM RES DR Reset i0 * RES DC Any State AID RSY ARD i3*ARD G2 Lost Framing S/T i3*AID i2 i3 RSY DR ARD 2) AID RSY RSY G3 ...
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States (NT) G1 Deactivated The transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. The clocks are deactivated if the bit MODE1.CFS to 1. Activation is ...
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G4 wait for DR Final state after a deactivation request. The transceiver remains in this state until DC is issued. Unconditional States Test Mode SSP Send Single Pulses Test Mode SCP Send ...
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Command Abbr. Activation Indication AI Activation Indication AIL Loop Deactivation DC Confirmation Indication Abbr. Timing TIM Reset RES Receiver not RSY Synchronous Activation Request AR Illegal Code CVR Ciolation Activation Indication AI Deactivation DI Indication Data Sheet Description of Functional ...
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Command/ Indicate Channel Codes (C/I0) - Overview The table below presents all defined C/I0 codes. A command needs to be applied continuously until the desired action has been initiated. Indications are strictly state orientated. Refer to the state diagrams ...
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Control Procedures 3.6.1 Example of Activation/Deactivation An example of an activation/deactivation of the S/T interface initiated by the terminal with the time relationships mentioned in the previous chapters is shown in Figure 42 Example of Activation/Deactivation Initiated by the ...
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Activation initiated by the Terminal INFO 1 has to be transmitted as long as INFO 0 is received. INFO 0 has to be transmitted thereafter as long as no valid INFO (INFO 2 or INFO 4) is received. After ...
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Activation initiated by the Network Termination NT INFO 0 has to be transmitted as long as no valid INFO (INFO 2 or INFO 4) is received. After reception of INFO 2 or INFO 4 transmission of INFO 3 has ...
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IOM-2 Interface The ISAC-SX supports the IOM-2 interface in linecard mode and in terminal mode with single clock and double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. The rising edge of FSC indicates ...
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IOM-2 Frame Structure (TE Mode) The frame structure on the IOM-2 data ports (DU,DD master device in IOM-2 terminal mode is shown in Figure 45 IOM -2 Frame Structure in Terminal Mode The frame is composed of three ...
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IOM-2 Frame Structure (LT-S, LT-T Modes) This mode is used in LT-S and LT-T applications. The frame is a multiplex eight IOM-2 channels (DCL = 4096 kHz, described above. The reset value for assignment to one of ...
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IOM-2 Handler The IOM-2 handler offers a great flexibility for handling the data transfer between the different functional units of the ISAC-SX and voice/data devices connected to the IOM- 2 interface. Additionally it provides a microcontroller access to all ...
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IOM_CR IOM-2 Handler EN_BCL, CLKM, DIS_OD, DIS_IOM, SDS1/2_CR SDS1/2_CR Controller Data Access (CDA) CDA Registers CDA Control ( DPS, TSS, EN_TBM, SWAP, CDA10 Control EN_I1/0, EN_O1/0, CDA11 MCDAxy, STIxy, Monitor Data CDA20 STOVxy, ACKxy ) (DPS, CS2-0, CDA21 EN_MON) CDA_TSDPxy ...
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Controller Data Access (CDA) With its four controller data access registers (CDA10, CDA11, CDA20, CDA21) the ISAC-SX IOM-2 handler provides a very flexible solution for the host access IOM-2 time slots. The functional unit CDA ...
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Data”. Besides that none of the IOM timeslots must be assigned more than one input and output of any functional unit. . TSa 0 1 Enable output input * (EN_O0) (EN_I0) CDAx0 1 0 TSa x ...
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Looping Data TSa CDA10 .TSS: TSa .DPS ’0’ .SWAP b) Shifting Data TSa CDA10 .TSS: TSa .DPS ’0’ .SWAP c) Switching Data TSa CDA10 .TSS: TSa .DPS ’0’ .SWAP Figure 49 Examples for Data Access via CDAxy Registers a) ...
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Figure 50 shows the timing of looping TSa from 0...11) via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD 0...11 FSC ...
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Shifting TSa TSb within one frame (a,b: 0...11 and b a+2) FSC DU TSa (DD) CDAxy b) Shifting TSa TSb in the next frame (a,b: 0...11 and ( <a) FSC DU TSa (DD) CDAxy *) ...
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Monitoring Data Figure 52 gives an example for monitoring of two IOM-2 time slots each simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to time slots with ...
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Synchronous Transfer While looping, shifting and switching the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). The microcontroller access to the CDAxy registers can be synchronized by means of ...
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Table 10 Examples for Synchronous Transfer Interrupts Enabled Interrupts (Register MSTI) STI STOV ...
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Figure 54 shows some examples based on the timeslot structure. Figure a) shows at which point in time an STI and STOV interrrupt is generated for a specific timeslot. Figure b) is identical to example 3 above, figure c) corresponds ...
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Serial Data Strobe Signal and Strobed Data Clock For time slot oriented standard devices connected to the IOM-2 interface the ISAC-SX provides two independent data strobe signals SDS1 and SDS2. Instead of a data strobe signal a strobed IOM-2 ...
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FSC DD, TS0 TS1 SDS1,2 (Example1) SDS1,2 (Example2) SDS1,2 (Example3) Example 1: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 2: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 3: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 For all examples SDS_CONF.SDS1/2_BCL must be set to “0”. Figure ...
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Strobed IOM-2 Bit Clock The strobed IOM-2 bit clock is active during the programmed window. Outside the programmed window a ’0’ is driven. Two examples are shown in FSC DD, TS0 TS1 SDS1 (Example1) SDS1 (Example2) Setting ...
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IOM-2 Monitor Channel The IOM-2 MONITOR channel (see MONITOR channel between a master mode device and a slave mode device. The MONTIOR channel data can be controlled by the bits in the MONITOR control register (MON_CR). For the transmission ...
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As a slave device the transceiver part of the ISAC-SX is programmed and controlled from a master device on IOM-2 (e.g. ISAR34 PSB 7115). This is used in applications where no microcontroller is connected directly to the ISAC-SX in ...
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P µ MIE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 MDA Int. MOX = DATA2 MDA Int. MXC = 0 MAC = 0 Figure 58 MONITOR Channel Protocol (IOM-2) Data Sheet ...
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Before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by a ’0’ in the MONITOR Channel Active MAC status bit. After having written the ...
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A pair of MX and MR in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission. • A start of a transmission is initiated by the transmitter by setting the ...
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MX/MR Treatment in Error Case In the master mode the MX/MR bits are under control of the microcontroller through MXC or MRC, respectively. An abort is indicated by an MAB interrupt or MER interrupt, respectively. In the slave mode the ...
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IOM -2 Frame No (DU (DD) 0 Figure 61 Monitor Channel, Normal End of Transmission 3.7.3.3 MONITOR Channel Programming as a Master Device As a master device the ISAC-SX can program and control other devices ...
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MONITOR Channel Programming as a Slave Device In applications without direct host controller connection the ISAC-SX must operate in the MONITOR slave mode which can be selected by pinstrapping the microcontroller interface pins according transceiver part of the ISAC-SX ...
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Programming Sequence The programming sequence is characterized by a ’1’ being sent in the lower nibble of the received address code. The data structure after this first byte and the principle of a read/ write access to a register is ...
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MONITOR Interrupt Logic Figure 62 shows the MONITOR interrupt structure of the ISAC-SX. The MONITOR Data Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable (MRE) and MR bit Control (MRC). The MONITOR channel End of ...
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C/I Channel Handling The Command/Indication channel carries real-time status information between the ISAC-SX and another device connected to the IOM-2 interface. 1) One C/I channel (called C/I0) conveys the commands and indications between the layer-1 and the layer-2 parts ...
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The CIR0 is buffered with a FIFO size of two second code change occurs in the received C/I channel 0 before the first one has been read, immediately after reading of CIR0 a new interrupt will be generated ...
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D-Channel Access Control D-channel access control is defined to guarantee all connected TEs and HDLC controllers a fair chance to transmit data in the D-channel. Collisions are possible • on the IOM-2 interface if there is more than one ...
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C/I channel the ISAC-SX itself (transmission of an HDLC frame in the D-channel). A software access request to the bus is effected by setting the BAC bit (CIX0 register) to ’1’. ...
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S-Bus Priority Mechanism for D-Channel The S-bus access procedure specified in ITU I.430 was defined to organize D-channel access with multiple TEs connected to a single S-bus (see To implement collision detection the D (channel) and E (echo) bits ...
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A TE may start transmission of a layer-2 frame first when a certain number of consecutive 1s has been received on the echo channel. This number is fixed priority class 1 and priority class ...
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D-channel data on the upstream D-bits low priority level (priority 10 consecutive ONEs are required. The priority class (priority 8 or priority 10) ...
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The upstream device can stop all D-channel sources by setting the A/B-bit to 0. The S/ G bit is not evaluated in this mode. The configuration settings of the ISAC-SX in intelligent NT applications are summarized in Table 13. Table ...
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NT D-Channel Controller Transmits Upstream In the initial state (’Ready’ state) neither the local D-channel sources nor any of the terminals connected to the S-bus transmit in the D-channel. The ISAC-SX S-transceiver thus receives BAC = “1” (IOM-2 DU ...
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Terminal Transmits D-Channel Data Upstream The initial state is identical to that described in the last paragraph. When one of the connected S-bus terminals needs to transmit in the D-channel, access is established according to the following procedure: • ...
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Activation/Deactivation of IOM-2 Interface The IOM-2 interface can be switched off in the inactive state, reducing power consumption to a minimum. In this deactivated state is FSC = ’1’, DCL and BCL = ’0’ and the data lines are ...
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DCL is activated such that its first rising edge occurs with the beginning of the bit following the C/I (C/I0) channel. After the clocks have been enabled this is indicated by the PU code in the C/I channel and, consequently, ...
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Asynchronous Awake (LT-S, NT, Int. NT mode) The transceiver is in power down mode (deactivated state) and MODE1.CFS=1 (TR_CONF0.LDD is don’t care in this case). Due to any signal on the line the level detect circuit will asynchronously pull the ...
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Auxiliary Interface 3.8.1 Mode Dependent Functions The AUX interface provides various functions, which depend on the operation mode (TE, LT-T, LT- Intelligent NT mode) selected by pins MODE0 and MODE1/EAW (see Table 14). After reset the pins ...
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INT0, INT1 In all modes two pins can be used as programmable I/O with optional interrupt input capability (default after reset, i.e. both interrupts masked). The INT0/1 pins are general input or output pins like AUX0-5 (see description above). In ...
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CH0, CH1, CH2 In linecard mode one FSC frame is a multiplex eight IOM-2 channels, each of them consisting of B1-, B2-, MONITOR-, D- and C/I-channel and MR- and MX-bits LT-T and LT-S mode one ...
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HDLC Controllers The ISAC-SX contains two HDLC controllers. The first one is used for the layer-2 functions of the D- channel protocol (LAPD), the second one provides B-channel access with reduced FIFO thresholds which can be used for firmware ...
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Message Transfer Modes The HDLC controllers can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus the receive data flow and the address recognition features can be ...
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Transparent mode 0 (MDS2-0 = ’110’). Characteristics: no address recognition Every received frame is stored in RFIFOx (first byte after opening flag to CRC field). Additional information can be read from RSTAx. Transparent mode 1 (MDS2-0 = ’111’). Characteristics: SAPI ...
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Data Reception 3.9.2.1 Structure and Control of the Receive FIFO The cyclic receive FIFO buffers with a length of 64 byte for D-channel and 128 byte for B-channel have variable FIFO block sizes (thresholds) of • ...
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The following description of the receive FIFO operation is illustrated in RFIFOx block size (threshold and 32 bytes. The RFIFOx requests service from the microcontroller by setting a bit in the ISTAx register, which causes an interrupt (RPF, ...
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RAM EXMx.RFBS=11 so after the first 4 bytes of a new frame have been stored in the fifo an receive pool full interrupt ISTAx.RPF is set. HDLC Receiver µP RAM HDLC Receiver RSTA The HDLC receiver has written further data ...
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Possible Error Conditions during Reception of Frames If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow (RDO) byte in the RSTAx byte will be set complete frame is lost, i.e. ...
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case of RME the last byte in RFIFO contains * the receive status information RSTA Figure 72 Data Reception Procedures Data Sheet Description of Functional Blocks START Receive Y Message End RME ? N Receive Pool Full ...
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Figure 73 gives an example of an interrupt controlled reception sequence, supposed that a long frame (68 byte) followed by two short frames (12 byte each) are received. The FIFO threshold (block size) is set to 32 byte in this ...
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Receive Frame Structure The management of the received HDLC frames as affected by the different operating modes (see Chapter 3.9.1) is shown in MDS2 MDS1 MDS0 MODE Non Auto/ Non Auto ...
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The ISAC-SX indicates to the host that a new data block can be read from the RFIFOx by means of an RPF interrupt (see previous chapter). User data is stored in the RFIFOx and information about the received frame is ...
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Data Transmission 3.9.3.1 Structure and Control of the Transmit FIFO The cyclic transmit FIFO buffers with a length of 64 byte for D-channel and 128 byte for B-channel have FIFO block sizes (thresholds) of • bytes ...
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XRES (Transmitter Reset) command, resetting the HDLC transmitter and clearing the transmit FIFO of any data. After an XRES command the transmitter always sends an abort sequence, i.e. this command can be used to abort a transmission. Pending interrupt ...
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XPR interrupt. However, the threshold can only be changed for D- channel. The maximum reaction time is (XFIFOx size - XFBS) / data transmission rate max With a selected block size of 16 bytes ...
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Command XTF Figure 75 Data Transmission Procedure Data Sheet Description of Functional Blocks START Transmit N Pool Ready XPR ? Y Write one data block to XFIFO End of N Message ? Y Command XTF+XME End 150 PEB 3086 PEF ...
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The following description gives an example for the transmission byte frame with a selected block size of 32 byte: • The host writes 32 bytes to the XFIFOx, issues an XTF command and waits for an XPR ...
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Transmit Frame Structure The transmission of transparent frames (XTF command) is shown in For transparent frames, the whole frame including address and control field must be written to the XFIFOx. The host configures whether the CRC is generated and ...
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Extended Transparent Mode This non-HDLC mode is selected by setting MODE2...0 to ’100’. In extended transparent mode fully transparent data transmission/reception without HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/check, bitstuffing mechanism. This allows user specific protocol ...
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HDLC Controller Interrupts The cause of an interrupt related to the HDLC controllers is indicated in the ISTA register by the ICD bit for D-channel and ICB for B-channel. These bits point to the different interrupt sources of the ...
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Test Functions The ISAC-SX provides test and diagnostic functions for the S-interface, the D-channel and each of the two B-channels: • Digital loop via TLP (Test Loop, TMD and TMB registers) command bit The TX path of layer 2 ...
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S interface LT-T mode Test loop 3 is activated with the C/I channel command Activate Request Loop (ARL interface is not required since INFO3 is looped back internally ...
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Detailed Register Description The register mapping of the ISAC-SX is shown in FFh 80h 70h 60h 40h 30h 00h Figure 80 Register Mapping of the ISAC-SX The register address range from 00 and the C/I-channel handler. The register set ...
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The address range from 40 timeslot and data port selection (TSDP) and the control registers (CR) for the transceiver data (TR), Monitor data (MON), HDLC/CI data (HCI) and controller access data (CDA), serial data strobe signal (SDS), IOM interface (IOM) ...
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D-channel HDLC, C/I-channel Handler Name RFIFOD XFIFOD ISTAD RME RPF MASKD RME RPF STARD XDOV XFW CMDRD RMC RRES MODED MDS2 MDS1 MDS0 EXMD1 XFBS RFBS TIMR1 CNT SAP1 SAP2 RBCLD RBC7 RBCHD 0 0 TEI1 TEI2 ...
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CIR1 CIX1 Transceiver, Auxiliary Interface NAME TR_ DIS_ BUS CONF0 TR TR_ 0 RPLL_ CONF1 ADJ TR_ DIS_ PDS CONF2 TX TR_STA RINF TR_CMD XINF SQRR1 MSYN MFEN SQXR1 0 MFEN SQRR2 SQR21SQR22SQR23SQR24SQR31SQR32SQR33 SQR34 SQXR2 SQX21SQX22SQX23SQX24SQX31SQX32SQX33 SQX34 ...
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Transceiver, Auxiliary Interface NAME ACFG2 A7SEL A5SEL FBS A4SEL ACL AOE OE7 OE6 ARX AR7 AR6 ATX AT7 AT6 IOM Handler (Timeslot , Data Port Selection, CDA Data and CDA Control Register) Name 7 6 CDA10 Controller ...
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TR_ DPS 0 TSDP_ BC1 TR_ DPS 0 TSDP_ BC2 CDA1_ CDA2_ IOM Handler (Control Registers, Synchronous Transfer Interrupt Control), MONITOR Handler Name 7 6 TR_CR EN_ EN_ D B2R (CI_CS=0) TRC_CR 0 0 ...
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SDS2_CR ENS_ ENS_ TSS TSS+1 IOM_CR SPU DIS_ AW STI STOV STOV 21 20 ASTI 0 0 MSTI STOV STOV 21 20 SDS_ 0 0 CONF MCDA MCDA21 MOR MOX MOSR MDR MER MOCR MRE MRC MSTA 0 0 MCONF ...
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Interrupt, General Configuration Registers NAME MODE1 0 0 MODE2 SRES RES_ RES_ CI BCH TIMR2 TMD 0 Data Sheet WTC1 WTC2 CFS RSS2 RSS1 0 0 INT_ 0 ...
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B-channel HDLC Control Registers Name ISTAB RME RPF MASKB RME RPF STARB XDOV XFW CMDRB RMC RRES MODEB MDS2 MDS1 MDS0 EXMB 1 1 RAH1 RAH2 RBCLB RBC7 RBCHB 0 0 RAL1 RAL2 RSTAB VFR RDO TMB ...
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D-channel HDLC Control and C/I Registers 4.1.1 RFIFOD - Receive FIFO D-Channel 7 RFIFOD A read access to any address within the range 00h-1Fh gives access to the “current” FIFO location selected by an internal pointer which is automatically ...
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ISTAD - Interrupt Status Register D-Channel Value after reset ISTAD RME RPF RME ... Receive Message End One complete frame of length less than or equal to the defined block size (EXMD1.RFBS) or the last part ...
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If an XMR interrupt occurs the transmit FIFO is locked until the XMR interrupt is read by the host (interrupt cannot be read if masked in MASKD). XDU ... Transmit Data Underrun The current transmission of a frame is aborted ...
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STARD - Status Register D-Channel Value after reset STARD XDOV XFW XDOV ... Transmit Data Overflow More than bytes (according to selected block size) have been written to the XFIFOD, i.e. data has ...
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CMDRD - Command Register D-channel Value after reset CMDRD RMC RRES RMC ... Receive Message Complete Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By setting this bit, the microcontroller confirms that ...
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XPR in ISTAD). During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing mechanism is done automatically. 4.1.7 MODED - Mode Register Value after reset MODED MDS2 MDS1 MDS0 MDS2-0 ... Mode Select Determines the ...
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TEIG = fixed value FF Two different methods of the high byte and/or low byte address comparison can be selected by setting SAP1.MHA and/or SAP2.MLA. RAC ... Receiver Active The D-channel HDLC ...
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RFBS … Receive FIFO Block Size RFBS Block Size Receive FIFO Bit 6 Bit5 byte byte byte byte Note: A change of RFBS will take effect after a ...
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TIMR1 - Timer 1 Register Value after reset TIMR1 CNT CNT ... Timer Counter CNT together with VALUE determines the time period T after which a AUXI.TIN1 interrupt will be generated: CNT=0...6:T = CNT x 2.048 ...
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SAP2 - SAPI2 Register Value after reset SAP2 SAPI2 ... SAPI2 value Value of the second programmable Service Access Point Identifier (SAPI) according to the ISDN LAPD-protocol. MLA... Mask Low Address 0 …The TEI address of ...
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RBCHD - Receive Frame Byte Count High D-Channel Value after reset RBCHD ... Overflow A ’1’ in this bit position indicates a message longer than (2 RBC8-11 ... Receive Byte Count Four ...
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TEI2 - TEI2 Register Value after reset TEI2 TEI2 ... Terminal Endpoint Identifier In all message transfer modes except in transparent modes 0, 1 and extended transparent mode, TEI2 is used by the ISAC-SX for address ...
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RDO ... Receive Data Overflow If RDO=1, at least one byte of the frame has been lost, because it could not be stored in RFIFOD. As opposed to the ISTAD.RFO an RDO indicates that the beginning of a frame has ...
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TMD -Test Mode Register D-Channel Value after reset TMD 0 0 For general information please refer to TLP ... Test Loop The TX path of layer-2 is internally connected with the RX path of layer-2. Data ...
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S/G ... Stop/Go Bit Monitoring Indicates the availability of the upstream D-channel on the S/T interface. 1: Stop 0: Go BAS ... Bus Access Status Indicates the state of the TIC-bus: 0: the ISAC-SX itself occupies the D- and C/I-channel ...
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If this bit is set, the ISAC-SX will try to access the TIC-bus to occupy the C/I-channel even if no D-channel frame has to be transmitted. It should be reset when the access has been completed to grant a similar ...
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Transceiver Registers 4.2.1 TR_CONF0 - Transceiver Configuration Register 0 Value after reset TR_ DIS_ BUS CONF0 TR DIS_TR ... Disable Transceiver Setting DIS_TR to “1” disables the transceiver. In order to reenable the transceiver again, a ...
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For general information please refer to LDD ... Level Detection Discard 0: Automatic clock generation after detection of any signal on the line in power down state 1: No clock generation after detection of any signal on the line in ...
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TR_CONF2 - Transmitter Configuration Register 2 Value after reset TR_ DIS_ PDS CONF2 TX DIS_TX ... Disable Line Driver 0: Transmitter is enabled 1: Transmitter is disabled For general information please refer to PDS ... Phase ...
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Note: Outside the active window of SGO (defined in SGD) the level on pin SGO remains in the “stop”-state depending on the selected polarity (SGP), i.e. SGO=1 (if SGP=0) or SGO=0 (if SGP=1) outside the active window. 4.2.4 TR_STA - ...
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TR_CMD - Transceiver Command Register Value after reset TR_ XINF CMD Important: This register is only writable if the Layer 1 state machine of the ISAC-SX is disabled (TR_CONF0.L1SW = 1)! With the ISAC-SX layer 1 ...
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LP_A ... Loop Analog The setting of this bit corresponds to the C/I command ARL. 0: Analog loop is open 1: Analog loop is closed internally or externally according to the EXLP bit in the TR_CONF0 register For general information ...
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SQXR1- S/Q-Channel TX Register 1 Value after reset SQXR1 0 MFEN MFEN ... Multiframe Enable Used to enable or disable the multiframe structure (see 0: S/T multiframe is disabled 1: S/T multiframe is enabled Readback value ...
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SQXR2 - S/Q-Channel TX Register 2 Value after reset SQXR2 SQX21 SQX22 SQX23 SQX24 SQX31 SQX32 SQX33 SQX34 SQX21-24, SQX31-34... Transmitted S Bits (NT mode only) Transmitted S bits in frames and 17 ...
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ISTATR - Interrupt Status Register Transceiver Value after reset ISTATR x x For all interrupts in the ISTATR register the following logical states are defined: 0: Interrupt is not acitvated 1: Interrupt is acitvated x ... ...
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MASKTR - Mask Transceiver Interrupt Value after reset MASKTR 1 1 The transceiver interrupts LD, RIC, SQC and SQW are enabled (0) or disabled (1). 4.2.14 TR_MODE - Transceiver Mode Register 1 Value after reset: 000000xx ...
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Auxiliary Interface Registers 4.3.1 ACFG1 - Auxiliary Configuration Register 1 Value after reset ACFG1 OD7 OD6 For general information please refer to OD7-0 ... Output Driver Select for AUX7 - AUX0 0: output is open drain ...
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A5SEL ... AUX5 Function Select 0: pin AUX5 provides normal I/O functionality. 1: pin AUX5 provides an FSC or BCL signal output (FBOUT) which is selected in ACFG2.FBS. Bit AOE.OE5 is don’t care, the output characteristic (push pull or open ...
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Note: An interrupt is only generated if the corresponding mask bit in AUXM is reset. This configuration is only valid if the corresponding output enable bit in AOE is disabled. For general information please refer to 4.3.3 AOE - Auxiliary ...
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ARX - Auxiliary Interface Receive Register Value after reset: (not defined) 7 ARX AR7 AR6 AR7-0 ... Auxiliary Receive The value of AR7-0 always reflects the level at pin AUX7-0 at the time when ARX is read by the ...
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IOM-2 and MONITOR Handler 4.4.1 CDAxy - Controller Data Access Register xy 7 CDAxy Data registers CDAxy which can be accessed from the controller. Register Register Address CDA10 40 H CDA11 41 H CDA20 42 H CDA21 43 H ...
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XXX_TSDPxy - Time Slot and Data Port Selection for CHxy 7 XXX_ DPS 0 TSDPxy Register Register Address CDA_TSDP10 44 H CDA_TSDP11 45 H CDA_TSDP20 46 H CDA_TSDP21 47 H BCH_TSDP_BC1 48 H BCH_TSDP_BC2 49 H TR_TSDP_BC1 4C H ...
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DPS ... Data Port Selection 0:The data channel xy of the functional unit XXX is output on DD. The data channel xy of the functional unit XXX is input from DU. 1:The data channel xy of the functional unit XXX ...
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EN_I1, EN_I0 ... Enable Input CDAx0, CDAx1 0: The input of the CDAx0, CDAx1 register is disabled 1: The input of the CDAx0, CDAx1 register is enabled EN_O1, EN_O0 ... Enable Output CDAx0, CDAx1 0: The output of the CDAx0, ...
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Note: Receive data corresponds to downstream direction, and transmit data corresponds to upstream direction. CS2-0 ... Channel Select for Transceiver D-channel This register is used to select one of eight IOM channels to which the transceiver D- channel data is ...