PXB4240 Siemens Semiconductor Group, PXB4240 Datasheet
PXB4240
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PXB4240 Summary of contents
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ICs for Communications Synchronous Digital Hierarchy Transceiver SDHT PXB 4240 Version 1.2 Preliminary Data Sheet 10.96 T4240-XV12-P1-7600 ...
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Edition 10.96 This edition was realized using the software system FrameMaker . Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 03.95. All Rights Reserved. Attention please! As far as patents or other rights ...
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PXB 4240 Revision History: Previous Version: Preliminary Data Sheet Version 1.1 Page Page Subjects (changes since last revision) (in Version (in Version 1.1) 1.2) page 59 page 68 Change of SDHT version value from the SDHT ...
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Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview The Synchronous Digital Hierarchy Transceiver (SDHT member of the Siemens ATM chip set. SDHT is a complete Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) framer for 155–MBit/s ATM implementations including Transmission Convergence (TC) Sublayer processing for ATM ...
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The SDHT is offered in a Metric Quad Flat Pack package with 160 pins. It operates at a voltage of 3.3V. The power dissipation is less than 0.7 W. The chip includes a power down mode. Semiconductor Group 8 PXB ...
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Synchronous Digital Hierarchy Transceiver SDHT Version 1.1 1.1 Features • 155 Mbit/s transmission rate • 2 operating modes: ATM and VC–4 • Single–port UTOPIA Interface • 16–bit generic Microprocessor Interface • Serial interface to optical transceiver • Transmit Functions - ...
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ATM cell payload descrambling - HEC evaluation: correction or detection and mode switchover according to ITU–T Recommendation [I.432]. - Counting of cell header corrections, discarded cells due to errors, discarded unassigned/idle cells and cells output to the UTOPIA interface ...
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Logic Symbol Figure 1 SDHT Logic Symbol Semiconductor Group 11 PXB 4240 10.96 ...
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Pin Configuration (top view) Figure 2 SDHT Pin Configuration Semiconductor Group 12 PXB 4240 10.96 ...
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Pin Definitions and Functions • Symbols with an * attached indicate active low signals 1) • Pins with a attached are connected with an internal pull up resistor 2) • Pins with a attached are connected with an internal ...
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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol 9 INT* 27–23 , DAT(15)–(11), 21–16 , DAT(10)–(5), 14–10 DAT(4)–(0) 2) 36–29 ADR(7)–( SMXD 39 Rsvd UTOPIA Interface 41–44 Rsvd 122 RxClav 123 RxSOC 2) RxEnb* 125 Semiconductor ...
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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol 126 Rsvd 127–129, RxData 7–5, 131–135 RxData 4–0 2) 136 AtmClk 137 Rsvd 147– TxData 7–5, 2) 145 , TxData 4–0 143– 2) 139 2) 148 TxEnb* 2) 150 TxSOC ...
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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol 53 TxAIS_N 54 TxAIS_P 55 TxD_N 56 TxD_P 57 TXC_N 58 TXC_P 2) 63 TRI_STM 2) 64 TRI_AIS 66 TxC0_N 67 TxC0_P 68 TXC1_N 69 TXC1_P 71 RxD_N 72 RxD_P ...
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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol 2) 45 XATMLOOP 2) 46 SXBMOD 2) 47 SIEIN 2) 48 SIAUS 2) 49 SILD 50 SLDON 51 SSERST TSTMRFL 77 PWRDWN 1) 78 TRI_ATM 1) 85 SIR1* ...
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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol 2) 86 SIR2 1) 87 SIRP SIUB SITE1 SRINH TAR1 RES 95 SAISOUT* 155 SLPOUT 2) 156 SLPINT* 1) 157 ...
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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol 1) 160 SAISIN* Low-Rate Serial Interface 100 TEOW 101 TEOWB 103 TSOW 104 TSOWB 105 DEOW1 106 DEOW2 2) 108 DSOW1 2) 109 DSOW2 110 TED1 111 TED2 113 TSD1 ...
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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol 114 TSD2 115 DED1 116 DED2 2) 117 DSD1 2) 119 DSD2 JTAG Boundary Scan 1) 79 TMS 1) 80 TDI 81 TDO 1) 82 TCK Miscellaneous 2) 96 TESTM ...
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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol 154 Rsvd Power 3, 15, 22, VSS 38, 59, 65,75, 84, 93, 102,112, 124,138, 149 8, 28, 52, VDD 70, 90, 107,118, 130,144, 152 60 OBIAS 61 IBIAS 62 ext. ...
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System Integration The Siemens ATM chip set includes five chips which can be used in a variety of Adapter and Switch applications. Table 2 ATM Devices Available from Siemens ASM ATM Switching Matrix, PXB 4310 ASP-up ATM Switch Preprocessor ...
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SDHT can also be used in a Line Card for an ATM Switch as shown in Figure 4. In this application, the SDHT is connected via the UTOPIA interface to the ASP chips (PXB43201/2). Figure 4 SDH/SONET Line Card Example ...
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Functional Description The SDHT performs five major functions: Cell–Rate Decoupling, HEC Header Generation and Verification, Cell Delineation, Transmission Frame Generation and Adaptation, and Receive Frame Recovery. See Figure 5. The combination of these functions achieves the task of framing ...
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Functional Block Diagram Figure 5 SDHT Block Diagram Semiconductor Group 25 PXB 4240 10.96 ...
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Transmit Frame Generation and Adaptation The SDHT chip generates and adapts frames for transmission on the physical medium in several steps. See Figure 5. In simple terms, the SDHT receives ATM cells from the ATM Layer via the UTOPIA ...
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Figure 6 Virtual Container–4 Semiconductor Group 27 PXB 4240 10.96 ...
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Figure 7 STM-1 Frame Structure Note: The parameters which are different between STM–1 and STS–3c are all separately programmable by microprocessor or at start up. Two items concerning STS–3c are worth noting: The STS–3c "Path RDI" (former "Path Yellow") and ...
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M–SOH) is built before scrambling, but does not include the R-SOH (but the pointer is included). Another parity byte (B3, in the POH) is used for path related bit error monitoring and thus is calculated over one VC–4. Figure 8 ...
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Table 3 Handling of SOH for SDH and TOH for SONET Bytes (cont’d) SOH/ Transmitter Setting TOH Byte(s) D1–D3 µP programmable or serial input DCC1 H1,H2 #1 AU–4 pointer, P–AIS;ss bits µP programmable H1, (9B,FF); dd bits µP ...
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Table 3 Handling of SOH for SDH and TOH for SONET Bytes (cont’d) SOH/ Transmitter Setting TOH Byte(s) Z1#1(S1) µP programmable Z1#2–#3 µP programmable Z2#1 Mode 'LPINT must equal 1 Z2#2 µP programmable Z2#3(M1) '1bbb bbbb''bbbbbbb': number of detected B2 ...
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Table 4 Handling of POH Bytes POH Byte Transmitter Setting BIP–8 (over VC–4) C2 13(hex), except mode 'UEQ 'bbbb f111''bbbb': number of detected B3 errors (P–FEBE) for feed back'f': P–FERF signalling H4 µP programmable or ...
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Figure 9 Structure of the AU-4 (or payload) Pointer The Pointer value is contained in H1#1, bits 7 and 8, and H2#1. The pointer value contains the relative starting position of the user data within the virtual container from the ...
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Figure 10 State Diagram of Pointer Evaluation, Normal Semiconductor Group 34 PXB 4240 10.96 ...
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Figure 11 State Diagram of Pointer Evaluation, with Concatenation Indication Note 1: This transition NORM -> LOP can occur along with other NORM -> NORM transitions in H1, H2 (Incr_ind, Decr_ind etc.). Priority is given to the transition to LOP ...
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Decr_ind Inv_point Evaluation Only for H1#2 and H1#3, H2#2 and H2#3: Conc_ind The dd bits are different for SONET/ SDH: see text above. Inv_point_conc 1 (H1#2; H2#2) Inv_point_conc 2 (H1#3; H2#3) Evaluation for H1#1–3 or H2#1–3: AIS_ind_conc norm_point_conc If SDHT ...
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ATM payloads are not descrambled. The ATM cell headers are neither scrambled nor do they change the internal scrambler state ATM data is present to be transmitted, this may be signalled by UEQ (unequipped). This has to be ...
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SDHT chip can be programmed using the Config1L Register bit LOFUS to be compatible with the desired protocol. For the realization of the 3-ms delay, no integration timer is used, i.e. whenever OOF goes inactive, the timer is ...
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Cells with multiple errored headers are discarded. 2.3.4 Cell-Rate Decoupling Cell Rate Decoupling is performed implicitely by elimination of any idle/unassigned ...
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After a successful end of this acquiring algorithm, the bit PTACK in the interrupt status register 2L becomes set. Now, the acquired path trace can be read from the Rx RAM. If ACQPT is reset to '0' before the acquiring ...
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Figure 12 Flow of Path Trace Acquiring Algorithm Semiconductor Group 41 PXB 4240 10.96 ...
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Figure 13 State Diagram of Path Trace Acquiring Algorithm 2.4.3 Detection of a Signal Label Mismatch If the received C–2 byte (path termination only) is different from 13 hex (indication for ATM payload) or from 01 hex (indication for non ...
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Figure 14 Signal Label Mismatch Detection 2.4.4 Section Termination Mode Standard operation of the SDHT is in path termination mode. To use the SDHT in multiplexer section termination mode instead, the µP or SPATH pin must map VC–4 cells into ...
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Latched status and latched release status register - 5 ms: Counters and detection circuit of excessive bit error rates based on B1, B2 UTOPIA frequency counter Each time a one second interval is finished, and the µP readable ...
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SIVCA, SISTA and SISTD are gated with 607,5 µs. The SISTD may appear sporadically, when the SDHT has lost its STM–1 synchronization. The test mode bits SSYATMT, SLOPT, SIXBT, SXCB2T, SXCB3T may be set to ...
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Interface Descriptions The SDHT chip contains five interfaces: Payload/UTOPIA, Microprocessor, Line, Control, and JTAG Boundary Scan. A detailed description of each interface follows. 3.1 Payload/UTOPIA Interface Payload data is expected at the payload interface, which can be configured for ...
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Figure 15 UTOPIA Reference Configuration 3.1.1 UTOPIA Hardware Functions 3.1.1.1 Clocking As PHY chips are defined for various transmission speeds, The ATM Forum specified the use of an ATM Layer Master Clock, making it responsible for clocking both transmit and ...
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The UTOPIA Interface of the SDHT is operated with a clock MHz, which is used by both receive and transmit interfaces. This clock is delivered from the ATM Layer and input at the ATMCLK pin. It ...
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The HEC Insertion for the Tx direction and the HEC correction are performed in the SDHT. This can be disabled by the mode bit ENHEC in the register Config1H (1: enabled; default). 3.1.1.3 Cell Counters Five on–chip, one–second interval counters ...
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The signals of the UTOPIA transmit interface are: TxData (7–0 8–bit data bus. TxData(7) is the MSB. TxSOC, Transmit Start–of–Cell signal indicating the first octet of a cell set to one when the first ...
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Figure 17 TxClav Example #2 Figure 18 TxClav Example #3 Semiconductor Group 51 PXB 4240 10.96 ...
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Figure 19 TxClav Example #4 Figure 20 RxClav Example #1 Semiconductor Group 52 PXB 4240 10.96 ...
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Figure 21 RxClav Example #2 Figure 22 RxClav Example #3 3.1.3 UTOPIA (Rx) During Receiving Error Conditions When the received STM–1 signals error conditions leading to a P–AIS error condition, the internal cell delineation is reset to the HUNT state. ...
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UTOPIA block internally. Cells already contained in the Rx FIFO remain accessible. 3.1.4 Switching Between UTOPIA and VC-4 The Payload Interface is switched to UTOPIA mode by the bit ENUTOPIA in the Config1H Register (1: UTOPIA enabled; default ...
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A1 byte). For registers comprising more than one byte, the most significant byte is associated with the highest address. 3.2 Microprocessor Interface This is the universal, generic, 16–bit microprocessor interface which is used for all Siemens ATM chips except the ...
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Internal reading is triggered by the falling edge of ALE regardless of the state of RD* or CS*. For the timing of ALE vs. address lines, see Chapter 5. If the SMXD control pin is low or ...
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Clock switching is performed on 155 MHz level. The selected clock is also provided to the output TXC. See also chapter 3.5.3. Figure 23 SDH Clock Switching 3.3.1.3 No Boundary Scan Boundary scan is not implemented at the serial 155.52 ...
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SPATH pin, rather than by the mode bit SVCEN. 3.3.2 Low–Rate Serial Interfaces For special applications, the SDHT chip provides access to the STM–1 section overhead bytes shown in Table 8 via serial ...
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Table 9 SDHT Boundary Scan Table (cont’d) Boundary PIN-Nr. Scan Number 100 15 101 16 103 17 104 18 105 19 106 20 108 21 109 22 ...
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Table 9 SDHT Boundary Scan Table (cont’d) Boundary PIN-Nr. Scan Number 36 127 37 128 38 129 39 131 40 132 41 133 42 134 43 135 44 136 45 139 46 140 47 141 48 142 49 143 50 ...
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Table 9 SDHT Boundary Scan Table (cont’d) Boundary PIN-Nr. Scan Number ...
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Table 9 SDHT Boundary Scan Table (cont’d) Boundary PIN-Nr. Scan Number 3.5 Control Signal Interface This interface includes control pins for mode select, alarms, ...
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When the signal at SIEIN has changed to low, LOS is released immediately or, if the bit LOSUS (register config 1L) is set (US mode), after receipt of 2 valid framing patterns. Note: Using the SDHT in US mode, does ...
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STM–1 frame. Thus, short pulses at SAISIN* may or may not result in transmission of P–AIS. The output pin SAISOUT* (active low) is activated when at least one of the following conditions is detected: LOS (via SIEIN ...
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Figure 24 SDH Flow Chart for Loopback Applications Semiconductor Group 65 PXB 4240 10.96 ...
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Figure 25 Semiconductor Group 66 PXB 4240 10.96 ...
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SDH Loopback Applications 3.5.6 Chip Reset By driving the SERES pin to high level for at least one microsecond, the complete SDHT chip is reset. The pins SPATH, SLPINT and XSONET determine the default values of the mode and configuration ...
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Register Description 4.1 SDHT Register Summary The internal SDHT registers can be accessed bytewise or wordwise, where 1 word = 16 bits. Table 10 presents all the registers in summary form. Following sections provide detailed descriptions by type of ...
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Table 10 SDHT Register Summary (cont’d) Register(s) Address Range POH bytes "...s" J1 00H–0FH 80H H4 81H Z3 (F3) 86H Z4 (K3) 87H Z5 (N1) 88H POH bytes "...r" J1 10H–1FH B3 - ...
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Table 10 SDHT Register Summary (cont’d) Register(s) Address Range Test Mode 96H–97H Test Status 9CH–9DH UTOPIA (1 Sec.) E0H–F3H Monitoring RXHECCOR E0 - E2H RXHECDIS E4 - E6H RXIDLE E8 - EAH RXINFO EEH ATMRXCLK F0 - F1H ...
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SDHT Register Address Mapping Summary The next table shows the comprehensive address mapping of the SDHT registers. Table 11 Register Address Mapping Summary low order addr bits .0 J1s J1r D1s F1s D1r K1s ...
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Table 11 Register Address Mapping Summary (cont’d) low high order 4 address bits order addr bits .A J1s J1r D9s Z1# D9r (10) (10 J1s J1r Z2# (11) (11 J1s J1r ...
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Control Registers There are four types of Control Registers: Status, Mode, Configuration, and Test. Table 12 SDHT Status and Mode Bits Register MSB bit6 Interrupt SIVCA SISTA Status 1L Interrupt SLOP SSYATM Status 1H Interrupt PTACK SEUEQ Status 2L ...
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Status Registers and Interrupt Generation Table 12 gives an overview of the SDHT Status and Mode Register bits. Table 13 provides a descriptive summary of the individual bits. The names of some status bits correspond to the control inputs ...
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Table 13 SDHT Status Bit Descriptions (Grouped Bytewise) Name Description SIVCA HW failure in VC-4 assembler circuit SISTA HW failure in STM-1 assembler circuit SISTD HW failure in STM-1/VC-4 disassembler circuit SITAKT Clock failure; may cause SIVCA, SISTA, SISTD! SIAUS ...
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Table 13 SDHT Status Bit Descriptions (Grouped Bytewise) (cont’d) Name Description SIXB UTOPIA Interface fault SEFERF Receipt of S FERF [Generation: Figure 28] SERAI Receipt of P FERF (don´t care unless path termination point) [Generation: Figure 28] SIST Stuffing error ...
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Table 14 SDHT Mode Bit Descriptions (Grouped Bytewise) Name Default after HW Reset SSTEN 1 SVCEN Pin SPATH SATSCR Pin SPATH SSTSCR 1 SDC1 1 SDC2 1 SERSMP 0 SMRES 0 LPINT Must be programmed to 1 SLOOP 0 SUEQEN ...
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Table 15 Mode Register After a Hardware Reset SPATH Mode H L 1000 0000 H 1000 0000 A software reset works in a manner similar to a hardware reset, except that the bits of Mode and Config Registers are not ...
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Table 17 SDHT Configuration Bit Descriptions (Grouped Bytewise) Default after HW Reset for: Name of XSONET Config bit low C1US 1 LOFUS 1 LOSUS 1 LAISUS 1 K1K2US 1 PRAIUS 1 NUS 1 UNDEFUS 1 ENIDLE ATMPTR RAIINH LOCRAIINH ENHEC ...
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Table 17 SDHT Configuration Bit Descriptions (Grouped Bytewise) (cont’d) Default after HW Reset for: Name of XSONET Config bit low ATC Table 18 Configuration Registers After a Hardware Reset SXBMOD XSONET ...
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The test of SXCB2 has the side effect of generating bit errors which will be counted in the B2 errors second counter and activate signal degrade (status bit SSDB2, depending on the SD threshold). The test of SXCB3 has the ...
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Table 19 SDHT Test Mode Bit Descriptions (cont’d) Name of Default after config-bit any reset SXCB3T 0 ENERSTXB 1 ENSEROFF 0 ENERST 1 ENTXC1 0 LOOPINT 1 LOOPAIS 1 Z21GEN 1 Z21EVAL 1 4.6 Performance Monitoring and Alarm Handling 4.6.1 ...
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Reset the register ( zero to clear the internal counters and a potentially active signal degrade state; – Set Ns to its requested value; – Program the register ( the required values for M and ...
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Figure 26 Performance Monitoring Semiconductor Group 84 PXB 4240 10.96 ...
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Alarm Handling The alarm handling is shown in Figure 28. For special functions (e.g. loop) refer to Figure 27. Figure 27 Special OAM Functions Semiconductor Group 85 PXB 4240 10.96 ...
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Figure 28 Alarm Handling Note: Only Status Registers with preprocessing are shown Semiconductor Group 86 PXB 4240 10.96 ...
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Electrical Characteristics 5.1 Absolute Maximum Ratings Table 20 Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Voltage Input/Output (bidirectional) Voltage Ambient temperature under bias: (without forced cooling) Maximum Power consumption Storage temperature The SDHT shows the following electrical ...
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Table 21 DC Characteristics (cont’d) Symbol Parameter VOH Output HIGH voltage 2.4 V VOL Output LOW voltage IOH Output current at HIGH voltage IOL Output current at LOW voltage IIH Input current at HIGH voltage IIL Input current at LOW ...
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Line Interface DC characteristics Table 22 Line Interface DC characteristics Parameter Input high voltage Input low voltage Input differential voltage Output high voltage *) Output low voltage *) Output differential voltage *) *) Values are adjustable by bias resistor ...
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AC Characteristics 3.3 V ± All inputs are driven to V and to All outputs are measured at and at The AC testing input/output ...
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AC Characteristics of the Line Interface The timing of the serial STM-1 line interface is described in the following figure and table: Figure 30 Line interface timing diagram Table 24 Line interface timing characteristics Parameter RxD input data setup ...
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UTOPIA AC Values The timing requirements for UTOPIA receive and transmit directions for 33 MHz, 8-bit bus are given in the Tables 26 and 29. Table 25 displays the general conditions for UTOPIA timing. Table 25 General Conditions on ...
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Table 26 AC Characteristics of UTOPIA Interface (cont’d) Signal name Direction RxData[7–0] A<=P RxSOC RxEnb* A=>P RxClav A<=P The most criticial parameter in Table 26 is the hold time of 1 ns. This is outlined in Figure 31. The worst ...
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Figure 31 Timing Relationship for UTOPIA Signals Semiconductor Group 94 PXB 4240 10.96 ...
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AC Characteristics of JTAG Interface The timing of the JTAG interface is described in the following figure and table: Figure 32 JTAG interface timing diagram Table 27 JTAG interface timing characteristics Parameter Test clock period Test clock period low ...
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Microprocessor Timings The address timing is shown in Figure 33, and the data timings in Figures 34 and 30. The capacitive load should not exceed 100 pF at any output of the microprocessor interface. If the load is moderately ...
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Figure 34 SDHT Write CycleTiming (setup, hold, pulse width) The minimum inactive read cycle time ( inactive high) between two successive read operation should be greater than 60ns. Figure 35 SDHT Read Cycle Timing (CS ->RD setup; ...
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Packaging Outline The SDHT is packaged in a 160–pin plastic quad flat package. P-MQFP-160-1 (Plastic Metric Quad Flat Package) Figure 36 SDHT package (shown from side and from top). Sorts of Packing Package outlines for tubes, trays etc. are ...
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Appendices 7.1 SDH Versus SONET Terminology Table 28 Terminology Comparison for SDH and SONET SDH (ITU) STM-1 SOH = R-SOH + M-SOH MS-AIS, MS-FERF, MS-FEBE, P-FERF, P-FEBE AU-4 pointer VC-4, POH C-4 (= VC-4 without POH) The AU-4 pointer ...
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Table 29 References (cont’d) [ANSI-SDH] ANSI T1.105a-1991, “Digital Hierarchy —Supplement to Optical Interface Rates and Formats Specifications (SONET)”—Draft, May 7, 1991 [ANSI-ATM] ANSI T1E1.2/94-002R1, “Broadband ISDN and DS1/ATM User- Network Interfaces: Physical Layer Specification,” [TR_253] Bellcore TR-NWT-000253, "Synchronous Optical Network ...
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Table 30 Acronyms (cont’d) FAP Frame Alignment Pattern FEBE Far End Block Error FERF Far End Receive Failure HDLC High level Data Link Control HEC Header Error Check/Control IEEE Institute for Electrical and Electronic Engineers ITU-T International Telecommunications Union– Telecommunication ...
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Table 30 Acronyms (cont’d) SOC Start Of Cell SOH Section OverHead SONET Synchronous Optical NETwork SPE Synchronous Payload Envelope STM-1 Synchronous Transport Mode 1, 155–Mbit/s STS-3c Synchronous Transport System, Level 3, concatenated payload TA Terminal Adapter TF Transmission Failure TOH ...