HT6535 Holtek, HT6535 Datasheet
HT6535
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HT6535 Summary of contents
Page 1
... It provides an automatic high-burst bandwidth channel that supports DMA for ECP in both the forward and reverse directions. This chip supports 16-byte FIFO to smooth data flow and improves the bandwidth requirement. It also supports run-length encode (RLE) decompression in hardware. 1 HT6535 25th June ’97 ...
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... Block Diagram Pin Assignments 2 25th June ’97 HT6535 ...
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... MHz OSC input or 24MHz crystal input TESTO O 24 MHz crystal output This active low signal is issued by the host microprocessor to indicate a read IORZ I operation This signal indicates to this chip that DMA operation data transfer complete Description 3 25th June ’97 HT6535 ...
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... This input pin is for testing. It must be pulled low. This input pin decides the chip number ID. Refer to hardware configuration NUMID I for use of this pin pulled up internally. NC — VDD — Positive power supply inputs VSS — Ground reference power supply inputs Description 4 25th June ’97 HT6535 ...
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... I =6mA 2.4 — sour 5V — — — 5V — — — 5V — — — 5V — — 2 — HT6535 +0.3V DD =5V 5%, V =0V) SS Max. Unit 0 – — V 500 A 25th June ’97 ...
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... Note that the con- figuration registers are all write only. Index 00: ECP FIFO threshold register (de- fault value=00H Index 01: Parallel port mode register 1 0 PMODE1 PMODE0 0 0 ISA Compatible 0 1 PS/2 Compatible 1 0 EPP 1 1 ECP 6 25th June ’97 HT6535 0 0 ...
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... EPP mode. IOWZ Result 1 0 Data written to PD[0: Data read from the output latch 1 0 Data written to PD[0: Data written is latched 0 1 Data read from the output latch 0 1 Data read from PD[0:7] Result 7 HT6535 25th June ’97 ...
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... In EPP mode time-out (10 s approxi- mately) occurs, the current EPP cycle is aborted and the time-out condition is indicated in the Status register bit logic “1”. To clear this time-out bit, just write any value to the Status register. 8 25th June ’97 HT6535 ...
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... Parallel port timing Parameter t1 PD[7:0] delay from IOWZ inactive t2 STRBZ, AFDZ, INITZ, SLTINZ delay from IOWZ inactive t3 IRQ delay from ACKZ t4 IRQ active low pulse width t5 IRQ delay from ERRZ Min. Max. Units Notes 60 ns 100 800 ns 180 ns 9 25th June ’97 HT6535 ...
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... BUSY asserted to AFDZ, SLTINZ deasserted t9 AFDZ, SLTINZ deasserted to BUSY deasserted t10 BUSY deasserted to STRBZ deasserted t11 BUSY deasserted to PD[7:0] invalid Min. Max. Units Notes 140 240 ns 150 140 ns 70 140 140 ns 140 ns 10 25th June ’97 HT6535 ...
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... PD[7:0] valid to BUSY asserted t8 BUSY asserted to IORDY deasserted t9 BUSY asserted to AFDZ, SLTINZ deasserted t10 AFDZ, SLTINZ deasserted to PD[7:0] Hi-Z t11 PD[7:0] Hi-Z to BUSY deasserted Min. Max. Units Notes 140 210 140 ns 70 140 25th June ’97 HT6535 ...
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... BUSY deasserted to STRBZ asserted 1. Maximum value only applies if there is data in the FIFO waiting to be written out. Min. Max. Units Notes 500 ns 500 ns 500 ns 900 ns Min. Max. Units Notes 0 180 140 140 170 ns 560 850 ns 12 25th June ’97 HT6535 1 ...
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... ACKZ deasserted to AFDZ asserted t5 AFDZ asserted to PD[7:0] changed t6 AFDZ asserted to ACKZ asserted 1. Maximum value only applies if there is room in FIFO and a terminal count has not been received. Min. Max. Units Notes 0 ns 140 210 300 350 25th June ’97 HT6535 1 ...
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... Application Circuit 14 25th June ’97 HT6535 ...