PCI9054-AB50PI PLX Technology, Inc., PCI9054-AB50PI Datasheet
PCI9054-AB50PI
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PCI9054-AB50PI Summary of contents
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PCI 9054 Data Book ...
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PCI 9054 Data Book Version 2.1 January 2000 Website: http://www.plxtech.com Email: apps@plxtech.com Phone: 408 774-9060 FAX: 408 774-2169 800 759-3735 ...
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... PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products. ...
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... PCI Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1. PCI Target Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.2. PCI Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.2.1. DMA Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.2.2. Direct Local-to-PCI Command Codes 2-1 2.1.3. PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2. Local Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.1. Local Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.2. PCI Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.3. PCI Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. v ...
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... PCI Initiator Delayed Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4.1.7. PCI Initiator Configuration (PCI Configuration Type 0 or Type 1 Cycles 3-5 3.4.1.7.1. PCI Initiator Configuration Cycle Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.1.8. PCI Initiator PCI Dual Address Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.1.9. PCI Initiator/Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.1.10. PCI Initiator Memory Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 vi PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © ...
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... PCI Target Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.2. PCI Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.2.1. DMA Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.2.2. Direct Local-to-PCI Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.3. PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2. Local Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1. Local Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.2. PCI Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.3. PCI Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © Contents vii ...
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... PCI Initiator Memory Write and Invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.4.2. PCI Target Operation (PCI Master-to-Local Bus Access 5-8 5.4.2.1. PCI Target Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.4.2.2. PCI Target PCI v2.1 Delayed Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.4.2.3. PCI Target PCI Read Ahead Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 viii PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © ...
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... M Mode Local-to-PCI Doorbell Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.6.1.2. C and J Modes Local-to-PCI Doorbell Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.6.2. PCI-to-Local Doorbell Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.7. Built-In Self Test Interrupt (BIST 6-3 6.1.8. DMA Channel 0/1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.9. All Modes PCI SERR# (PCI NMI 6-4 6.1.10. M Mode PCI SERR 6-4 PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © Contents ix ...
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... Hot Swap Control/Status Register (HS_CSR 9-3 9.1.2.2.4. Hot Swap Capabilities Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 10. PCI Vital Product Data (VPD 10-1 10.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.1. VPD Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.2. VPD Serial EEPROM Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.3. Sequential Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.4. Random Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 x PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © ...
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... General Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2. Local Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.3. Local Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 14. Package, Signal, and Pinout Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1. 176-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2. 225-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 A. General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1. Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.2. United States and International Representatives, and Distributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.3. Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index-1 PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © Contents xi ...
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... PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... Block DMA Mode Initialization (Single Address or Dual Address PCI 5-7 5-5. Dual Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. xiii ...
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... PQFP PCB Layout Suggested Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14-3. 176-Pin PQFP PCI 9054 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14-4. 225-Pin PBGA Package Mechanical Dimensions—Topside, Underside, and Cross-Section Views . 14-4 14-5. 225-Pin PBGA PCB Layout Suggested Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14-6. 225-Pin PBGA Package Layout (Underside View 14-6 xiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 PLX Technology, Inc. All rights reserved. © PCI 9054 Data Book v2.1 ...
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... DMA Master Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-3. Local-to-PCI Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-4. Local-to-PCI I/O Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-5. Local-to-PCI Configuration Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-6. Local Bus Types (176-Pin PQFP 4-2 4-7. Local Bus Types (225-Pin PBGA 4-2 4-8. Burst and Bterm on the Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved 2-5 xv ...
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... PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © ...
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... PQFP Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14-2. 225-Pin PBGA Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14-3. 225-Pin PBGA PCI 9054 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 A-1. Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1 PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © Tables xvii ...
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... PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... PCI:04h, LOC:84h) Local Address Space 0 Local Base Address (Remap 11-19 11-40. (MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/DMA Arbitration 11-20 11-41. (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor 11-21 11-42. (LMISC; PCI:0Dh, LOC:8Dh) Local Miscellaneous Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. xix ...
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... PCI:A8h, LOC:128h) DMA Channel 0 Command/Status 11-38 11-81. (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status 11-38 11-82. (DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration 11-39 11-83. (DMATHR; PCI:B0h, LOC:130h) DMA Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39 11-84. (DMADAC0; PCI:B4h, LOC:134h) DMA Channel 0 PCI Dual Address Cycle Address Register . . 11-39 xx PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © ...
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... PCI:D8h, LOC:158h) Outbound Free Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11-97. (OFTPR; PCI:DCh, LOC:15Ch) Outbound Free Tail Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11-98. (OPHPR; PCI:E0h, LOC:160h) Outbound Post Head Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11-99. (OPTPR; PCI:E4h, LOC:164h) Outbound Post Tail Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 11-100. (QSR; PCI:E8h, LOC:168h) Queue Status/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © Registers xxi ...
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... PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... DMA PCI-to-Local, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords . . . . . . . . . . . . . . 3-52 3-35. DMA Local-to-PCI, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords . . . . . . . . . . . . . . 3-53 3-36. DMA Local-to-PCI, Address Unaligned, Bterm Disabled, Burst Enabled, PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved 3- 3-35 xxiii ...
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... PCI Initiator Configuration Read—Type 1 or Type 5-37 5-16. PCI Initiator Configuration Write—Type 1 or Type 5-38 5-17. Initialization from Serial EEPROM (2K Bit 5-39 5-18. Initialization from Serial EEPROM (4K Bit 5-40 5-19. PCI Configuration Write to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 xxiv PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © ...
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... PCI Target Burst Read with Prefetch Enabled (32-Bit Local Bus), Prefetech Counter Set 5-80 5-63. DMA Aligned PCI Address to Aligned Local Address, Bterm Enabled, Burst Enabled . . . . . . . . . . . 5-81 5-64. DMA Aligned Local Address to Aligned PCI Address, Bterm Enabled, Burst Enabled . . . . . . . . . . . 5-82 PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © Timing Diagrams xxv ...
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... PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... Tel: 781 246-9318, Fax: 781 224-1239, http://www.picmg.org • Intelligent I Architecture Specification Revision 1 Special Interest Group 2 404 Balboa Street, San Francisco, CA, 94118, USA Tel: 415 750-8352, Fax: 415 751-4829, http://www.i2osig.org PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Hot Swap Specification xxvii ...
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... M Mode— TSIZ0 is now pin 92 (PQFP) and pin N14 (PBGA). TSIZ1 is now pin 91 (PQFP) and pin P15 (PBGA). C and J Modes—LBE3# is now pin 92 (PQFP) and pin N14 (PBGA). LBE2# is now pin 91 (PQFP) and pin P15 (PBGA). PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © ...
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... Revised timing information in Tables 13-6 through 13-9, AC Electrical Characteristics for Local inputs and outputs. Corrected information for B9, C6, D10, and P6 in PBGA Pinout in Table 14-3. Added new Section 15, “Ordering Instructions.” PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © Revision History Comments xxix ...
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... Register 11-67, revised bit read bit, not reserved. Table 13-5, revised ICC Max range to 200. Table 14-2, revised 225-Pin PBGA Package Mechanical Dimensions. xxx Comments O to “I O simultaneously switching outputs.” PLX Technology, Inc. All rights reserved. © PCI 9054 Data Book v2.1 ...
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... Register 11-45, Bit 4, changed to all modes, added “/RETRY#.” Register 11-67, Bit 17, changed “Writing” to “Reading.” Section 12.1, Notes, changed. Sections 13.2 and 13.3, deleted note. Consolidated Appendices A and B into one appendix. PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. © Revision History Comments xxxi ...
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... PCI Local Data transfers up to 132 MB/s Serial EEPROM PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved Compatible, CompactPCI Hot Swap Friendly 2 for Adapters and Embedded Systems • 3.3V, 5V tolerant PCI and Local signaling supports Universal PCI Adapter designs, 3.3V core, low- power CMOS in 176-pin PQFP and 225-pin PBGA • ...
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... Local Slave Interface: (for PCI Initiator Xfers) - Dynamic Bus Width of 8,16 bits Local Master (for Ch 0/1 DMA Xfers) - Endian Conversion Local Master - Muxed (for PCI or non-Muxed Target Xfers) Addr/Data Unaligned Xfer PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Features ...
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... Company and Product Background 1.2 COMPANY AND PRODUCT BACKGROUND PLX Technology, Inc., the world leader in PCI-to-Local Bus I/O Accelerator chips, supports OEM customers in a wide variety of PCI applications. Customer applications include PC workstations and servers, PCI add-in boards, embedded PCI systems (such as routers and switches), and industrial PCI implementations (such as CompactPCI, PMC, and Passive Backplane PCI) ...
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... Incorporates an Extended Capability Pointer (ECP) mechanism • Incorporates added resources for software control of ENUM#, the ejector switch, and the status LED, which indicates insertion and removal to the user PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. include high ...
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... Management Event interrupt (PME#). PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. VPD Support. Fully supports the Vital Product Data (VPD) PCI extension, which provides an alternate access method other than Expansion ROM for VPD. PCI Dual-Address Cycle (DAC) Support (64-bit Address Space) ...
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... Data-Transfer modes: • Configuration Register Access • PCI Initiator Operation • PCI Target Operation • DMA Operation • IDMA/SDMA Operation © Company and Product Background Description processors. The PCI 9054 PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. ...
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... RST# Timing. Supports response to first configuration accesses after de-assertion of RST# under 2 PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Subsystem ID and Subsystem Vendor ID. Contains Subsystem ID and Subsystem Vendor ID in the PCI Configuration Register Space in addition to System and Vendor IDs. The PCI 9054 also contains a permanent Vendor ID (10B5h) and Device ID (9054h) ...
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... Reads allowed via Vital Reads allowed via Product Data Function Serial EEPROM Control (refer to Section 10) Register (CNTRL) © PLX Technology, Inc. All rights reserved. PCI 9050 160 PQFP Eight 32 bit Two 32 bit — — ...
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... All Stop TRDY# All Target Ready PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Total Pins Function 32 All multiplexed on the same PCI pins. The Bus transaction consists of an Address phase, followed by one or more Data phases. The PCI 9054 supports both Read and Write bursts. ...
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... Address cycle to occur. Used in conjunction with the PCI 9054 programmable wait state generator. As output from the PCI 9054: Asserted, along with READY#, to request break burst and start of a new Address cycle (PCI Aborts only). © PLX Technology, Inc. All rights reserved. PCI 9054 Data Book v2.1 ...
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... LA[31:2] C LAD[31:0] J Address/Data Bus PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Total Pins Function input, driven by the Master along with address and data indicating a Burst transfer is in progress output, driven by the PCI 9054 along with address and data indicating a Burst transfer is in progress ...
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... CompactPCI board latch status. 1 Could be used to monitor PCI Bus activity. Available only on the PBGA package. 1 Asserted to request use of the Local Bus. The Local Bus arbiter asserts LHOLDA when control is granted. © PLX Technology, Inc. All rights reserved. PCI 9054 Data Book v2.1 ...
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... Ready Input/Output RETRY# M Retry TA# M Transfer Acknowledge PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Total Pins Function 1 Asserted by the Local Bus arbiter when control is granted in response to LHOLD. Bus should not be granted to the PCI 9054 unless requested by LHOLD input to the PCI 9054, when asserted low, causes a PCI interrupt ...
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... Ready input from an external Master for PCI Initiator accesses output, asserted by the PCI 9054 when internal wait state generator causes wait states. Can be thought output providing PCI 9054 Ready status. 1 See BIGEND#/WAIT#. © PLX Technology, Inc. All rights reserved. PCI 9054 Data Book v2.1 ...
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... PCI command codes when the PCI 9054 is the Master. DMA cannot perform I/O or configuration accesses. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 2.1.2.1 DMA Master Command Codes DMA controllers of the PCI 9054 can assert the Memory cycles listed in Table 2-2. ...
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... Local Processor generates wait states with WAIT# PCI 9054 PCI accessing Local Bus 9054 PCI 9054 generates wait states with WAIT# (programmable) Local Bus can respond to PCI 9054 requests with READY# PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... BI# is supported in Burst-4 mode. Refer to the MPC850 or MPC860 data manual. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. On the Local Bus, BTERM# is not supported, but the Bterm bit can be used to gain maximum performance and data throughput. • If the Burst Mode bit is enabled, but the Bterm Mode bit is disabled, then the PCI 9054 bursts four Lwords ...
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... PCI 9054. The PCI Bus parity checking and generation is independent of the Local Bus parity checking and generation. PCI Bus parity checking may result in assertion of PERR#, a PCI Bus system PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Local Bus Cycles ...
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... AD[15:8] 2 AD[23:16] 3 AD[31:24] PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. M Mode Bus Operation 2.3.2 Local Bus Big/Little Endian Mode The PCI 9054 Local Bus can be programmed to operate in Big or Little Endian mode. Table 2-11. Byte Number and Lane Cross-Reference Byte Number Big Endian ...
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... Byte 2 appears on Local Data [7:0] Byte 3 appears on Local Data [7:0] Little Endian BYTE 2 BYTE 1 BYTE 0 First Cycle Second Cycle 7 Third Cycle BYTE BYTE BYTE Big Endian 0 PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved ...
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... EEPROM initialization, the PCI 9054 responds to a Local processor access by delaying acknowledgement of the cycle (TA#). PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. M Mode Bus Operation 2.4.1.2 Local Initialization The PCI 9054 issues a Retry to all PCI accesses until the Local Init Status bit (LMISC[2]) is set. This bit can be programmed three different ways: 1 ...
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... The PCI 9054 then loads the Least Significant Word bits (LSW[15:0]), starting again from the most significant bit ([15]). Therefore, the PCI 9054 loads the Device ID, Vendor ID, class code, and so forth. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Serial EEPROM Condition ...
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... LSW of PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. from the serial EEPROM, the CNTRL[27] bit (refer to Section 2.4.2) or the VPD function should be utilized. With full utilization of VPD, the designer can perform reads and writes from/to the serial EEPROM, 32 bits at a time ...
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... NM93C56L). PCI Register Serial EEPROM Register Bits Affected PCISID[15:0] PCISVID[15:0] LAS1RR[31:16] LAS1RR[15:0] LAS1BA[31:16] LAS1BA[15:0] LBRD1[31:16] LBRD1[15:0] Reserved HS_NEXT[7:0] / HS_CNTL[7:0] Recommended Serial EEPROMs PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... Power Management registers • Hot Swap registers • VPD registers Figure 2-6 illustrates how these accessed. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. PCI Bus Master Set Clear Figure 2-6. PCI 9054 Internal Register Access by delaying 2.4.3.1 PCI Bus Access to Internal ...
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... The PCI 9054 TA# signal indicates that Data transfer is complete. 2-12 Address Mode Pin PCI 9054 how the PCI 9054 Internal Register Chip Select Figure 2-7. Address Decode Mode © PLX Technology, Inc. All rights reserved. Serial EEPROM CCS# (PCI 9054 Chip Select) PCI 9054 Data Book v2.1 ...
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... D15 D14 D13 D12 D11 D10 D9 BITS [15:0] CONFIGURATION REGISTER 0 HEX EESK(continues) EECS EEDO D15 D14 D13 D12 D11 D10 LAST WORD Timing Diagram 2-1. Initialization from Serial EEPROM (2K Bit) PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 10us 15us ...
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... BITS [31:16] CONFIGURATION REGISTER 0 HEX D14 D13 D12 D11 D10 BITS [31:16] OF CONFIGURATION REGISTER 8 HEX EESK, EEDO, EECS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ 200ns 250ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 30us ...
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... Timing Diagram 2-4. PCI Configuration Read to PCI Configuration Register 0ns 50ns CLK 1 2 FRAME# AD[31:0] ADDR C/BE[3:0]# CMD=7 IRDY# DEVSEL# TRDY# Timing Diagram 2-5. PCI Memory Write to Local Configuration Register PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 100ns 150ns Data Read BE 100ns 150ns Data BE ...
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... LINT# Timing Diagram 2-7. Local Interrupt Asserting PCI Interrupt 2-16 100ns 150ns Data Read BE 200ns 300ns ADDR CMD RESPONSE ON THE PCI BUS © PLX Technology, Inc. All rights reserved. Serial EEPROM 200ns 250ns 7 8 400ns 500n DATA BE PCI 9054 Data Book v2.1 ...
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... I/O Space bits (PCICR[2:0]) programmed by that Host after initialization completes (LMISC[2]=1). PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 3.3 RESPONSE TO FIFO FULL OR EMPTY Table 3-1 lists the PCI 9054 response to full and empty FIFOs. 3.4 DIRECT DATA TRANSFER MODES The PCI 9054 supports three direct transfer modes: • ...
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... Full Normal Empty De-assert REQ# Full De-assert REQ# Empty Normal Direct Data Transfer Modes Local Bus 1 De-assert TA#, RETRY# Normal 2 Normal De-assert TA# Normal 4 De-assert BB# 4 De-assert BB# Normal 4 De-assert BB# Normal Normal 4 De-assert BB# PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
Page 65
... PCI 9054. All PCI Initiator cycles are then decoded as PCI Memory, I/O, or Configuration Type PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Local Range for PCI Initiator-to-PCI PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration ...
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... PCI Initiator cycle ends. The Read cycle is terminated when the Local BDIP# input is de-asserted. Unused Read data is flushed from the FIFO. Direct Data Transfer Modes PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... Local Bus. For reads, the PCI 9054 holds off TA# while receiving an Lword from the PCI Bus. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 3.4.1.6 RETRY# Capability 3.4.1.6.1 PCI Initiator Write FIFO Full The PCI 9054 supports the PCI Initiator Write FIFO full condition ...
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... PCI Read or a PCI Write cycle. Whenever the DMDAC register contains a value of 0x00000000, the PCI 9054 performs a Single Address Cycle (SAC) on the PCI Bus. (Refer to Figure 3-4.) Value 00b 000100b 000b 01010b 00000000b 1 Direct Data Transfer Modes PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... If a Local Bus Master is attempting a Burst read from a nonresponding PCI device (Master/Target Abort), it PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Mode Register PCI Address Register receives TA# for the first cycle only. In addition, the PCI 9054 asserts TEA# if the Enable Local Bus TEA# bits are enabled (INTCSR[1:0], which can be used as an NMI) ...
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... Otherwise, it continues with a normal write Target disconnects before a cache line is completed, the PCI 9054 completes the remainder of that cache line, using normal writes. Figure 3-5. Dual Address Timing Direct Data Transfer Modes PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... PCI 9054 (no connection). Refer to Section 3.4.1 for more information about PCI Initiator Data transfers. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. M Mode Functional Description 3.4.2.2 SDMA Operation The PCI 9054 supports the MPC850 or MPC860 Serial DMA (SDMA) mode, using PCI Initiator mode. ...
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... Local Bus Figure 3-7. PCI Target PCI 9054 Read Ahead Mode Note: The figure represents a sequence of Bus cycles. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Local Bus PCI 9054 requests Read data from Local Bus Local memory ...
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... BTERM# Input Enable bit (the BTERM# input signal becomes the BI# signal in M mode). Space LBRD0[7], Space LBRD1[7], and Expansion ROM is in LBRD0[23]. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Master FRAME#, C/BE#, AD (addr) IRDY#, AD (data) DEVSEL#, TRDY# Figure 3-8 ...
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... Care Address bits, effectively specifying the address space required. The PCI software then maps the Local Address space into the PCI Address space by programming the PCI Base Address register. (Refer to Figure 3-10.) © Direct Data Transfer Modes O mode. 2 PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. ...
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... Address Figure 3-10. Local Bus PCI Target Access PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Range for PCI-to-Local Address Space 0/1 Bus Region Descriptors for PCI-to-Local Accesses Range for PCI-to-Local Expansion ROM Bus Region Descriptors for PCI-to-Local Accesses ...
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... Port Size LD[0:7] LD[8:15] LD[0:7] — OP0 — OP0 — — OP1 OP1 — OP2 — OP2 OP3 — OP3 OP3 — OP0 OP1 OP0 OP3 OP2 OP3 OP2 OP3 OP0 OP1 OP0 PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... DMA transfer from the Local Bus by re-asserting BR#. When it receives BG#, it drives the bus and continues the DMA transfer. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. M Mode Functional Description 3.4.4 Deadlock Conditions Deadlock can occur when a PCI Bus Master must ...
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... End of Transfer (EOT#). Only DMA Channel 0 supports Demand mode DMA transfers. Master mode must be enabled with the Master Enable bit (PCICR[2]) before the PCI 9054 can become a PCI © PLX Technology, Inc. All rights reserved. DMA Operation PCI 9054 Data Book v2.1 ...
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... Hi-Addr, with the command (C/BE[3:0]#) “6” or “7”, depending upon whether PCI Read or PCI Write cycle. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. M Mode Functional Description 3.5.2 Block DMA Mode The Host processor or the Local processor sets the Local and PCI starting addresses, transfer byte count, and transfer direction ...
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... Bit(s) BDIP# Output Disabled (1) BDIP# is not asserted. Enabled (0) Immediate transfer terminated by EOT#. Disabled (1) Enabled (0) BDIP# is asserted by the PCI 9054. Transfers up to the nearest 16-byte boundary, then terminates (MPC850 or MPC860 compatible). PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... DMA, using the DMA Clear Count Mode bit(s) (DMAMODE0[16] and/ or DMAMODE1[16]). PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. M Mode Functional Description Notes: In Scatter/Gather DMA mode, the descriptor includes the PCI and Local Address Space, transfer size, and next descriptor pointer ...
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... DMA Priority The DMA Channel Priority bit (MARBR[20:19]) can be used to specify the following priorities: • Rotating (MARBR[20:19]=00) • DMA Channel 0 (MARBR[20:19]=01) • DMA Channel 1 (MARBR[20:19]=10) © PLX Technology, Inc. All rights reserved. DMA Operation the Memory Write and PCI 9054 Data Book v2.1 ...
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... DMACSR1) to Initiate DMA Transfer Figure 3-17. Scatter/Gather DMA Mode Descriptor Initialization [DAC PCI Address (DMAMODE0[18], DMAMODE1[18]) Descriptor Dependent (PCI Address High Added) PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. M Mode Functional Description Local or Host Memory 3 First PCI Address ...
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... Clear Interrupt DMACSR1[3]=1). 3.5.7 DMA Data Transfers The PCI 9054 DMA controller can be programmed to transfer data from the Local-to-PCI Bus or from the PCI-to-Local Bus. DMA Operation bit(s) (DMACSR0[3]=1 and/or PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... FIFO becomes available, or after two PCI clocks if disconnect is received. Figure 3-19. PCI-to-Local Bus DMA Data Transfer Operation PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Load FIFO with FIFO Local Bus Read Cycles Local Bus ...
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... Immediate transfer Enabled (0) terminated by EOT#. Disabled (1) Enabled (0) BDIP# asserted by the PCI 9054. Transfers up to the nearest 16-byte boundary, then terminates (MPC850 or MPC860 compatible). Lword of the DMA transfer EOT# Enable bit(s) is PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. set ...
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... MPC860 compatible). PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 3.5.10 DMA Arbitration The PCI 9054 asserts BR# when it needs to be the Local Bus Master. Upon receiving BG#, the PCI 9054 waits for BB de-asserted. The PCI 9054 then ...
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... Timing Diagram 3-1. Local Bus Arbitration (BR#, BG#, BB#, and so forth) 3-26 250ns Other Local Bus Master drives Local Bus M Mode Timing Diagrams 500ns PCI 9054 asserts BB# to drives Local Bus and de-asserts BB# to end cycle PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# LCLK LA[0:31] A0 RD/WR# TSIZ[0:1] 00 BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-2. PCI Initiator Single Write Cycle, Zero Wait States PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns D0 Section 3 M Mode Functional Description 500ns 3-27 ...
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... DEVSEL# TRDY# LCLK LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# WAIT# Timing Diagram 3-3. PCI Initiator Single Read Cycle, One Wait State (WAIT# Asserted for One Clock) 3-28 250ns Mode Timing Diagrams 500ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... IRDY# DEVSEL# TRDY# LCLK LA[0:31] A0 RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-4. PCI Initiator Burst Write Cycle of Four Lwords, Zero Wait States PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns Section 3 M Mode Functional Description 500ns ...
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... IRDY# DEVSEL# TRDY# LCLK LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-5. PCI Initiator Burst Read Cycle of Four Lwords, Zero Wait States 3-30 250ns Mode Timing Diagrams 500ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# LCLK LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# RETRY# Timing Diagram 3-6. PCI Initiator Deferred Read Mode (RETRY#) PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns A0 00 Section 3 M Mode Functional Description 500ns 3-31 ...
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... Timing Diagram 3-7. PCI Initiator Burst Read with Read Ahead Mode (Prefetch Counter Set to Eight Lwords) 3-32 250ns 500ns © M Mode Timing Diagrams 750ns PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. ...
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... BURST# TS# BDIP# LD[0:31] TA# It takes a minimum of five clocks for the PCI 9054 to assert TA# Timing Diagram 3-9. Local Configuration Read from Configuration Register PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns 00 250ns 00 D0 Section 3 M Mode Functional Description 500ns 500ns ...
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... TRDY# LCLK LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-10. PCI Initiator Burst Write of Six Lwords beyond MPC860 Protocol 3-34 250ns Mode Timing Diagrams 500ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... IRDY# DEVSEL# TRDY# LCLK LA[0:31] A0 RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-11. PCI Initiator Burst Read of Six Lwords beyond MPC860 Protocol PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. M Mode Functional Description 250ns 500ns Section ...
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... M Mode PCI Target 0ns CLK FRAME# AD[31: C/BE[3:0 IRDY# DEVSEL# TRDY# LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-12. PCI Target Single Write Cycle, Zero Wait States 3-36 250ns © PLX Technology, Inc. All rights reserved. M Mode Timing Diagrams 500ns PCI 9054 Data Book v2.1 ...
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... CLK FRAME# AD[31: C/BE[3:0 IRDY# DEVSEL# TRDY# LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-13. PCI Target Single Write Cycle, One Wait State by Delaying TA# PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. M Mode Functional Description 250ns 500ns Section 3 3-37 ...
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... LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# LD[0:31] TA# Timing Diagram 3-14. Local Bus Single Write Cycle, Zero Wait States, Burst Enabled, 16-Bit Local Bus 3-38 250ns 500ns A A Mode Timing Diagrams 750ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# LD[0:31] TA# Timing Diagram 3-15. Local Bus Single Write Cycle, One Wait State, Burst Disabled, 8-Bit Local Bus PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns 500ns A A+1 A+2 A Section 3 M Mode Functional Description ...
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... M Mode Functional Description 0ns CLK FRAME# AD[31:0] A C/BE[3:0]# 6 IRDY# DEVSEL# TRDY# LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-16. PCI Target Single Read Cycle, Zero Wait States 3-40 250ns © PLX Technology, Inc. All rights reserved. M Mode Timing Diagrams 500ns PCI 9054 Data Book v2.1 ...
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... CLK FRAME# AD[31:0] A C/BE[3:0]# 6 IRDY# DEVSEL# TRDY# LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-17. PCI Target Single Read Cycle, One Wait State Using TA# PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. M Mode Functional Description 250ns 500ns Section 3 3-41 ...
Page 104
... CLK FRAME# AD[31:0] A C/BE[3:0]# 0 IRDY# DEVSEL# TRDY# LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-18. PCI Target Single Read Cycle, Zero Wait States, 16-Bit Bus 3-42 250ns A A © PLX Technology, Inc. All rights reserved. M Mode Timing Diagrams 500ns D0 PCI 9054 Data Book v2.1 ...
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... Timing Diagram 3-19. PCI Target Single Read Cycle, One Wait State, Burst Disabled, 8-Bit Local Bus 0ns LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-20. PCI Target Burst Write Cycle of Four Lwords, Bterm Disabled, Burst Enabled PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns 500ns A A+1 A 250ns 500ns ...
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... Timing Diagram 3-22. PCI Target Burst Write Cycle of Eight Lwords, Bterm Disabled, Burst Enabled 3-44 250ns 500ns 250ns 500ns Mode Timing Diagrams 750ns 750ns A7 PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-24. PCI Target Burst Write Cycle of 10 Lwords, Zero Wait States beyond MPC860 Protocol, Bterm Enabled, Burst Enabled PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns 500ns ...
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... Timing Diagram 3-25. PCI Target Burst Read Cycle of 10 Lwords, Zero Wait States beyond MPC860 Protocol, Bterm Enabled, Burst Enabled 3-46 250ns 500ns Mode Timing Diagrams 750ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
Page 109
... D15 D14 D13 D12 D11 D10 D9 BITS [15:0] CONFIGURATION REGISTER 0 HEX EESK(continues) EECS EEDO D15 D14 D13 D12 D11 D10 LAST WORD Timing Diagram 3-26. Initialization from Serial EEPROM (2K Bit) PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 10us 15us ...
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... CONTINUES 100ns 150ns Data BE M Mode Timing Diagrams 20us 25us BITS [31:16] CONFIGURATION REGISTER 0 HEX BITS [31:16] OF CONFIGURATION REGISTER 8 HEX 200ns 250ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 30us D0 D3 ...
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... CLK 1 2 FRAME# AD[31:0] ADDR C/BE[3:0]# CMD=7 IRDY# DEVSEL# TRDY# Timing Diagram 3-30. PCI Memory Write to Local Configuration Register PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 100ns 150ns 200ns Data Read BE 100ns 150ns Data ...
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... Timing Diagram 3-32. Local Interrupt Asserting PCI Interrupt 3-50 100ns 150ns Data Read BE 200ns 300ns ADDR CMD RESPONSE ON THE PCI BUS © PLX Technology, Inc. All rights reserved. M Mode Timing Diagrams 200ns 250ns 7 8 400ns 500n DATA BE PCI 9054 Data Book v2.1 ...
Page 113
... CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# LCLK LA[0:31] A0 RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# TEA# Timing Diagram 3-33. Master Abort Condition During PCI Initiator Read Cycle Causes TEA# PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. M Mode Functional Description 250ns 500ns 00 Section 3 3-51 ...
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... Timing Diagram 3-34. DMA PCI-to-Local, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords 3-52 250ns 500ns Mode Timing Diagrams 750ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... BR# BG# BB# LA[0:31 RD/WR# TSIZ[0:1] 00 BURST# TS# BDIP# LD[0:31 TA# Timing Diagram 3-35. DMA Local-to-PCI, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns 500ns ...
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... Example: Starting Local Address = 1008h, Starting PCI Address = 1000h Timing Diagram 3-36. DMA Local-to-PCI, Address Unaligned, Bterm Disabled, Burst Enabled, 3-54 250ns Transfer Size = Six Lwords M Mode Timing Diagrams 500ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
Page 117
... LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Example: Starting PCI Address = 1003h, Starting Local Address = 1000h Timing Diagram 3-37. DMA PCI-to-Local, Address Unaligned, Bterm Disabled, Burst Enabled, PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns 500ns ...
Page 118
... Timing Diagram 3-38. DMA Local-to-PCI, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts in the Middle of the Quad-Lword of Data 3-56 250ns 500ns Mode Timing Diagrams 750ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
Page 119
... BDIP# LD[0:31 TA# EOT# Timing Diagram 3-39. DMA Local-to-PCI, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts at the Last Data of the First Quad-Lword PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns 500ns ...
Page 120
... Timing Diagram 3-40. DMA PCI-to-Local, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts in the Middle of the First Quad-Lword of Data 3-58 250ns 500ns Mode Timing Diagrams 750ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
Page 121
... BURST# TS# BDIP# LD[0:31] TA# EOT# Timing Diagram 3-41. DMA PCI-to-Local, Bterm Disabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts at the Last Data of the First Quad-Lword PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns 500ns ...
Page 122
... Timing Diagram 3-42. DMA Local-to-PCI, Bterm Enabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts at End of Third Local Data beyond MPC860 Protocol 3-60 250ns 500ns Mode Timing Diagrams 750ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
Page 123
... BURST# TS# BDIP# LD[0:31] TA# EOT# Timing Diagram 3-43. DMA PCI-to-Local, Bterm Enabled, Burst Enabled, Transfer Size = Eight Lwords, EOT# Asserts at End of Third Local Data beyond MPC860 Protocol PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns 500ns ...
Page 124
... Local Bus Latency Timer expires --> PCI 9054 finishes current data and one more data is transferred before releasing the Local Bus (de-asserts BB#) in DMA Operation beyond MPC860 Protocol M Mode Timing Diagrams 750ns 750ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
Page 125
... TRDY# LCLK BR# BG# BB# LA[0:31] RD/WR# TSIZ[0:1] BURST# TS# BDIP# LD[0:31] TA# Timing Diagram 3-46. DMA PCI-to-Local, Bterm Enabled, Burst Enabled, Transfer Size = 10 Lwords, PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns 500ns ...
Page 126
... Timing Diagram 3-47. DMA Local-to-PCI, Bterm Enabled, Burst Enabled, Transfer Size = 10 Lwords, 3-64 250ns 500ns beyond MPC860 Protocol M Mode Timing Diagrams 750ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
Page 127
... The MPC850 or MPC860 starts IDMA cycle when the IDMA Enable bit is set in the MPC850 or MPC860 respective register. The PCI 9054 does not look at SDACK[1:0]# because the pins do not exist in the PCI 9054 (not connected). PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns 500ns D0 ...
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...
Page 129
... Programmable internal registers determine PCI command codes when the PCI 9054 is the Master. DMA cannot perform I/O or configuration accesses. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 4.1.2.1 DMA Master Command Codes DMA controllers of the PCI 9054 can assert the Memory cycles listed in Table 4-2. ...
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... Local Bus Cycles Local Bus Arbitration are asserted. When the PCI Local Master. After the PCI The Local Bus Pause Timer applies only to DMA PCI Initiator PCI Target PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 9054 9054 ...
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... The Internal Wait State bit(s) (LBRD0[21:18, 5:2], (LBRD1[5:2]), DMAMODE0[5:2], and/or DMAMODE1 PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. [5:2]) can be used to program the number of internal wait states between the first address-to-data (and subsequent data-to-data in Burst mode). Local Bus ...
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... Direct PCI access 16-bit Local Bus results in the PCI Bus Lword being broken into multiple Local Bus transfers. For each transfer, byte enables are encoded as in the i960C to provide Local Address bits LA[1:0]. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Local Bus Cycles ...
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... PCI Bus is a Little Endian bus (that is, the address is invariant and data is Lword-aligned to the lowermost byte lane). PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Bus Operation Table 4-10. PCI Bus Little Endian Byte Lanes Byte Number Byte Lane ...
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... Byte 1 appears on Local Data [7:0] Byte 2 appears on Local Data [7:0] Byte 3 appears on Local Data [7:0] Little Endian 0 BYTE 2 BYTE 1 BYTE 0 First Cycle Second Cycle 7 0 Third Cycle BYTE BYTE BYTE 0 0 Big Endian PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved ...
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... PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 4.4.1.2 Local Initialization The PCI 9054 issues a Retry to all PCI accesses until the Local Init Status bit (LMISC[2]) is set. This bit can be programmed three different ways: 1 ...
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... The PCI 9054 then loads the Least Significant Word bits (LSW[15:0]), starting again from the most significant bit [15]. Therefore, the PCI 9054 loads the Device ID, Vendor ID, class code, and so forth. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Serial EEPROM Condition ...
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... LSW of PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Section 4.4.2) or the VPD function should be utilized. With full utilization of VPD, the designer can perform reads and writes from/to the serial EEPROM, 32 bits at a time ...
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... Serial EEPROM Control register (CNTRL). Values should be programmed in the order listed in Table 4-21. The 44 16-bit words listed in Table 4-20 and Table 4-21 should be stored sequentially in the serial EEPROM. Description © PLX Technology, Inc. All rights reserved. Serial EEPROM Register Bits Affected PCISID[15:0] PCISVID[15:0] LAS1RR[31:16] LAS1RR[15:0] ...
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... Figure 4-5. Serial EEPROM Memory Map PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Bus Operation 4.4.2.5 Serial EEPROM Initialization During serial EEPROM initialization, the PCI 9054 responds to PCI Target accesses with a Retry. During serial EEPROM initialization, the PCI 9054 responds ...
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... The PCI 9054 READY# signal indicates that Data transfer is complete. Address Mode Pin PCI 9054 CCS# (PCI 9054 Chip Select) PCI 9054 Internal Register Chip Select Figure 4-7. Address Decode Mode PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Serial EEPROM how the ...
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... D15 D14 D13 D12 D11 D10 D9 BITS [15:0] CONFIGURATION REGISTER 0 HEX EESK(continues) EECS EEDO D15 D14 D13 D12 D11 D10 LAST WORD Timing Diagram 4-1. Initialization from Serial EEPROM (2K Bit) PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 10us 15us ...
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... AFTER COMPLETION OF READ CONTINUES 100ns 150ns Data BE Serial EEPROM 20us 25us BITS [31:16] CONFIGURATION REGISTER 0 HEX BITS [31:16] OF CONFIGURATION REGISTER 8 HEX 200ns 250ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 30us D0 D3 ...
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... CLK 1 2 FRAME# AD[31:0] ADDR C/BE[3:0]# CMD=7 IRDY# DEVSEL# TRDY# Timing Diagram 4-5. PCI Memory Write to Local Configuration Register PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 100ns 150ns 200ns Data Read BE 100ns 150ns Data ...
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... LINT# Timing Diagram 4-7. Local Interrupt Asserting PCI Interrupt 4-16 100ns 150ns Data Read BE 200ns 300ns ADDR CMD RESPONSE ON THE PCI BUS © PLX Technology, Inc. All rights reserved. Serial EEPROM 200ns 250ns 7 8 400ns 500n DATA BE PCI 9054 Data Book v2.1 ...
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... I/O Space bits (PCICR[2:0]) programmed by that Host after initialization completes (LMISC[2]=1). PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 5.3 RESPONSE TO FIFO FULL OR EMPTY Table 5-1 lists the response of the PCI 9054 to full and empty FIFOs. 5.4 DIRECT DATA TRANSFER MODES The PCI 9054 supports three direct transfer modes: • ...
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... Direct Data Transfer Modes Local Bus De-assert READY# Normal 1 Normal De-assert READY# Normal 3 De-assert LHOLD, assert BLAST# 3 De-assert LHOLD, assert BLAST# Normal 3 De-assert LHOLD, assert BLAST# Normal Normal 3 De-assert LHOLD, assert BLAST# PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
Page 147
... PCI Base Address Figure 5-1. PCI Initiator Access of the PCI Bus PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description Local Range for PCI Initiator-to-PCI PCI Configuration Address Register for PCI Initiator-to-PCI I/O Configuration PCI Command Register ...
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... READY# until the Write FIFO is full. It then holds off READY# until space becomes available in the Write FIFO. A programmable PCI Initiator FIFO “almost full” status output is provided (DMPAF). PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Master LA, ADS#, LBE#, LD/LAD, LW/R#, BLAST# READY# ...
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... Read data for I/O and configuration reads. For PCI Initiator I/O or Configuration cycles, the PCI 9054 asserts the same PCI Bus byte enables as set on the Local Bus. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description 5.4.1.5 PCI Initiator I/O If the ...
Page 150
... Master Abort. The Local Bus 000b Master must clear the Received Master Abort bit or 01010b Target Abort bit (PCISR[13 or 11]=0, respectively) and continue by processing the next task. 00000000b 1 © PLX Technology, Inc. All rights reserved. Direct Data Transfer Modes PCI 9054 Data Book v2.1 ...
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... It can then clear the Target Abort bit (PCISR[11]) to de-assert the LSERR# interrupt and re-enable PCI Initiator transfers. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. Mode Register PCI Address Register (set direction only) Figure 5-5. Dual Address Timing ...
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... With or without wait state(s), the Local Bus, independent of the PCI Bus, can: • Burst as long as data is available (Continuous Burst mode) • Burst four Lwords at a time (recommended) • Perform a continuous Single cycle PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... FIFO of the PCI 9054 instead of from the Local Bus. The address must be subsequent to the previous PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description address and 32-bit aligned (next address = current address + 4). Read Ahead mode functions with or without PCI Delayed Read mode ...
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... The PCI software then maps the Local Address space into the PCI Address space by programming the PCI Base Address register. (Refer to Figure 5-10.) Direct Data Transfer Modes PCI Target PCI-to-Local Address Mapping Initialization PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... Address Figure 5-10. Local Bus PCI Target Access PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description Range for PCI-to-Local Address Space 0/1 Bus Region Descriptors for PCI-to-Local Accesses Range for PCI-to-Local Expansion ROM ...
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... For PCI Read transactions from the Local Bus, the PCI 9054 holds off TRDY# while gathering data from the Local Bus. For Read accesses mapped to PCI Memory space, the PCI 9054 prefetches PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... Master on the PCI 9054 Local Bus must access the PCI Bus. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description There are two types of deadlock: • Partial Deadlock—A Local Bus Master is performing a Direct Bus Master access to a PCI ...
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... Assert PCI interrupt (INTA#) or Local interrupt (LINT#) when DMA transfer is complete or Terminal Count is reached during Scatter/Gather DMA mode transfers • Operate in DMA Clear Count mode (only if the descriptor is in Local memory) © PLX Technology, Inc. All rights reserved. DMA Operation PCI 9054 Data Book v2.1 ...
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... PCI Target or PCI Initiator has a higher priority than DMA. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. The PCI 9054 releases the PCI Bus if one of the following and conditions occur (refer to Figure 5-11 and Figure 5-12): • FIFO is full (PCI-to-Local Bus) • ...
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... DMA controller can be programmed to clear the transfer size at completion of each DMA, using the DMA Clear Count Mode bit(s) (DMAMODE0[16] and/ or DMAMODE1[16]). DMA Operation Block DMA PCI Dual Address Cycle Scatter/Gather DMA Mode PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... Local Bus (Control Access from the Local Bus) Note: The figures represent a sequence of Bus cycles. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description Figure 5-13. Dual Address Timing interrupt after terminal count (bit 2), and next descriptor location (bit 0) bits. ...
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... Scatter/Gather DMA operations. The PCI 9054 clears the Transfer Size descriptor to zero by writing to a descriptor-memory location at the end of each transfer chain. This feature works only if DMA descriptors are on the Local Bus. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. DMA Operation ...
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... Initiate DMA Transfer Figure 5-17. Scatter/Gather DMA Mode Descriptor Initialization [DAC PCI Address (DMAMODE0[18], DMAMODE1[18]) Descriptor Dependent] (PCI Address High Added) PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description Local or Host Memory 3 First PCI Address ...
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... A DMA Channel interrupt is cleared by the Channel Clear Interrupt DMACSR1[3]=1). 5.5.7 DMA Data Transfers The PCI 9054 DMA controller can be programmed to transfer data from the Local-to-PCI Bus or from the PCI-to-Local Bus. © PLX Technology, Inc. All rights reserved. DMA Operation whether to assert a PCI bit(s) (DMACSR0[3]=1 and/or ...
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... FIFO becomes available, or after two PCI clocks if disconnect is received. Figure 5-19. PCI-to-Local Bus DMA Data Transfer Operation PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description Load FIFO with FIFO Local Bus Read Cycles ...
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... During the descriptor loading on the Local Bus, assertion of EOT# causes a complete descriptor load and no subsequent Data transfer; however, this is not recommended. This has no effect when the descriptor is loaded from the PCI Bus. DMA Operation (DMAMODE0[15]=1 and/or PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... The DMA controller de-asserts its PCI Bus request (REQ#) for a minimum of two PCI clocks. PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description 5.5.11 Local Bus Latency and Pause Timers The Local Bus Latency and Pause Timers are programmable with the Mode/DMA Arbitration register (MARBR[7:0, 15:8]) ...
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... MUST REMAIN HIGH UNTIL LHOLD GOES LOW Local Bus PCI 9054 DRIVES BUS Timing Diagram 5-1. Local Bus Arbitration (LHOLD and LHOLDA) 5-24 250ns 500ns WILL NOT BE RE-ASSERTED UNTIL LHOLDA GOES LOW © PLX Technology, Inc. All rights reserved. C Mode Timing Diagrams PCI 9054 Data Book v2.1 ...
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... BLAST# LBE[3:0]# LBE LW/R# LA[31:2] A LD[31:0] D0 READY# (output) CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# Timing Diagram 5-2. PCI Initiator Single Write PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description 100ns 200ns A0 CMD Section 5 300ns 400ns D0 BE 5-25 ...
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... LCLK ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] A LD[31:0] READY# (output) CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# Timing Diagram 5-3. PCI Initiator Single Read 5-26 100ns 200ns LBE A0 CMD C Mode Timing Diagrams 300ns 400ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... READY# (output) WAIT# (input) CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# Timing Diagram 5-4. PCI Initiator Memory Write of 12 Lwords with WAIT# Input PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns CMD ...
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... WAIT# (input) CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# Timing Diagram 5-5. PCI Initiator Burst Read of Seven Lwords with WAIT# Input 5-28 250ns 500ns CMD BE © PLX Technology, Inc. All rights reserved. C Mode Timing Diagrams 750ns PCI 9054 Data Book v2.1 ...
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... CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# Timing Diagram 5-6. PCI Initiator Memory Read of 12 Lwords with Prefetch Counter Set to 16 PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description 250ns 500ns ...
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... Timing Diagram 5-7. Memory Write and Invalidate with Cache Line Size of Eight 5-30 250ns 500ns CMD © C Mode Timing Diagrams 750ns 1000ns D10 D11 D12 D13 D14 D15 BE PCI 9054 Data Book v2.1 PLX Technology, Inc. All rights reserved. ...
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... AD[31:0] A C/BE[3:0]# CMD DEVSEL# IRDY# TRDY# Timing Diagram 5-8. PCI Initiator Memory Read with Keep Bus Mode PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 500ns 750ns D0D1 De-assert IRDY# and Keep Bus Section 5 C and J Modes Functional Description ...
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... Timing Diagram 5-9. PCI Initiator Memory Read with Drop Bus Mode 5-32 250ns 500ns 750ns Mode Timing Diagrams 1000ns 1250ns 1500ns D10 D11 D13 D14 D12 D15 Drop Bus PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# Timing Diagram 5-10. PCI Bus Request (REQ#) Delay During Direct Master Write (Eight-PCI Clock Delay) PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description 250ns ...
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... IRDY# TRDY# LOCK# Timing Diagram 5-11. PCI Initiator Locked Read Followed by Write and Release (LLOCK# and LOCK#) 5-34 250ns 500ns KEEP LOCK --> R-RA D0 CMD 0 © PLX Technology, Inc. All rights reserved. C Mode Timing Diagrams 750ns UNLOCK --> WD R-WA WD CMD PCI 9054 Data Book v2.1 ...
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... Note: For partial deadlock, PCI Target Retry Delay Clock bits (LBRD0[31:28]) can be used to issue Retrys to the PCI Master attempting the PCI Target access. Timing Diagram 5-12. BREQo and Deadlock PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description 250ns 500ns BYTE ENABLES < ...
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... First READY# output will be delayed at least five clocks for access to shared registers. Timing Diagram 5-14. Local Bus Read to Configuration Register 5-36 100ns 200ns DATA 1 100ns 200ns DATA 0 DP0 C Mode Timing Diagrams 300ns 400ns 300ns 400ns DATA 1 DP1 PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... ADS# BLAST# LW/R# LA[31:2] LD[31:0] READY# (output) CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# Timing Diagram 5-15. PCI Initiator Configuration Read—Type 1 or Type 0 PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description 250ns 500ns A0 D0 CMD 0 Section 5 750ns D1 5-37 ...
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... LCLK ADS# BLAST# LW/R# LA[31:2] LD[31:0] READY# (output) CLK REQ# GNT# FRAME# AD[31:0] C/BE[3:0]# DEVSEL# IRDY# TRDY# Timing Diagram 5-16. PCI Initiator Configuration Write—Type 1 or Type 0 5-38 C Mode Timing Diagrams 250ns A D1 © PLX Technology, Inc. All rights reserved. 500ns A0 D0 CMD 0 PCI 9054 Data Book v2.1 ...
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... D15 D14 D13 D12 D11 D10 D9 BITS [15:0] CONFIGURATION REGISTER 0 HEX EESK(continues) EECS EEDO D15 D14 D13 D12 D11 D10 LAST WORD Timing Diagram 5-17. Initialization from Serial EEPROM (2K Bit) PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 10us 15us ...
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... EESK, EEDO, EECS FROM CONFIGURATION REGISTERS AFTER COMPLETION OF READ CONTINUES C Mode Timing Diagrams 20us 25us BITS [31:16] CONFIGURATION REGISTER 0 HEX BITS [31:16] OF CONFIGURATION REGISTER 8 HEX PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 30us D0 D3 ...
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... CLK 1 2 FRAME# AD[31:0] ADDR C/BE[3:0]# CMD=A IRDY# DEVSEL# TRDY# Timing Diagram 5-20. PCI Configuration Read to PCI Configuration Register PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description 100ns 150ns Data BE 100ns 150ns 200ns ...
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... DEVSEL# TRDY# Timing Diagram 5-22. PCI Memory Read to Local Configuration Register 5-42 100ns 150ns Data BE 100ns 150ns Data Read BE © PLX Technology, Inc. All rights reserved. C Mode Timing Diagrams 200ns 250ns 7 8 200ns 250ns 7 8 PCI 9054 Data Book v2.1 ...
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... FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# INTA# LCLK LINT# Timing Diagram 5-23. Local Interrupt Asserting PCI Interrupt PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description 200ns 300ns ADDR DATA CMD BE RESPONSE ON THE PCI BUS Section 5 400ns 500n ...
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... IRDY# DEVSEL# TRDY# LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) Timing Diagram 5-24. PCI Target Single Write (32-Bit Local Bus) 5-44 250ns LBE ADDR C Mode Timing Diagrams 500ns Data PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... Timing Diagram 5-25. PCI Target Burst Cycle Write (16-Bit Local Bus) 0ns LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LD[7:0]# LW/R# LA[31:2] READY# (input) Timing Diagram 5-26. PCI Target Burst Cycle Write (8-Bit Local Bus) PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 100ns 200ns 100ns 200ns ...
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... ADS# BLAST# LW/R# LA[31:2] LD[31:0] READY# (input) Timing Diagram 5-27. PCI Target Single-Cycle Read (32-Bit Local Bus) 5-46 100ns 200ns Mode Timing Diagrams 300ns 400ns DATA ADDR DATA PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 500ns ...
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... LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) Timing Diagram 5-28. PCI Target Single Read with One Wait State Using READY# Input (32-Bit Local Bus) PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 100ns 200ns 300ns ...
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... Timing Diagram 5-29. PCI Target Single Read with One Wait State Using Internal Wait State (32-Bit Local Bus) 5-48 200ns 300ns Mode Timing Diagrams 400ns 500ns 14 DATA ADDR DATA PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
Page 193
... LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] BTERM# (input) READY# (input) Timing Diagram 5-30. PCI Target Non-Burst Write (32-Bit Local Bus) PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns ADDR D0 Section 5 C and J Modes Functional Description 500ns ...
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... LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[7:0] BTERM# (input) READY# (input) Timing Diagram 5-31. PCI Target Non-Burst Write (8-Bit Local Bus) 5-50 100ns 200ns Mode Timing Diagrams 300ns 400ns PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... TRDY# LCLK LHOLD LHOLDA ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] BTERM# (input) READY# (input) Timing Diagram 5-32. PCI Target Non-Burst Local Bus Read PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. C and J Modes Functional Description 250ns ADDR D0 Section 5 500ns ...
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... Note: If Bterm is disabled, a new ADS# cycle starts every quad-Lword boundary. Timing Diagram 5-33. PCI Target Burst Write with Bterm Enabled (32-Bit Local Bus) 5-52 250ns LBE A A+4 A+8 A+C A+10 A+ Bterm FORCES NEW ADS# --> C Mode Timing Diagrams 500ns A+18 A+1C A+20 A+24 A+ D10 PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... Unaligned Transfer results in new ADS#. Note: Not all byte enables asserted or a quad boundary LA[3:2]=11 results in a new ADS#. Timing Diagram 5-34. PCI Target Burst Write with Bterm Disabled (32-Bit Local Bus) PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 200ns 300ns LBE = 0 ADDR A+4 ...
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... Timing Diagram 5-35. PCI Target Burst Read with Prefetch Counter Set to 8 (32-Bit Local Bus) 5-54 250ns BE ADDR + Mode Timing Diagrams 500ns LBE +8 +12 +16 +20 +24 + PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...
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... ADS# BLAST# LBE[3:0]# LW/R# LA[31:2] LD[31:0] READY# (input) Timing Diagram 5-36. PCI Target Burst Read with Prefetch Counter Set to 5 (32-Bit Local Bus) PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. 250ns BE LBE ADDR + Section 5 C and J Modes Functional Description 500ns ...
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... Five Lwords, one external wait state, Bterm enabled, Burst enabled. Timing Diagram 5-37. PCI Target Burst Write (32-Bit Local Bus) 5-56 250ns Mode Timing Diagrams 500ns LBE + PCI 9054 Data Book v2.1 © PLX Technology, Inc. All rights reserved. ...