CY37128P84-125YMB

Manufacturer Part NumberCY37128P84-125YMB
DescriptionUltraLogic 128-Macrocell ISR CPLD
ManufacturerCypress Semiconductor Corporation.
CY37128P84-125YMB datasheet
 


Specifications of CY37128P84-125YMB

CasePLCC-84L  
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Features
• 128 macrocells in eight logic blocks
• In-System Reprogrammable (ISR™)
— JTAG-compliant on-board programming
— Design changes don’t cause pinout changes
— Design changes don’t cause timing changes
• Up to 128 I/Os
— plus 5 dedicated inputs including 4 clock inputs
• High speed
— f
= 167 MHz
MAX
— t
= 6.5 ns
PD
— t
= 3.5 ns
S
Logic Block Diagram (160-pin TQFP)
16 I/Os
I/O
–I/O
0
15
16 I/Os
I/O
–I/O
16
31
16 I/Os
I/O
–I/O
32
47
16 I/Os
I/O
–I/O
28
63
TDI
JTAG Tap
TCLK
TDO
Controller
TMS
Selection Guide
Maximum Propagation Delay, t
(ns)
PD
Minimum Set-Up, t
(ns)
S
Maximum Clock to Output, t
(ns)
CO
Typical Supply Current, I
(mA) in Low Power Mode
CC
Cypress Semiconductor Corporation
PRELIMINARY
UltraLogic™ 128-Macrocell ISR™ CPLD
— t
= 4.5 ns
CO
• Product-term clocking
• IEEE 1149.1 JTAG boundary scan
• Programmable slew rate control on individual I/Os
• Low power option on individual logic block basis
• 5V and 3.3V I/O capability
• User-Programmable Bus Hold capabilities on all I/Os
• Simple Timing Model
• PCI compliant
• 84-160 pins in TQFP, PLCC and CLCC packages
• Pinout compatible with the CY37064/37064V, CY37128V,
CY37192/37192V, CY37256/37256V, CY7C373i,
CY7C374i, CY7C375i
CLOCK
INPUTS
INPUTS
1
4
INPUT/CLOCK
INPUT
MACROCELL
MACROCELLS
4
LOGIC
LOGIC
BLOCK
36
36
BLOCK
A
PIM
16
16
LOGIC
LOGIC
BLOCK
36
36
BLOCK
B
16
16
LOGIC
LOGIC
BLOCK
36
36
BLOCK
C
16
16
LOGIC
LOGIC
BLOCK
36
36
BLOCK
D
16
16
64
CY37128-167
6.5
4
4
30
3901 North First Street
CY37128
4
16 I/Os
I/O
–I/O
112
127
H
16 I/Os
I/O
–I/O
96
111
G
16 I/Os
I/O
–I/O
80
95
F
16 I/Os
I/O
–I/O
64
79
E
64
37128–1
CY37128-125
CY37128-100
10
12
5.5
7.0
6.5
6.5
30
30
San Jose
CA95134
• 408-943-2600
January 6, 1999

CY37128P84-125YMB Summary of contents