CY37128VP84-83YMB Cypress Semiconductor Corporation., CY37128VP84-83YMB Datasheet

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CY37128VP84-83YMB

Manufacturer Part Number
CY37128VP84-83YMB
Description
UltraLogic 3.3V 128-Macrocell ISR CLPD
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY37128VP84-83YMB

Case
PLCC-84L
Features
Selection Guide
Logic Block Diagram (160-pin TQFP)
Maximum Propagation Delay, t
Minimum Set-Up, t
Maximum Clock to Output, t
Typical Supply Current, I
Note:
• 128 macrocells in eight logic blocks
• 3.3V In-System Reprogrammable™ (ISR™)
• IEEE standard 3.3V operation
• Up to 128 I/Os
• High speed
Cypress Semiconductor Corporation
TDI
TCLK
TMS
1.
— JTAG-compliant on-board programming
— Design changes don’t cause pinout changes
— Design changes don’t cause timing changes
— 3.3V ISR
— 5V tolerant
— plus 5 dedicated inputs including 4 clock inputs
— f
Due to the 5V tolerant nature of the I/Os, the I/Os are not clamped to V
MAX
I/O
I/O
I/O
I/O
16
32
28
= 125 MHz
0
–I/O
–I/O
–I/O
–I/O
JTAG Tap
Controller
15
31
47
63
16 I/Os
16 I/Os
16 I/Os
16 I/Os
S
(ns)
CC
(mA) in Low Power Mode
CO
TDO
PD
(ns)
BLOCK
BLOCK
BLOCK
BLOCK
(ns)
LOGIC
LOGIC
LOGIC
LOGIC
4
C
D
64
A
B
MACROCELL
UltraLogic
INPUT
36
16
36
16
36
16
36
16
3901 North First Street
INPUTS
PRELIMINARY
1
PIM
INPUTS
TM
CLOCK
CC
.
4
3.3V 128-Macrocell ISR
36
16
36
16
36
16
36
16
INPUT/CLOCK
MACROCELLS
• Product-term clocking
• IEEE 1149.1 JTAG boundary scan
• Programmable slew rate control on individual I/Os
• Low power option on individual logic block basis
• User-Programmable Bus Hold capabilities on all I/Os
• Simple Timing Model
• PCI compliant
• 84 160 pins in TQFP, PLCC and CLCC packages
• Pinout compatible with the CY37128, CY37064/37064V,
CY37192/37192V, CY37256/37256V
— t
— t
— t
BLOCK
BLOCK
BLOCK
LOGIC
BLOCK
LOGIC
LOGIC
LOGIC
PD
S
CO
64
= 5.5 ns
H
G
E
F
= 10 ns
= 6.5 ns
4
San Jose
CY37128V-125
[1]
16 I/Os
16 I/Os
16 I/Os
16 I/Os
5.5
6.5
10
30
I/O
I/O
I/O
I/O
CA95134
112
96
80
64
–I/O
–I/O
–I/O
–I/O
37128v–1
111
95
79
127
CY37128V-83
CY37128V
January 6, 1999
TM
408-943-2600
8.0
8.0
15
30
CLPD

Related parts for CY37128VP84-83YMB

CY37128VP84-83YMB Summary of contents

Page 1

Features • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ (ISR™) — JTAG-compliant on-board programming — Design changes don’t cause pinout changes — Design changes don’t cause timing changes • IEEE standard 3.3V operation — 3.3V ISR — ...

Page 2

Functional Description The CY37128V is an In-System Reprogrammable (ISR) Com- plex Programmable Logic Device (CPLD) and is part of the Ultra37000™ family of high-density, high-speed CPLDs. Like all members of the Ultra37000 family, the CY37128V is de- signed to bring ...

Page 3

Pin Configurations GND I I/O /TCLK GND 10 11 I ...

Page 4

Pin Configurations (continued I I /TCLK I CLK / VCC 21 GND 22 CLK ...

Page 5

Pin Configurations (continued) 100 TCLK 1 GND CLK / ...

Page 6

Operating Range Ambient [2] Range Temperature Commercial +70 C Industrial – +85 C [3] Military – +125 C Shaded areas contain advance information. Electrical Characteristics Over the Operating Range Parameter Description V ...

Page 7

Capacitance Parameter Description C Input/Output Capacitance I/O C Clock Signal Capacitance CLK [7] Endurance Characteristics Parameter Description N Minimum Reprogramming Cycles AC Test Loads and Waveforms 238 (COM'L) 319 (MIL) 5V OUTPUT 170 (COM' 236 (MIL) INCLUDING ...

Page 8

Switching Characteristics Over the Operating Range Parameter Combinatorial Mode Parameters [10, 11] t Input to Combinatorial Output PD [10, 11] t Input to Output Through Transparent Input or Output Latch PDL [10, 11] t Input to Output Through Transparent Input ...

Page 9

Switching Characteristics Over the Operating Range Parameter t Buried Register Used as an Input Register or Latch Data IHPT Hold Time [10, 11] t Product Term Clock or Latch Enable (PTCLK) to Output CO2PT Delay (Through Logic Array) Pipelined Mode ...

Page 10

Typical I Characteristics The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. PRELIMINARY L ...

Page 11

Switching Waveforms Combinatorial Output INPUT COMBINATORIAL OUTPUT Registered Output with Synchronous Clocking INPUT SYNCHRONOUS CLOCK REGISTERED OUTPUT REGISTERED OUTPUT SYNCHRONOUS CLOCK Registered Output with Product Term Clocking Input Going Through the Array INPUT PRODUCT TERM CLOCK REGISTERED OUTPUT PRODUCT TERM ...

Page 12

Switching Waveforms (continued) Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register INPUT PRODUCT TERM CLOCK REGISTERED OUTPUT PRODUCT TERM CLOCK Latched Output INPUT LATCH ENABLE LATCHED OUTPUT Registered Input REGISTERED INPUT INPUT REGISTER CLOCK COMBINATORIAL OUTPUT ...

Page 13

Switching Waveforms (continued) Clock to Clock INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE PRELIMINARY t ...

Page 14

Switching Waveforms (continued) Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Output Enable/Disable INPUT OUTPUTS PRELIMINARY CY37128V t RR 37128V- 37128V- ...

Page 15

... CY37128VP160-83AC CY37128VP100-83AC CY37128VP84-83JC CY37128VP160-83AI CY37128VP100-83AI CY37128VP84-83JI CY37128VP84-83YMB In-System Reprogramming, ISR, UltraLogic, Ultra37000, InSRkit, Warp , and Impulse3 are trademarks of Cypress Semiconductor Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation. Document #: 38 00621–C Package Diagrams 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 ...

Page 16

Package Diagrams (continued) 160-Pin Thin Plastic Quad Flat Pack (TQFP) A160 PRELIMINARY 84-Lead Plastic Leaded Chip Carrier J83 16 CY37128V 51-85049-A 51-85006-A ...

Page 17

Package Diagrams (continued) © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor ...

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