CY7C09369V-12AI Cypress Semiconductor Corporation., CY7C09369V-12AI Datasheet
CY7C09369V-12AI
Specifications of CY7C09369V-12AI
Related parts for CY7C09369V-12AI
CY7C09369V-12AI Summary of contents
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... North First Street CY7C09269V/79V/89V CY7C09369V/79V/89V 3.3V 16K/32K/64K x 16/18 [1] — Active= 115 mA (typical) — Standby (typical) — Shorten cycle times — Minimize bus noise — Supported in Flow-Through and Pipelined modes 1 0 0/1 ...
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... Functional Description The CY7C09269V/79V/89V and CY7C09369V/79V/89V are high speed 3.3V synchronous CMOS 16K, 32K, and 64K x 16/18 dual-port static RAMs. Two ports are provided permit- ting independent, simultaneous access for reads and writes to [5] any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time ...
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... TTL Level) Typical Standby Current for SB3 (Both ports CMOS level) Shaded area contains advance information. Notes: 9. This pin is NC for CY7C09369V. 10. This pin is NC for CY7C09369V and CY7C09379V. PRELIMINARY 100-Pin TQFP (Top View ...
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... Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >1100V Latch-Up Current ...................................................... >200mA Operating Range Range Commercial +0.5V CC Industrial +0.5V CC Shaded area contains advance information. 4 CY7C09269V/79V/89V CY7C09369V/79V/89V AND CE must be asserted –I/O 8/9L 15/17L Ambient Temperature +70 C 3.3V – +85 C 3.3V . MAX ) ...
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... 3. 250 TH OUTPUT (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 90% 10% 10% GND 3 ns AND CE must be asserted to their active states ( CY7C09269V/79V/89V CY7C09369V/79V/89V -9 -12 Typ Max Min Typ Max 2.4 2.4 0.4 0.4 2.2 2.2 0.8 0.8 –10 10 –10 10 135 230 115 180 185 300 ...
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... Max 7 CY7C09269V/79V/89V CY7C09369V/79V/89V -9 -12 Min Max Min Max Units 40 33 MHz 67 50 MHz ...
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... CD2 CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only CY7C09269V/79V/89V CY7C09369V/79V/89V n+3 t CKHZ Q Q n+1 n OHZ OLZ t OE ...
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... [20,21,22,23] NO MATCH t CD1 MATCH t CWDD VALID , R/W, CNTEN, and CNTRST = for the Left Port, which is being written to CY7C09269V/79V/89V CY7C09369V/79V/89V CD2 CKHZ CKHZ CKLZ CD2 ...
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... During “No operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. PRELIMINARY [17,24,25,26 n+1 n CD2 CKHZ Q n READ NO OPERATION [17,24,25,26 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE . IH 9 CY7C09269V/79V/89V CY7C09369V/79V/89V A A n+3 n CD2 CKLZ WRITE READ A A n+4 n CKLZ CD2 Q n+4 READ Q n+3 ...
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... n+1 n+2 n n+2 t CD1 Q n+1 t CKHZ NO READ OPERATION [15,17,24,25,26 n+1 n+2 n n+2 n OHZ READ WRITE 10 CY7C09269V/79V/89V CY7C09369V/79V/89V n+3 n CD1 CD1 Q n CKLZ DC WRITE READ A A n+4 n CD1 t CD1 Q n CKLZ DC READ ...
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... R/W and CNTRST = PRELIMINARY [27] t SAD t SCN t CD2 n COUNTER HOLD READ WITH COUNTER [27 n+1 READ WITH COUNTER . IH 11 CY7C09269V/79V/89V CY7C09369V/79V/89V t HAD t HCN Q n+2 READ WITH COUNTER t t SAD HAD t t SCN HCN Q n+2 n+3 COUNTER HOLD COUNTER Q n+3 READ WITH ...
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... UB, LB, and R and CNTRST = 29. The “Internal Address” is equal to the “External Address” when ADS = V PRELIMINARY A n n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = CY7C09269V/79V/89V CY7C09369V/79V/89V [28,29 n+2 n n+3 n+4 WRITE WITH COUNTER . IH A n+4 ...
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... UB, and 31. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. PRELIMINARY WRITE READ ADDRESS 0 ADDRESS 0 13 CY7C09269V/79V/89V CY7C09369V/79V/89V n n READ READ ADDRESS 1 ...
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... Read OUT High-Z Outputs Disabled [32,36,37,38] CNTEN CNTRST I/O Mode Reset out( Load out( Hold out( Increment out(n+ CY7C09269V/79V/89V CY7C09369V/79V/89V Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation ...
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... Shaded area contains advance information. 16K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 7.5 CY7C09369V–7AC 9 CY7C09369V–9AC CY7C09369V–9AI 12 CY7C09369V–12AC CY7C09369V–12AI Shaded area contains advance information. 32K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 7.5 CY7C09379V–7AC 9 CY7C09379V–9AC CY7C09379V–9AI 12 CY7C09379V– ...
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... Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack CY7C09269V/79V/89V CY7C09369V/79V/89V Operating Range Commercial Commercial Industrial Commercial Industrial 51-85048-A ...