CY7C68013A-100AC Cypress Semiconductor Corporation., CY7C68013A-100AC Datasheet
CY7C68013A-100AC
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CY7C68013A-100AC Summary of contents
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... Features (CY7C68013A/14A only) • CY7C68014A: Ideal for battery powered applications — Suspend current: 100 µA (typ) • CY7C68013A: Ideal for non-battery powered applica- tions — Suspend current: 300 µA (typ) • Available in four lead-free packages with GPIOs — 128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), ...
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... CY7C68015A: Ideal for non-battery powered applica- tions — Suspend current: 300 µA (typ) • Available in lead-free 56-pin QFN package (26 GPIOs) — 2 more GPIOs than CY7C68013A/14A enabling addi- tional features in same footprint Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB FX2LP (CY7C68013A/14A low-power version of the EZ-USB FX2 ...
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... Note: 1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1, respectively. Document #: 38-08032 Rev. *G CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A The CLKOUT pin, which can be three-stated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency— ...
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... USB interrupt source, the FX2LP provides a second level of interrupt vectoring, called Autovectoring. When a USB interrupt is asserted, the FX2LP pushes the program counter onto its stack then jumps to address 0x0043, where it expects to find a “jump” instruction to the USB Interrupt service routine. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A SCON1 ...
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... Just as the USB Interrupt is shared among 27 individual USB- interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table 3-4 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Notes Page ...
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... RESET# pin is asserted. Cypress provides an application note which describes and recommends power on reset implementation and can be found on the Cypress web site. For more information on reset imple- mentation for the FX2 family of products visit the http://www.cypress.com. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Notes [3] . Figure 3-2 Page ...
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... USB upload • Set-up data pointer 2 • interface boot load. 3.10.3 External Code Memory The bottom 16 KBytes of program memory is external, and therefore the bottom 16 KBytes of internal RAM is accessible only as data memory. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A RESET Powered Reset Page ...
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... KBytes RAM here—RD#/WR# Code and Data strobes are not (PSEN#,RD#,WR#)* active) Data 2 C interface boot access Figure 3-3. Internal Code Memory CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A 48 KBytes External Code Memory (PSEN#) (OK to populate program memory here— PSEN# strobe is not active) ...
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... E73F 64 Bytes RESERVED E700 E6FF 8051 Addressable Registers (512) E500 E4FF Reserved (128) E480 E47F 128 bytes GPIF Waveforms E400 E3FF Reserved (512) E200 E1FF 512 bytes 8051 xdata RAM E000 CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A 64 KBytes External Code Memory (PSEN#) Code Page ...
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... EP8 EP8 512 512 512 1024 1024 512 512 512 Figure 3-5. Endpoint Configuration CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A EP2 EP2 EP2 EP2 EP2 512 1024 1024 1024 ...
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... FIFO. The slave interface can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A ...
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... GPIF The GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine. It allows the CY7C68013A/15A to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, printer parallel port, and Utopia. The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general-purpose ready inputs (RDY) ...
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... CY7C68013A is identical to CY7C68014A in form, fit, and functionality. CY7C68015A is identical to CY7C68016A in form, fit, and functionality. CY7C68014A and CY7C68016A have a lower suspend current than CY7C68013A and CY7C68015A respectively. CY7C68014A and CY7C68016A have a lower suspend current than CY7C68013A and CY7C68015A respectively: hence are ideal for power- sensitive battery applications ...
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... The signals on the left edge of the 56-pin package in Figure 4-1 are common to all versions in the FX2LP family with the noted differences between the CY7C68013A and the CY7C68015A. Three modes are available in all package versions: Port, GPIF master, and Slave FIFO. These modes define the signals on the right edge of the diagram ...
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... CS OE# D5 PSEN A15 D2 A14 D1 A13 D0 A12 A11 A10 128 Figure 4-1. Signals ** pinout for CY7C68015A/CY7C68016A only CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Slave FIFO FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0] SLRD SLWR FLAGA FLAGB FLAGC INT0#/ PA0 INT1#/ PA1 SLOE WU2/PA3 FIFOADR0 FIFOADR1 PKTEND PA7/FLAGD/SLCS# ...
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... *IFCLK 32 33 RESERVED 34 BKPT SCL 37 SDA OE# 38 Figure 4-2. CY7C68013A/CY7C68014A 128-pin TQFP Pin Assignment Document #: 38-08032 Rev. *G CY7C68013A/CY7C68014A 128-pin TQFP * denotes programmable polarity CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A PD0/FD8 *WAKEUP VCC RESET# CTL5 GND PA7/*FLAGD/SLCS# PA6/*PKTEND PA5/FIFOADR1 ...
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... AGND 19 VCC 20 GND 21 INT4 *IFCLK 26 RESERVED 27 BKPT 28 SCL 29 SDA 30 Figure 4-3. CY7C68013A/CY7C68014A 100-pin TQFP Pin Assignment Document #: 38-08032 Rev. *G CY7C68013A/CY7C68014A 100-pin TQFP * denotes programmable polarity CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A PD0/FD8 80 *WAKEUP 79 VCC 78 RESET# 77 CTL5 76 GND 75 PA7/*FLAGD/SLCS# 74 PA6/*PKTEND 73 PA5/FIFOADR1 72 PA4/FIFOADR0 ...
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... Figure 4-4. CY7C68013A/CY7C68014A 56-pin SSOP Pin Assignment Document #: 38-08032 Rev. *G CY7C68013A/CY7C68014A 56-pin SSOP PD5/FD13 1 PD6/FD14 2 PD7/FD15 3 GND 4 CLKOUT/T1OUT 5 VCC 6 GND 7 RDY0/*SLRD 8 RDY1/*SLWR 9 AVCC PA7/*FLAGD/SLCS# 10 XTALOUT PA6/PKTEND 11 XTALIN PA5/FIFOADR1 12 AGND PA4/FIFOADR0 13 AVCC 14 DPLUS 15 DMINUS 16 AGND 17 VCC 18 GND CTL2/*FLAGC 19 *IFCLK/T0OUT ...
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... XTALIN 5 AGND 6 AVCC 7 DPLUS 8 DMINUS 9 AGND 10 VCC 11 GND 12 *IFCLK/**PE0/T0OUT 13 RESERVED 14 Figure 4-5. CY7C68013A/14A/15A/16A 56-pin QFN Pin Assignment Document #: 38-08032 Rev. *G CY7C68013A/CY7C68014A & CY7C68015A/CY7C68016A 56-pin QFN * denotes programmable polarity ** denotes CY7C68015A/CY7C68016A pinout CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A RESET# 42 GND 41 PA7/*FLAGD/SLCS# 40 PA6/*PKTEND 39 PA5/FIFOADR1 38 PA4/FIFOADR0 ...
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... CY7C68013A/15A Pin Descriptions Table 4-1. FX2LP Pin Descriptions 128 100 56 56 TQFP TQFP SSOP QFN AVCC AVCC AGND AGND DMINUS DPLUS 117 A4 118 A5 119 A6 120 A7 126 ...
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... I/O/Z I Multiplexed pin whose function is selected by: (PA1) PORTACFG.1 PA1 is a bidirectional IO port pin. INT1# is the active-LOW 8051 INT1 interrupt input signal, which is either edge triggered (IT1 = 1) or level triggered (IT1 = 0). CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Description Page ...
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... Multiplexed pin whose function is selected by the (PB2) following bits: IFCONFIG[1..0]. PB2 is a bidirectional I/O port pin. FD[2] is the bidirectional FIFO/GPIF data bus. I/O/Z I Multiplexed pin whose function is selected by the (PB3) following bits: IFCONFIG[1..0]. PB3 is a bidirectional I/O port pin. FD[3] is the bidirectional FIFO/GPIF data bus. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Description Page ...
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... GPIFADR6 is a GPIF address output pin. I/O/Z I Multiplexed pin whose function is selected by (PC7) PORTCCFG.7 PC7 is a bidirectional I/O port pin. GPIFADR7 is a GPIF address output pin. I/O/Z I Multiplexed pin whose function is selected by the (PD0) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Description Page ...
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... PORTECFG.3 bit. PE3 is a bidirectional I/O port pin. RXD0OUT is an active-HIGH signal from 8051 UART0. If RXD0OUT is selected and UART0 is in Mode 0, this pin provides the output data for UART0 only when sync mode. Otherwise CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Description Page ...
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... RDY5 is a GPIF input signal. O/Z H Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL0 is a GPIF control output. FLAGA is a programmable slave-FIFO output status flag signal. Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Description Page ...
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... Input N/A RXD1is an active-HIGH input signal for 8051 UART1, which provides data to the UART in all modes. Output H TXD1is an active-HIGH output pin from 8051 UART1, which provides the output clock in sync mode, and the output data in async mode. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Description Page ...
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... Ground. Ground N/A Ground. N/A N/A No Connect. This pin must be left open. N/A N/A No Connect. This pin must be left open. N/A N/A No Connect. This pin must be left open. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Description chip from suspending interface. Connect to VCC with a 2. peripheral is attached. 2 C-compatible interface. Connect to VCC 2 C-compatible ...
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... LINE15 LINE14 LINE13 LINE12 LINE7 LINE6 LINE5 LINE4 COL5 COL4 COL3 COL2 LINE15 LINE14 LINE13 LINE12 CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Default xxxxxxxx CLKSPD0 CLKINV CLKOE 8051RES 00000010 rrbbbbbr ASYNC GSTATE IFCFG1 IFCFG0 10000000 RW FLAGA3 FLAGA2 ...
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... EP8 EP6 EP4 EP2 0 EP0ACK HSGRANT URES 0 EP0ACK HSGRANT URES EP8 EP6 EP4 EP2 EP8 EP6 EP4 EP2 CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Default LINE3 LINE2 LINE1 LINE0 00000000 R COL1 COL0 0 0 00000000 R IN:PKTS[0] 0 PFC9 PFC8 10001000 bbbbbrbb OUT:PFC10 PFC9 ...
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... BC6 BC5 BC4 BC6 BC5 BC4 BC6 BC5 BC4 HSNAK CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Default 0 0 GPIFWF GPIFDONE 000000xx ERRLIMIT 00000000 ERRLIMIT 0000000x bbbbrrrb LIMIT3 LIMIT2 LIMIT1 LIMIT0 xxxx0100 rrrrbbbb x ...
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... SLAVE RDYASYNC CTLTOGL SUSTAIN TC31 TC30 TC29 TC28 TC23 TC22 TC21 TC20 TC15 TC14 TC13 TC12 CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Default FULL EMPTY 0 STALL 00101000 rrrrrrrb FULL EMPTY 0 STALL 00101000 rrrrrrrb FULL EMPTY 0 STALL 00000100 rrrrrrrb FULL EMPTY ...
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... D4 0 DISCON A15 A14 A13 A12 A15 A14 A13 A12 CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Default TC3 TC2 TC1 TC0 00000001 RW 00000000 FS1 FS0 00000000 FIFO2FLAG 00000000 xxxxxxxx 0 0 ...
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... D15 D14 D13 D12 SM0_1 SM1_1 SM2_1 REN_1 TF2 EXF2 RCLK TCLK CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Default SEL 00000000 IDLE 00110000 RW IE1 IT1 IE0 IT0 00000000 RW GATE 00000000 ...
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... D15 D14 D13 D12 RS1 1 ERESI RESI EX6 PX6 CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Default 00000000 00000000 RW D11 D10 D9 D8 00000000 RW RS0 00000000 RW INT6 01000000 RW D3 ...
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... Reset Time after Valid Power RESET Pin Reset after powered on 8.1 USB Transceiver USB 2.0-compliant in full- and high-speed modes. Notes: 15 recommended to not power I/O with chip power is off. 16. Measured at Max VCC, 25°C. Document #: 38-08032 Rev. *G CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Conditions 0< V < VCC OUT I = – ...
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... CL AV DSU t (48 MHz) = 3*t – t – ns. ACC1 CL AV DSU Document #: 38-08032 Rev STBH STBL [18 ACC1 data in Min 9.6 0 CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A t AV Typ. Max. Unit 20.83 ns 41.66 ns 83 Page Notes 48 MHz 24 MHz 12 MHz ...
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... CL AV DSU Document #: 38-08032 Rev. *G Stretch = STBL STBH t SCSL t SOEL t DSU [ ACC1 data in Stretch = 1 [19] t ACC1 Figure 9-2. Data Memory Read Timing Diagram Min. 9.6 0 CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A DSU t DH data in Typ. Max. Unit 20.83 ns 41.66 ns 83 ...
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... Clock to CS Pulse LOW SCSL t Clock to Data Turn-on ON1 t Clock to Data Hold Time OFF1 Document #: 38-08032 Rev STBL STBH data out Stretch = 1 data out Figure 9-3. Data Memory Write Timing Diagram Description CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A OFF1 Min. Max. Unit ...
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... IFCLK must not exceed 48 MHz. Document #: 38-08032 Rev IFCLK t SGA X t SRY t RYH valid t t SGD DAH X t XCTL N N+1 t XGD Description Output Propagation Delay Description Output Propagation Delay CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A [19] [20, 21] Min. Max. Unit 20. 6.7 ns [21] Min. Max. Unit 20 ...
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... SLOE Turn-off to FIFO Data Hold OEoff t Clock to FLAGS Output Propagation Delay XFLG t Clock to FIFO Data Output Propagation Delay XFD Document #: 38-08032 Rev IFCLK t RDH t SRD t XFLG N N OEon XFD Description Description CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A t OEoff [19] [21] Min. Max. Unit 20. 10.5 ns 10.5 ns 9.5 ns TBD 11 ns [21] Min ...
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... SLOE Turn-off to FIFO Data Hold OEoff Note: 23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document #: 38-08032 Rev RDpwh t RDpwl t XFLG t XFD N OEon OEoff [23] Description CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A [19] Min. Max. Unit 10.5 ns 10.5 ns Page ...
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... FIFO Data to Clock Set-up Time SFD t Clock to FIFO Data Hold Time FDH t Clock to FLAGS Output Propagation Time XFLG Document #: 38-08032 Rev IFCLK t WRH t SWR SFD FDH t XFLG Description Description CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Z [19] [21] Min. Max. Unit 20. 9.5 ns [21] Min. Max. Unit 20.83 ...
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... XFLG Description Description the FIFOs or thereafter. The only consideration is the set-up time t and the hold time t SPE Although there are no specific timing requirement for the PKTEND assertion, there is a specific corner case condition CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A [19] [23] Min. Max. Unit ...
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... IFCLK cycle timing between the assertion of PKTEND and clocking of the last byte of the previous packet (causing the packet to be committed automatically). Failing to adhere to this timing, will result in the FX2 failing to send the one byte/word short packet. t PEpwl t XFLG Description CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A >= t WRH FDH ...
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... Table 9-16. Slave FIFO Address to Flags/Data Parameters Parameter t FIFOADR[1:0] to FLAGS Output Propagation Delay XFLG t FIFOADR[1:0] to FIFODATA Output Propagation Delay XFD Document #: 38-08032 Rev OEoff t OEon Description t XFLG t XFD N N+1 Description CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A [19] Min. Max. Unit 10.5 ns 10.5 ns [19] Min. Max. Unit 10.7 ns 14.3 ns Page ...
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... Figure 9-15. Slave FIFO Asynchronous Address Timing Diagram Slave FIFO Asynchronous Address Parameters Parameter t FIFOADR[1:0] to SLRD/SLWR/PKTEND Set-up Time SFA t RD/WR/PKTEND to FIFOADR[1:0] Hold Time FAH Document #: 38-08032 Rev SFA FAH [21] Description t SFA [23] Description CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Min. Max. Unit 20.83 200 FAH [19] Min. Max. Unit 10 ns ...
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... During the first read cycle, on the rising edge of the clock the FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK, while the SLRD is asserted, the FIFO pointer is incre- mented and the next data value is placed on the data bus. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A >= t RDH t ...
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... PKTEND pin atleast one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet (the packet with the number of bytes equal to what is set in the AUTOINLEN register). Refer to Figure 9- 10 for further details on this timing. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A t FAH >= t ...
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... through 5. Note: In burst read mode, during SLOE is assertion, the data bus driven state and outputs the previous data. Once SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incremented. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A t FAH t ...
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... SLWR and the PKTEND before the de- SFD signal at the same time. It should be designed to assert the PKTEND after SLWR is de-asserted and met the minimum de- asserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion. CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A t FAH t t WRpwl ...
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... SSOP • 56-pin QFN • 100-pin TQFP • 128-pin TQFP Package Diagrams Figure 11-1. 56-lead Shrunk Small Outline Package O56 Document #: 38-08032 Rev. *G CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A Package Type RAM Size 128 TQFP – Lead-Free 100 TQFP – Lead-Free 56 SSOP – Lead-Free 56 QFN – ...
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... Package Diagrams (continued) Dimensions in millimeters E-Pad size 4 5.0 mm (typ). Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 – 8 mm) LF56 Figure 11-3. 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-08032 Rev. *G CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A 51-85144-*D 51-85050-*A Page ...
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... Note: 24. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf. Document #: 38-08032 Rev. *G CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A [24] • preferred is to have no vias placed on the DPLUS or DMINUS trace routing. • Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm ...
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... PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane Figure 13-3. X-ray Image of the Assembly 2 C system, provided that the system conforms to the I CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A 2 C Standard Specification Page ...
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... Document History Page Document Title: CY7C68013A EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller Document Number: 38-08032 REV. ECN NO. Issue Date ** 124316 03/17/03 *A 128461 09/02/03 *B 130335 10/09/03 *C 131673 02/12/04 *D 230713 See ECN *E 242398 See ECN *F 271169 See ECN *G 316313 See ECN Document #: 38-08032 Rev. *G Orig ...