KU80486SXSA-33 Intel Corporation, KU80486SXSA-33 Datasheet
KU80486SXSA-33
Related parts for KU80486SXSA-33
KU80486SXSA-33 Summary of contents
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Embedded Intel486™ SX Processor Product Features 32-Bit RISC Technology Core 8-Kbyte Write-Through Cache Four Internal Write Buffers Burst Bus Cycles Dynamic Bus Sizing for 8- and 16-bit Data Bus Devices SL Technology 64-Bit Interunit Transfer Bus 32-Bit Data Bus 32-Bit ...
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Contents 1.0 Introduction.................................................................................................................................... 5 1.1 Features................................................................................................................................ 5 1.2 Family Members ................................................................................................................... 6 2.0 How To Use This Document ......................................................................................................... 7 3.0 Pin Descriptions ............................................................................................................................ 7 3.1 Pin Assignments ................................................................................................................... 7 3.2 Pin Quick Reference ...........................................................................................................16 4.0 Architectural and Functional Overview ...
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Contents Tables 1 The Embedded Intel486™ SX Processor Family ......................................................................... 6 2 Pinout Differences for 168-Pin PGA Package .............................................................................. 9 3 Pin Assignment for 168-Pin PGA Package .................................................................................. 9 4 Pin Cross Reference for 168-Pin PGA Package ........................................................................ 11 5 ...
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Introduction The embedded Intel486™ SX processor provides high performance to 32-bit, embedded applications. Designed for applications that do not need a floating-point unit, the processor is ideal for embedded designs running DOS*, Microsoft* Windows*, OS/2*, or UNIX* applications written ...
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Intel486™ SX Processor • Write Buffers — The processor contains four write buffers to enhance the performance of consecutive writes to memory. The processor can continue internal operations after a write to these buffers, without waiting for the write to ...
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How To Use This Document For a complete set of documentation related to the embedded Intel486 SX processor, use this document in conjunction with the following reference documents: • Embedded Intel486™ Processor Family Developer’s Manual — Order No. 273021 ...
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Intel486™ SX Processor Figure 1. Package Diagram for 168-Pin PGA Embedded Intel486™ SX Processor A B D20 D19 D11 1 D22 D21 D18 CLK D23 DP3 SS 5 D25 ...
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Table 2. Pinout Differences for 168-Pin PGA Package Pin # Intel486™ A10 A12 A14 A15 B12 B13 B14 B15 B16 C14 J1 R17 S4 † INC. Internal No Connect. These pins are not connected to any internal pad ...
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Intel486™ SX Processor Table 3. Pin Assignment for 168-Pin PGA Package (Sheet Pin # Description B10 B11 B12 B13 B14 B15 B16 B17 ...
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Table 4. Pin Cross Reference for 168-Pin PGA Package Address Pin # A2 Q14 A3 R15 A4 S16 A5 Q12 A6 S15 A7 Q13 A8 R13 A9 Q11 A10 S13 A11 R12 A12 S7 A13 Q10 A14 S5 A15 R7 ...
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Intel486™ SX Processor Figure 2. Package Diagram for 196-Lead PQFP Embedded Intel486™ SX Processor V 148 SS NC 149 A3 150 NC 151 A4 152 NC 153 A5 154 NC 155 RESERVED# 156 NC 157 A6 158 A7 159 NC ...
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Table 5. Pin Assignment for 196-Lead PQFP Package Pin # Description A21 3 A22 4 A23 5 A24 A25 8 A26 9 A27 10 A28 A29 13 A30 ...
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Intel486™ SX Processor Table 5. Pin Assignment for 196-Lead PQFP Package Pin # Description D10 D11 38 D12 39 D13 D14 42 D15 43 DP2 44 D16 45 ...
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Table 6. Pin Cross Reference for 196-Lead PQFP Package (Sheet Address Pin # A16 181 A17 183 A18 189 A19 191 A20 193 A21 2 A22 3 A23 4 A24 5 A25 7 A26 8 A27 9 ...
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Intel486™ SX Processor 3.2 Pin Quick Reference The following is a brief pin description. For detailed signal descriptions refer to Appendix A, “Signal Descriptions,” in the Embedded Intel486™ Processor Family Developer’s Manual, order No. 273021. Table 7. Embedded Intel486™ SX ...
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Table 7. Embedded Intel486™ SX Processor Pin Descriptions (Sheet Symbol Type BUS CYCLE DEFINITION M/IO# O D/C# O W/R# O LOCK# O PLOCK# O BUS CONTROL ADS# O RDY# I Datasheet Name and Function Memory/Input-Output , Data/Control ...
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Intel486™ SX Processor Table 7. Embedded Intel486™ SX Processor Pin Descriptions (Sheet Symbol Type BURST CONTROL BRDY# I BLAST# O INTERRUPTS RESET I INTR I NMI I SRESET I SMI# I SMIACT Name and Function ...
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Table 7. Embedded Intel486™ SX Processor Pin Descriptions (Sheet Symbol Type STPCLK# I BUS ARBITRATION BREQ O HOLD I HLDA O BOFF# I CACHE INVALIDATION AHOLD I EADS# I CACHE CONTROL KEN# I Datasheet Name and Function ...
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Intel486™ SX Processor Table 7. Embedded Intel486™ SX Processor Pin Descriptions (Sheet Symbol Type FLUSH# I PAGE CACHEABILITY PWT O PCD O BUS SIZE CONTROL BS16# I BS8# I ADDRESS MASK A20M# I TEST ACCESS PORT TCK ...
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Table 8. Output Pins Name BREQ HLDA BE3#-BE0# PWT, PCD W/R#, M/IO#, D/C# LOCK# PLOCK# ADS# BLAST# PCHK# A3-A2 SMIACT# NOTE: The term “Previous State” means that the processor maintains the logic level applied to the signal pin just before ...
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Intel486™ SX Processor Table 11. Input Pins Name CLK RESET SRESET HOLD AHOLD EADS# BOFF# FLUSH# A20M# BS16#, BS8# KEN# RDY# BRDY# INTR NMI RESERVED# SMI# STPCLK# TCK TDI TMS NOTES: 1. Though STPCLK# has an internal pull-up resistor, an ...
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CPUID Instruction The embedded Intel486 SX processor supports the CPUID instruction (see Table 12). Because not all Intel processors support the CPUID instruction, a simple test can determine if the instruction is supported. The test involves the processor’s ID ...
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Intel486™ SX Processor Processor Signature Intel Reserved (Do Not Use) Feature Flags 4.2 Identification After Reset Processor Identification - Upon reset, the EDX register contains the processor signature: Processor Signature 4.3 Boundary Scan (JTAG) 4.3.1 Device Identification Table 13 shows ...
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Boundary Scan Register Bits and Bit Order The boundary scan register contains a cell for each pin as well as cells for control of bidirectional and three-state pins. There are “Reserved” bits which correspond to no-connect (N/C) signals of ...
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Intel486™ SX Processor 5.2 DC Specifications The following tables show the operating supply voltages, DC I/O specifications, and component power consumption for the embedded Intel486 SX processor. Table 15. Operating Supply Voltages Product x80486SXSA33 x80486SXSA33 NOTE: To address the fact ...
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Table 17 Values CC Functional Operating Range: V Parameter I Active CC (Power Supply) I Active CC (Thermal Design) I Stop Grant CC I Stop Clock CC NOTES: 1. This parameter is for proper power supply selection. ...
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Intel486™ SX Processor Table 18. AC Characteristics T = 0° +85° CASE D31–D0, DP3–DP0 Write Data Valid t 10 Delay D31–D0, DP3–DP0 Write Data Float t 11 Delay t EADS# Setup Time 12 t EADS# Hold ...
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Table 19. AC Specifications for the Test Access Port (5V PQFP Processors) T Symbol t TCK Frequency 24 t TCK Period 25 t TCK High Time 26 t TCK Low Time 27 t TCK Rise Time 28 t TCK Fall ...
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Intel486™ SX Processor Figure 4. Input Setup and Hold Timing BS8#, BS16#, KEN# BOFF#, AHOLD, HOLD RESET, FLUSH#, A20M#, INTR, NMI, SMI#, STPCLK#, SRESET Figure 5. Input Setup and Hold Timing RDY#, BRDY# D31-D0, DP3–DP0 ...
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Figure 6. PCHK# Valid Delay Timing RDY#, BRDY# Figure 7. Output Valid Delay Timing A2-A31, PWT, PCD, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, Datasheet CLK D31-D0 VALID DP3-DP0 MIN t 8 MAX PCHK ...
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Intel486™ SX Processor Figure 8. Maximum Float Delay Timing A2-A31, PWT, PCD, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA D31-D0, DP3–DP0 Figure 9. TCK Waveform TCK 0.8 V Figure 10. Test Signal Timing Diagram TCK TMS TDI TDO OUTPUT INPUT 32 ...
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Capacitive Derating Curves The following graphs are the capacitive derating curves for the embedded Intel486 SX processor. Figure 11. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition Processor nom+5 nom+4 nom+3 nom+2 ...
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Intel486™ SX Processor 6.0 Mechanical Data This section describes the packaging dimensions and thermal specifications for the embedded Intel486 SX processor. 6.1 Package Dimensions Figure 13. 168-Pin PGA Package Dimensions 34 Datasheet ...
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Table 20. 168-Pin Ceramic PGA Package Dimensions Symbol Min A 3. 0.43 D 44.07 D 40 1.52 1 Table 21. Ceramic PGA ...
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Intel486™ SX Processor Figure 14. Principal Dimensions and Data for 196-Lead Plastic Quad Flat Pack Package NOTE: Interpret dimensions and tolerances in accordance with ANSI Y14.5M-1982. Table 22. Symbol List and Dimensions for 196-Lead PQFP Package Symbol A Package Height: ...
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Figure 15. Typical Lead for 196-Lead PQFP Package 6.2 Package Thermal Specifications The embedded Intel486 SX processor is specified for operation when the case temperature (T within the range of 0° 85° the processor is within ...
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Intel486™ SX Processor Values for θ and θ JA Maximum T is shown in Table 26 for each product operating at 33 MHz. A Table 23. Thermal Resistance, θ 196-Lead PQFP (5V) - Without Heat Sink 196-Lead PQFP (5V) - ...