UPD78F0034BSGB-8ET NEC, UPD78F0034BSGB-8ET Datasheet
UPD78F0034BSGB-8ET
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UPD78F0034BSGB-8ET Summary of contents
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User’s Manual µ PD780024AS, 780034AS Subseries 8-Bit Single-Chip Microcontrollers µ PD780021AS µ PD780022AS µ PD780023AS µ PD780024AS µ PD780031AS µ PD780032AS µ PD780033AS µ PD780034AS µ PD78F0034BS µ PD78F0034BS(A) Document No. U16035EJ3V0UD00 (3rd edition) Date Published January 2004 N CP(K) ...
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User’s Manual U16035EJ3V0UD ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • ...
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Major Revisions in This Edition (1/3) Page Throughout Addition of description of expanded specification (12 MHz Revision of 1.6 78K/0 Series Lineup p. 36 Addition of description about pin handling to 2.2. Modification of description ...
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... Addition of Caution 5 to Figure 15-2 Format of Interrupt Request Flag Register (IF0L, IF0H, IF1L) p. 267 Addition of Caution to Figure 15-5 Format of External Interrupt Rising Edge Enable Regis- ter (EGP) and External Interrupt Falling Edge Enable Register (EGN) Description Pin and Figure 11-21 Example of Connection REF Pin and Figure 12-22 Example of Connection REF User’s Manual U16035EJ3V0UD 7 ...
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Major Revisions in This Edition (3/3) Page p. 269 Addition of description and Remark to 15.4.1 Non-maskable interrupt request acknowledge operation p. 272 Addition of description to 15.4.2 Maskable interrupt request acknowledge operation p. 275 Addition of item to Table ...
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Readers This manual has been prepared for user engineers who understand the functions of the µ PD780024AS, 780034AS Subseries and wish to design and develop application systems and programs for these devices. µ PD780024AS Subseries: µ PD780021AS, 780022AS, 780023AS, 780024AS, ...
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How to Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. • For readers who use this as an (A) product: → Standard products ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices µ PD780024AS, 780034AS Subseries User’s Manual 78K/0 Series Instructions User’s Manual 78K/0 Series Basic (I) ...
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... NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing ...
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... DD1 2.2.15 V and V ............................................................................................................................. SS0 SS1 2.2.16 V (flash memory versions only) .............................................................................................. PP 2.2.17 IC (mask ROM version only) ...................................................................................................... 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins .................................... CHAPTER 3 CPU ARCHITECTURE ................................................................................................. 3.1 Memory Spaces ..................................................................................................................... 3.1.1 Internal program memory space ................................................................................................ 3.1.2 Internal data memory space ...................................................................................................... 3.1.3 Special function register (SFR) area .......................................................................................... 3.1.4 External memory space ............................................................................................................. ...
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Relative addressing .................................................................................................................... 3.3.2 Immediate addressing ................................................................................................................ 3.3.3 Table indirect addressing ........................................................................................................... 3.3.4 Register addressing ................................................................................................................... 3.4 Operand Address Addressing ............................................................................................. 3.4.1 Implied addressing ..................................................................................................................... 3.4.2 Register addressing ................................................................................................................... 3.4.3 Direct addressing ....................................................................................................................... 3.4.4 Short direct addressing .............................................................................................................. 3.4.5 ...
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Configuration of 16-Bit Timer/Event Counter 0 .................................................................. 108 6.3 Registers Controlling 16-Bit Timer/Event Counter 0 ......................................................... 111 6.4 Operations of 16-Bit Timer/Event Counter 0 ...................................................................... 116 6.4.1 Operation as interval timer ......................................................................................................... 116 6.4.2 Operation as external event counter ...
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CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ............................................ 172 10.1 Functions of Clock Output/Buzzer Output Controller ....................................................... 172 10.2 Configuration of Clock Output/Buzzer Output Controller ................................................. 173 10.3 Registers Controlling Clock Output/Buzzer Output Controller ........................................ 173 10.4 Operations of Clock Output/Buzzer ...
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... Memory Size Switching Register ......................................................................................... 292 18.2 Flash Memory Characteristics ............................................................................................. 293 18.2.1 Programming environment ......................................................................................................... 293 18.2.2 Communication mode ................................................................................................................ 294 18.2.3 On-board pin handling ................................................................................................................ 297 18.2.4 Connection of adapter for flash writing ....................................................................................... 300 CHAPTER 19 INSTRUCTION SET ................................................................................................... 305 19.1 Conventions .......................................................................................................................... 305 19.1.1 Operand identifiers and specification methods .......................................................................... 305 19.1.2 Description of “operation” column .............................................................................................. 306 19.1.3 Description of “ ...
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B.4 Flash Memory Writing Tools ................................................................................................ 350 B.5 Debugging Tools (Hardware) ............................................................................................... 351 B.6 Debugging Tools (Software) ................................................................................................ 352 B.7 Embedded Software ............................................................................................................. 353 APPENDIX C NOTES ON TARGET SYSTEM DESIGN ................................................................ 354 APPENDIX D REGISTER INDEX ...................................................................................................... 356 D.1 ...
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Features • Internal memory Type Program Memory Part Number (ROM/Flash Memory) µ PD780021AS, 780031AS 8 KB µ PD780022AS, 780032AS 16 KB µ PD780023AS, 780033AS 24 KB µ PD780024AS, 780034AS 32 KB µ PD78F0034BS Note 32 KB Note The capacities ...
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Applications µ PD780021AS, 780022AS, 780023AS, 780024AS µ PD780031AS, 780032AS, 780033AS, 780034AS, 78F0034BS Home electric appliances, pagers, AV equipment, car audios, car electric equipment, office automation equipment, etc. µ PD780021AS(A), 780022AS(A), 780023AS(A), 780024AS(A) µ PD780031AS(A), 780032AS(A), 780033AS(A), 780034AS(A), 78F0034BS(A) Control ...
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Quality Grade Part Number µ PD780021ASGB-×××-8ET µ PD780022ASGB-×××-8ET µ PD780023ASGB-×××-8ET µ PD780024ASGB-×××-8ET µ PD780031ASGB-×××-8ET µ PD780032ASGB-×××-8ET µ PD780033ASGB-×××-8ET µ PD780034ASGB-×××-8ET µ PD78F0034BSGB-8ET µ PD780021ASGB(A)-×××-8ET µ PD780022ASGB(A)-×××-8ET µ PD780023ASGB(A)-×××-8ET µ PD780024ASGB(A)-×××-8ET µ PD780031ASGB(A)-×××-8ET µ PD780032ASGB(A)-×××-8ET µ PD780033ASGB(A)-×××-8ET µ PD780034ASGB(A)-×××-8ET µ ...
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... Remarks 1. When these devices are used in applications that require the reduction of noise generated from an on-chip microcontroller, the implementation of noise measures is recommended, such as supplying V and V independently, connecting V DD0 DD1 2. Pin connection in parentheses is intended for the µ PD78F0034BS and 78F0034BS(A). 22 CHAPTER 1 OUTLINE ...
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... AV : Analog power supply Analog reference voltage REF AV : Analog ground SS BUZ: Buzzer clock IC: Internally connected INTP0 to INTP3: External interrupt input P00 to P03: Port 0 P10 to P13: Port 1 P20 to P25: Port 2 P34 to P36: Port 3 P40 to P47: Port 4 P50 to P57: Port 5 CHAPTER 1 OUTLINE P70 to P75: ...
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Series Lineup The 78K/0 Series product lineup is illustrated below. Part numbers in the boxes indicate subseries names. Products in mass production Control µ PD78075B 100-pin µ PD78078 100-pin µ PD78070A 100-pin 100-pin µ PD780058 80-pin µ PD78058F ...
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The major functional differences between the subseries are shown below. • Subseries without the suffix Y Function ROM Subseries Name Capacity 8-Bit 16-Bit Watch WDT A/D µ PD78075B Control ...
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Subseries with the suffix Y Function ROM Subseries Name Capacity 8-Bit 16-Bit Watch WDT A/D µ PD78078Y Control µ PD78070AY – µ PD780018AY 48 ...
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... SS AV REF INTP0/P00 to Interrupt control 4 INTP3/P03 BUZ/P75 Clock/buzzer PCL/P74 output control Remarks 1. The internal ROM and RAM capacities depend on the product. 2. Pin connection in parentheses is intended for the µ PD78F0034BS. CHAPTER 1 OUTLINE 78K/0 ROM CPU core RAM System control DD0 ...
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Outline of Function Part Number Item Internal memory ROM High-speed RAM Memory space General-purpose register Minimum instruction execution time When main system clock selected When subsystem clock selected Instruction set I/O port A/D converter Serial interface Timer Timer output ...
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The outline of the timer/event counter is as follows (for details, refer to CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0, CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, CHAPTER 8 WATCH TIMER, and CHAPTER 9 WATCHDOG TIMER). Operation Interval timer mode External ...
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Pin Function List (1) Port pins Pin Name I/O P00 I/O Port 0 4-bit I/O port P01 Input/output mode can be specified in 1-bit units. P02 An on-chip pull-up resistor can be used by software settings. P03 P10 to ...
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... Input A/D converter analog input ADTRG Input A/D converter trigger signal input AV Input A/D converter reference voltage input REF AV — A/D converter analog power supply. Connect — A/D converter ground potential. Connect RESET Input System reset input X1 Input Crystal/ceramic connection for main system clock oscillation X2 — ...
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... Non-port pins (2/2) Pin Name I/O V — Ground potential for ports SS0 V — Ground potential other than ports SS1 IC — Internally connected. Connect directly — High-voltage application for program write/verify CHAPTER 2 PIN FUNCTION Function SS0 SS1 User’s Manual U16035EJ3V0UD ...
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Description of Pin Functions 2.2.1 P00 to P03 (Port 0) These are 4-bit I/O ports. Besides serving as I/O ports, they function as an external interrupt input, and A/D converter external trigger input. The following operating modes can be ...
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Control mode These ports function as serial interface data I/O and clock I/O. (a) SI30 and SO30 Serial interface serial data I/O pins. (b) SCK30 Serial interface serial clock I/O pin. ( and ...
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... PCL Clock output pin. (f) BUZ Buzzer output pin. 2.2.8 AV REF This is an A/D converter reference voltage input pin. When no A/D converter is used, connect this pin to the pin. SS1 2.2 This is an analog power supply pin of A/D converter. Always use the same potential as that of the V pin even when no A/D converter is used ...
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... High-voltage apply pin for flash memory programming mode setting and program write/verify. Handle in either of the following ways. • Independently connect a 10 kΩ pull-down resistor. • Set the jumper on the board so that this pin is connected directly to the dedicated flash programmer in programming mode and directly to V When there is a potential difference between the V two pins is too long or external noise is input to the V 2 ...
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... Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 shows the types of pin I/O circuit and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Pin Name I/O Circuit Type P00/INTP0 to P02/INTP2 8-C P03/INTP3/ADTRG P10/ANI0 to P13/ANI3 25 P20/SI30 8-C P21/SO30 5-H P22/SCK30 8-C P23/RxD0 ...
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TYPE 2 IN Schmitt-triggered input with hysteresis characteristics TYPE 5-H Pull-up enable V DD0 Data P-ch Output N-ch disable V Input enable TYPE 8-C Pull-up enable V DD0 Data P-ch Output N-ch disable V 38 CHAPTER 2 PIN FUNCTION Figure ...
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CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Spaces PD780024AS, 780034AS Subseries can access 64 KB memory space respectively. Figures 3-1 to 3-5 show memory maps. Caution In case of the internal memory capacity, the initial value of memory size switching register ...
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Figure 3-2. Memory Map ( PD780022AS, 780032AS) FFFFH FF00H General-purpose FEFFH FEE0H FEDFH Internal high-speed RAM FD00H FCFFH Data memory space 4000H 3FFFH Program memory space 0000H 40 CHAPTER 3 CPU ARCHITECTURE Special function registers (SFRs) 256 8 bits registers ...
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Figure 3-3. Memory Map ( PD780023AS, 780033AS) FFFFH Special function registers (SFRs) FF00H General-purpose FEFFH registers FEE0H 32 FEDFH Internal high-speed RAM FB00H FAFFH Data memory space 6000H 5FFFH Program memory 24576 space 0000H CHAPTER 3 CPU ARCHITECTURE 256 8 ...
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Figure 3-4. Memory Map ( PD780024AS, 780034AS) FFFFH FF00H General-purpose FEFFH FEE0H FEDFH Internal high-speed RAM FB00H FAFFH Data memory space 8000H 7FFFH Program memory space 0000H 42 CHAPTER 3 CPU ARCHITECTURE Special function registers (SFRs) 256 8 bits registers ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map ( PD78F0034BS) FFFFH Special function registers (SFRs) FF00H General-purpose FEFFH registers FEE0H 32 FEDFH Internal high-speed RAM FB00H FAFFH Data memory space 8000H 7FFFH Program Flash memory memory 32768 space 0000H 256 ...
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Internal program memory space The internal program memory space contains the program and table data. Normally addressed with the program counter (PC). The PD780024AS, 780034AS Subseries products incorporate an on-chip ROM (mask ROM or flash memory), as ...
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Internal data memory space The PD780024AS, 780034AS Subseries products incorporate an internal high-speed RAM, as listed below. Table 3-3. Internal High-Speed RAM Capacity Part Number PD780021AS, 780031AS PD780022AS, 780032AS PD780023AS, 780033AS PD780024AS, 780034AS PD78F0034BS The 32-byte area FEE0H to ...
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Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Correspondence Between Data Memory and Addressing ( PD780022AS, 780032AS) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 512 8 bits ...
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Figure 3-8. Correspondence Between Data Memory and Addressing ( PD780023AS, 780033AS) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Correspondence Between Data Memory and Addressing ( PD780024AS, 780034AS) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 8 bits ...
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Figure 3-10. Correspondence Between Data Memory and Addressing ( PD78F0034BS) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH Reserved ...
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Processor Registers The PD780024AS, 780034AS Subseries products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word ...
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Auxiliary carry flag (AC) If the operation result has a carry from bit borrow at bit 3, this flag is set (1 reset (0) in all other cases. (e) In-service priority flag (ISP) This ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-14. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP is FEE0H) SP FEE0H FEE0H FEDFH SP FEDEH FEDEH (b) CALL, CALLF, CALL instructions (when SP is FEE0H) SP FEE0H FEE0H ...
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Figure 3-15. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP is FEDEH FEDEH (b) RET instruction (when SP is FEDEH FEDEH (c) RETI, RETB instructions (when SP is FEDDH) SP FEE0H ...
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General-purpose registers A general-purpose register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers ( and H). Each ...
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Special function register (SFR) Unlike a general-purpose register, each special function register has special functions allocated in the FF00H to FFFFH area. The special function register can be manipulated like the general-purpose register, with the operation, transfer ...
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Table 3-5. Special Function Register List (1/2) Address Special Function Register (SFR) Name FF00H Port 0 FF01H Port 1 FF02H Port 2 FF03H Port 3 FF04H Port 4 FF05H Port 5 FF07H Port 7 FF0AH 16-bit timer capture/compare register 00 ...
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Table 3-5. Special Function Register List (2/2) Address Special Function Register (SFR) Name FF47H Memory expansion mode register FF48H External interrupt rising edge enable register FF49H External interrupt falling edge enable register FF60H 16-bit timer mode control register 0 FF61H ...
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Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and ...
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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits the immediate data of an operation code are transferred to the program counter (PC) and branched. This ...
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... ROR4/ROL4 A register for storage of digit data which undergoes digit rotation [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing ...
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Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register specify code (Rn and RPn instruction word in the registered bank specified with the register bank select flag (RBS0 and ...
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Direct addressing [Function] The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [Operand format] [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration] 7 addr16 (lower) ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. An internal RAM and a ...
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Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the ...
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Register indirect addressing [Function] Register pair contents specified with a register pair specify code in an instruction word of the register bank specified with a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing ...
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Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flag ...
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Based indexed addressing [Function] The register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with ...
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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation ...
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CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD780024AS, 780034AS Subseries products incorporate four input ports and 35 I/O ports. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out ...
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Pin Name P00 Port 0 4-bit I/O port. P01 Input/output mode can be specified in 1-bit units. P02 An on-chip pull-up resistor can be used by software settings. P03 P10 to P13 Port 1 4-bit input-only port. P20 Port 2 ...
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Configuration of Ports A port includes the following hardware. Item Control register Port Pull-up resistor 4.2.1 Port 0 Port 4-bit I/O port with output latch. P00 to P03 pins can specify the input mode/output mode in ...
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Figure 4-2. Block Diagram of P00 to P03 WR PU PU00 to PU03 Alternate function RD WR PORT Output latch (P00 to P03 PM00 to PM03 PU: Pull-up resistor option register PM: Port mode register RD: Port 0 ...
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Port 1 Port 4-bit input-only port. This port can also be used as an A/D converter analog input. Figure 4-3 shows a block diagram of port 1. Figure 4-3. Block Diagram of P10 to P13 RD ...
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Port 2 Port 6-bit I/O port with output latch. P20 to P25 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). An on-chip pull-up resistor of P20 to ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P21 and P24 WR PU PU21, PU24 RD WR PORT Output latch (P21, P24 PM21, PM24 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port ...
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WR PU PU22 Alternate function RD WR PORT Output latch (P22 PM22 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal 78 CHAPTER 4 PORT FUNCTIONS ...
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Port 3 Port 3-bit I/O port with output latch. P34 to P36 pins can specify the input mode/output mode in 1-bit units with port mode register 3 (PM3). Use of an on-chip pull-up resistor can be ...
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WR PU PU35 RD WR PORT Output latch (P35 PM35 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal 80 CHAPTER 4 PORT FUNCTIONS Figure 4-8. ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P36 WR PU PU36 Alternate function RD WR PORT Output latch (P36 PM36 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 3 read signal ...
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Port 4 Port 8-bit I/O port with output latch. The P40 to P47 pins can specify the input mode/output mode in 1- bit units with port mode register 4 (PM4). An on-chip pull-up resistor of P40 ...
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Port 5 Port 8-bit I/O port with output latch. The P50 to P57 pins can specify the input mode/output mode in 1- bit units with port mode register 5 (PM5). An on-chip pull-up resistor of P50 ...
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Port 7 Port 6-bit I/O port with output latch. The P70 to P75 pins can specify the input mode/output mode in 1-bit units with port mode register 7 (PM7). An on-chip pull-up resistor of P70 to ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P71 WR PU PU71 Alternate function RD WR PORT Output latch (P71 PM71 PU: Pull-up resistor option register PM: Port mode register RD: Port 7 read signal WR: Port ...
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Figure 4-15. Block Diagram of P74 and P75 WR PU PU74, PU75 RD WR PORT Output latch (P74, P75 PM74, PM75 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 7 read signal WR: ...
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Registers Controlling Port Function The following two types of registers are used to control the ports. • Port mode registers (PM0, PM2 to PM5, PM7) • Pull-up resistor option registers (PU0, PU2 to PU5, PU7) (1) Port mode registers ...
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Figure 4-16. Format of Port Mode Register (PM0, PM2 to PM5, PM7) Address: FF20H After reset: FFH Symbol 7 6 PM0 1 1 Address: FF22H After reset: FFH Symbol 7 6 PM2 1 1 Address: FF23H After reset: FFH Symbol ...
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Table 4-3. Port Mode Registers and Output Latch Settings When Alternate Function Is Used Pin Name P00 to P02 INTP0 to INTP2 P03 INTP3 ADTRG P10 to P13 ANI0 to ANI3 P20 SI30 P21 SO30 P22 SCK30 P23 RxD0 P24 ...
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... RESET input clears these registers to 00H. Cautions 1. The P10 to P13 pins do not incorporate a pull-up resistor. 2. When PUm is set to 1, the on-chip pull-up resistor is connected irrespective of the input/ output mode. When using in output mode, therefore, set the bit of PUm ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-17. Format of Pull-up Resistor Option Register (PU0, PU2 to PU5, PU7) Address: FF30H After reset: 00H R/W Symbol 7 6 PU0 0 0 Address: FF32H After reset: 00H R/W Symbol 7 6 PU2 0 ...
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Operations of Port Function Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed ...
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CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This ...
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Figure 5-1. Block Diagram of Clock Generator FRC Subsystem XT1 f XT clock oscillator XT2 Main system X1 clock f X2 oscillator X STOP 94 CHAPTER 5 CLOCK GENERATOR Internal bus Oscillation stabilization time select register (OSTS) OSTS2 OSTS1 OSTS0 ...
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Registers Controlling Clock Generator The clock generator is controlled by the following two registers. • Processor clock control register (PCC) • Oscillation stabilization time select register (OSTS) (1) Processor clock control register (PCC) This register selects the CPU clock ...
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... A STOP instruction should not be used. 3. This bit can be set to 1 only when the subsystem clock is not used. Cautions 1. Be sure to set bit When the external clock is input, MCC should not be set. This is because the X2 pin is connected to V DD1 Remarks ...
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The fastest instructions of µ PD780024AS, 780034AS Subseries are carried out in two CPU clocks. The relationship between the CPU clock (f ) and minimum instruction execution time is shown in Table 5-2. CPU Table 5-2. Relationship Between CPU Clock ...
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... Do not execute the STOP instruction and do not set MCC (bit 7 of processor clock control register (PCC external clock is input. This is because when the STOP instruction or MCC is set to 1, the main system clock operation stops and the X2 pin is connected pull-up resistor. ...
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... Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (32.768 kHz TYP.) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin and an inverted-phase clock signal to the XT2 pin. ...
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... Do not fetch signals from the oscillator. Take special note of the fact that the subsystem clock oscillator is a circuit with low-level amplification so that power consumption is maintained at low levels. Figure 5-6 shows examples of incorrect resonator connection. Figure 5-6. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring IC X2 ...
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... Cautions 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning. To prevent that from occurring recommended to wire X2 and XT1 so that they are not in parallel, and to connect the IC pin between X2 and XT1 directly to V CHAPTER 5 CLOCK GENERATOR (d) Current flowing through ground line of ...
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... In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. To minimize leakage current, the above internal feedback resistor can be removed by setting bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2 pins as described above. ...
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... MHz operation) can be selected by setting the PCC. (c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. To reduce current consumption in the STOP mode, the subsystem clock feedback resistor can be disconnected to stop the subsystem clock. ...
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Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee ...
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Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out. (a) The minimum instruction execution time remains constant (122 µ ...
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System clock and CPU clock switching procedure This section describes switching procedure between the system clock and CPU clock. Figure 5-9. System Clock and CPU Clock Switching V DD RESET Interrupt request signal System clock CPU clock <1> The ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.1 Functions of 16-Bit Timer/Event Counter 0 16-bit timer/event counter 0 has the following functions. (1) Interval timer 16-bit timer/event counter 0 generates interrupt requests at the preset time interval. • Number of counts: ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.2 Configuration of 16-Bit Timer/Event Counter 0 16-bit timer/event counter 0 includes the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 0 Item Timer counter 16-bit timer counter 0 (TM0) Register 16-bit timer ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (1) 16-bit timer counter 0 (TM0) TM0 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 CR00 is set by a 16-bit memory manipulation instruction. RESET input makes CR00 undefined. Cautions 1. Set CR00 to a value other than 0000H in the clear & start mode entered on a match ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.3 Registers Controlling 16-Bit Timer/Event Counter 0 The following six registers are used to control 16-bit timer/event counter 0. • 16-bit timer mode control register 0 (TMC0) • Capture/compare control register 0 (CRC0) • ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Cautions 1. To write different data to TMC0, stop the timer operation before writing. 2. The timer operation must be stopped before writing to bits other than the OVF0 flag. Remark TO0: Output pin ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (3) 16-bit timer output control register 0 (TOC0) This register controls the operation of the 16-bit timer/event counter 0 output controller. It sets R-S type flip-flop (LV0) set/reset, output inversion enable/disable, and 16-bit timer/event ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (4) Prescaler mode register 0 (PRM0) This register is used to set the 16-bit timer counter 0 (TM0) count clock and TI00, TI01 input valid edges. PRM0 is set by an 8-bit memory manipulation ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (5) Port mode register 7 (PM7) This register sets port 7 input/output in 1-bit units. When using the P70/TO0/TI00 pin for timer output, clear PM70 and the output latch of P70 to 0. When ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4 Operations of 16-Bit Timer/Event Counter 0 6.4.1 Operation as interval timer Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 6-7 allows operation as ...
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... TM0 continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after the CR00 change is smaller than that (N) before the change necessary to restart the timer after changing CR00. Figure 6-10. Timing After Change of Compare Register During Timer Count Operation ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI00/TO0/P70 pin with using 16-bit timer counter 0 (TM0). TM0 is incremented ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-12. External Event Counter Configuration Diagram Noise eliminator X Valid edge of TI00 Note OVF0 is 1 only when 16-bit timer capture/compare register 00 is set to FFFFH. Figure 6-13. ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4.3 Operation as pulse width measurement It is possible to measure the pulse width of the signals input to the TI00/TO0/P70 pin and TI01/P71 pin using 16-bit timer counter 0 (TM0). There are two ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-15. Configuration Diagram for Pulse Width Measurement with Free-Running Counter TI00/TO0/P70 Figure 6-16. Timing of Pulse Width Measurement Operation with Free-Running Counter and ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-17 possible to simultaneously measure the pulse ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-18. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock TM0 count value 0000H 0001H TI00 pin input CR01 capture value INTTM01 TI01 pin input CR00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-19 possible to measure the ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-20. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM0 count value 0000H 0001H TI00 pin input CR01 capture value CR00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-21. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register 0 (TMC0) TMC0 (b) Capture/compare control register 0 (CRC0) CRC0 0 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4.4 Operation as square-wave output A square wave with any selected frequency can be output at intervals determined by the count value preset to 16-bit timer capture/compare register 00 (CR00). The TO0 pin output ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4.5 Operation as PPG output Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 6-25 allows operation as PPG (Programmable Pulse Generator) output. In the ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-26. PPG Output Configuration Diagram 16-bit timer capture/compare Figure 6-27. PPG Output Operation Timing t Count clock TM0 count value 0000H Count start ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.5 Program List Caution The following sample program is shown as an example to describe the operation of semiconductor products and their applications. information to your devices, design the devices after performing evaluation under ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.5.1 Interval timer /*******************************************************************************/ /* /* Setting example of timer 0 interval timer mode /* Cycle set to 130 as intervalTM0 (at 8.38 MHz for 1 ms) /* Variable ppgdata prepared as rewrite data ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.5.2 Pulse width measurement by free-running counter and one capture register /******************************************************************************/ /* /* Timer 0 operation sample /* Pulse width measurement example by free-running and CR01 /* Measurement results ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.5.3 Two pulse widths measurement by free-running counter /******************************************************************************/ /* /* Timer 0 operation sample /* Two-pulse-width measurement sample by free-running /* Measurement results bits and not checked for ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 /* INTTM00 interrupt function */ void intervalint() { unsigned int work; /******************************************************/ /* /* Define variables required for interrupt here /* /******************************************************/ work = CR00; data[4] = work - data[5]; data[5] = work; data[3] ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.5.4 Pulse width measurement by restart /**************************************************************************/ /* /* Timer 0 operation sample /* Pulse width measurement example by restart /* Measurement results bits, not to be checked for errors /* ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.5.5 PPG output /******************************************************************************/ /* /* Timer 0 PPG mode setting example /* Cycle set to 130 as intervalTM0 /* Active period set active_time /* Array ppgdata prepared as data area ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.6 Cautions for 16-Bit Timer/Event Counter 0 (1) Timer start errors An error one clock may occur in the time required for a match signal to be generated after timer start. ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (5) Operation of OVF0 flag <1> The OVF0 flag is also set the following case. Either of the clear & start mode entered on a match between TM0 and CR00, clear ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (8) Capture operation <1> If TI00 is specified as the valid edge of the count clock, a capture operation by the capture register specified as the trigger for TI00 is not possible. <2> If ...
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... Cycle: • Duty ratio: Set value of compare register/256 (2) Mode using cascade connection (16-bit resolution: cascade connection mode) The timer operates as a 16-bit timer/event counter by combining two 8-bit timer/event counters. It has the following functions. • Interval timer with 16-bit resolution • External event counter with 16-bit resolution • ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50 8-bit timer compare register 50 (CR50) Note 1 TI50/TO50/P72 8-bit timer ...
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... The counter is incremented in synchronization with the rising edge of the count clock. When TM50 and TM51 can be connected in cascade and used as a 16-bit timer, they can be read by a 16-bit memory manipulation instruction. However, since they are connected by an internal 8-bit bus, TM50 and TM51 are read separately twice in that order ...
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... Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand sure to set bits Remarks 1. When cascade connection is used, only TCL50 is valid for count clock setting Main system clock oscillation frequency X 3. Figures in parentheses are for operation with f ...
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... Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand sure to set bits Remarks 1. When cascade connection is used, only TCL50 is valid for count clock setting Main system clock oscillation frequency X 3. Figures in parentheses are for operation with f (2) 8-bit timer mode control register 5n (TMC5n TMC5n is a register that makes the following six settings ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 7-5. Format of 8-Bit Timer Mode Control Register 50 (TMC50) Address: FF70H After reset: 00H R/W Symbol <7> 6 TMC50 TCE50 TMC506 TCE50 0 After clearing to 0, count operation disabled (prescaler ...
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... After clearing to 0, count operation disabled (prescaler disabled) 1 Count operation start TMC516 0 Clear and start mode by match between TM51 and CR51 1 PWM (free-running) mode TMC514 0 Discrete mode 1 Cascade connection mode (TM50: Lower timer, TM51: Higher timer) LVS51 LVR51 other modes (TMC516 = 0) ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 (3) Port mode register 7 (PM7) This register sets port 7 input/output in 1-bit units. When using the P72/TO50/TI50 and P73/TI51/TO51 pins for timer output, set PM72, PM73, and the output latches of ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 7.4 Operations of 8-Bit Timer/Event Counters 50, 51 7.4.1 Operation as 8-bit interval timer The 8-bit timer/event counters operate as interval timers that generate interrupt requests repeatedly at intervals of the count value ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 7-8. Interval Timer Operation Timing (2/3) Count clock TM5n 00H CR5n TCE5n INTTM5n TO5n t Count clock TM5n 01H CR5n FFH TCE5n INTTM5n TO5n Remark (b) When ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 7-8. Interval Timer Operation Timing (3/3) (d) Operated by CR5n transition (M < N) Count clock TM5n N 00H CR5n TCE5n H INTTM5n TO5n (e) Operated by CR5n transition (M > N) ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to TI5n using 8-bit timer counter 5n (TM5n). TM5n is incremented each time ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 7.4.3 Operation as square-wave output (8-bit resolution) A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 7-10. Square-Wave Output Operation Timing Count clock TM5n count value 00H 01H 02H Count start CR5n N Note TO5n Note The TO5n output initial value can be set by bits 2 and ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 (1) PWM output basic operation [Setting] <1> Set each register. • Set port latches (P72, P73) • TCL5n: Count clock selection • CR5n: Compare value • TMC5n: Count operation stop, PWM mode selection, ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 Figure 7-11. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H CR5n N TCE5n INTTM5n TO5n Count clock TM5n 00H 01H FFH ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 (2) Operated by CR5n transition Figure 7-12. Timing of Operation by Change of CR5n (a) CR5n value is changed from when TM5n > CR5n Count clock TM5n N N+1 N+2 ...
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... TM51 → TMC51 = 0001×××0B ×: don’t care <2> When TMC51 is set to TCE51 = 1 and then TCE50 is set to TCE50 = 1, the count operation starts. <3> When the values of TM50 and CR50 of the cascade-connected timer match, INTTM50 of TM50 is generated (TM50 and TM51 are cleared to 00H). ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 7.5 Program List Caution The following sample program is shown as an example to describe the operation of semiconductor products and their applications. Therefore, when applying the following information to your devices, design ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 7.5.2 External event counter /***************************************************************/ /* /* Timer 50 operation sample /* Event counter setting example /* data: Count up flag /* /***************************************************************/ #pragma sfr #pragma EI #pragma DI #pragma interrupt INTTM50 intervalint ...
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... CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 7.5.3 Interval timer (16-bit) /***************************************************************/ /* /* Timer 5 operation sample /* Cascade connection setting example /* /***************************************************************/ #pragma sfr #pragma EI #pragma DI #define intervalTM5 130 #pragma interrupt INTTM50 ppgint rb2 unsigned char ppgdata[2]; void main(void) { int interval; interval = intervalTM5; PCC = 0x0; ppgdata[ ppgdata[ 0b11111011; ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51 7.6 Cautions for 8-Bit Timer/Event Counters 50, 51 (1) Timer start errors An error one clock may occur in the time required for a match signal to be generated after ...
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Functions of Watch Timer The watch timer has the following functions. (1) Watch timer When the main system clock or subsystem clock is used, interrupt requests (INTWT) are generated at 2 second intervals. (2) Interval timer Interrupt requests (INTWTI) ...
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Configuration of Watch Timer The watch timer includes the following hardware. Table 8-1. Configuration of Watch Timer Item Counter Prescaler Control register CHAPTER 8 WATCH TIMER Configuration 5 bits × bits × 1 Watch timer operation mode ...
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Register Controlling Watch Timer The watch timer operation mode register (WTM) is used to control the watch timer. • Watch timer operation mode register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and ...
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Operations of Watch Timer 8.4.1 Operation as watch timer The watch timer generates an interrupt request (INTWT specific time interval (2 main system clock or subsystem clock. The interrupt request is generated at the following time interval. ...
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Figure 8-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Start Count clock Watch timer interrupt INTWT Interval timer interrupt INTWTI Caution When operation of the watch timer and 5-bit counter is enabled by the ...
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CHAPTER 9 WATCHDOG TIMER 9.1 Functions of Watchdog Timer The watchdog timer has the following functions. (1) Watchdog timer The watchdog timer detects a program loop. Upon detection of a program loop, a non-maskable interrupt request or RESET can be ...
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Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 9-1. Configuration of Watchdog Timer Item Control registers 9.3 Registers Controlling Watchdog Timer The following two registers are used to control the watchdog timer. • Watchdog timer ...
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Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 9-3. Format of Watchdog Timer ...
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Operations of Watchdog Timer 9.4.1 Operation as watchdog timer When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any program loops. The program loop detection time ...
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Operation as interval timer The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to ...
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CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 10.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ICs. The clock selected with the clock ...
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CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 10.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 10-1. Configuration of Clock Output/Buzzer Output Controller Item Control registers 10.3 Registers Controlling Clock Output/Buzzer Output Controller ...
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CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 10-2. Format of Clock Output Select Register (CKS) Address: FF40H After reset: 00H R/W Symbol <7> 6 CKS BZOE BCS1 BZOE 0 Stop clock divider operation. BUZ fixed to low level. 1 Enable ...
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CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register (PM7) This register sets port 7 input/output in 1-bit units. When using the P74/PCL pin for clock output and the P75/BUZ pin for buzzer output, set PM74, PM75 and the ...
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CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 10.4 Operations of Clock Output/Buzzer Output Controller 10.4.1 Operation as clock output The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits (CCS0 ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.1 Functions of A/D Converter A/D converter is an 8-bit resolution converter that converts analog inputs into digital values. It can control analog input channels (ANI0 to ANI3). ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) Figure 11-1. Block Diagram of 8-Bit A/D Converter ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ADTRG/INTP3/P03 ADS01 ADS00 ADSC0 TRG0 FR02 FR01 FR00 EGA01 EGA00 Analog input channel specification register 0 (ADS0) Note The ...
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... A/D conversion. (4) Voltage comparator The voltage comparator compares the sampled analog input voltage to the series resistor string output voltage. (5) Series resistor string The series resistor string is connected between AV the analog input. Configuration 4 channels (ANI0 to ANI3) ...
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... Caution A series resistor string of several 10 kΩ is connected between the AV Therefore, when the output impedance of the reference voltage is too high, it seems as if the AV pin and the series resistor string are connected in series. This may cause a greater REF reference voltage error. (8) AV ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.3 Registers Controlling A/D Converter The following two registers are used to control the A/D converter. • A/D converter mode register 0 (ADM0) • Analog input channel specification register 0 (ADS0) ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) Caution When rewriting FR00 to FR02 to other than the same data, stop A/D conversion operations once prior to performing rewrite. Remarks Main system clock oscillation frequency X ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.4 Operations of A/D Converter 11.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with analog input channel specification register 0 (ADS0). <2> The voltage input to ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) Figure 11-4. Basic Operation of 8-Bit A/D Converter Setting ADCS0 to 1, external trigger, or overwriting ADS0 A/D conversion start delay time Sampling time A/D converter Sampling operation Undefined 80H SAR ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) Table 11-2. Sampling Time and A/D Conversion Start Delay Time of A/D Converter FR02 FR01 FR00 Conversion Time 144 120 96/f X ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in A/D ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.4.3 A/D converter operation mode Select one analog input channel from among ANI0 to ANI3 by analog input channel specification register 0 (ADS0) to start A/D conversion. A/D conversion can be ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) Figure 11-6. A/D Conversion by Hardware Start (When Falling Edge Is Specified) ADTRG ADM0 set ADCS0 = 1, TRG0 = 1 Standby A/D conversion state ADCR0 INTAD0 Remarks ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) (2) A/D conversion by software start When bit 6 (TRG0) and bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) are set to 0 and 1, respectively, A/D conversion of ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.5 How to Read A/D Converter Characteristics Table Here we will explain the special terms unique to A/D converters. (1) Resolution This is the minimum analog input voltage that can be ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) (4) Zero scale error This shows the difference between the actual measured value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0……000 to ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) (8) Conversion time This expresses the time from when the sampling was started to the time when the digital output was obtained. Sampling time is included in the conversion time in ...
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CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) 11.6 Cautions for A/D Converter (1) Power consumption in standby mode A/D converter stops operating in the standby mode. At this time, power consumption can be reduced by clearing bit 7 ...
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... A series resistor string of several 10 kΩ is connected between the AV Therefore, when the output impedance of the reference voltage is too high, it seems as if the AV series resistor string are connected in series. This may cause a greater reference voltage error. (6) Interrupt request flag (ADIF0) The interrupt request flag (ADIF0) is not cleared even if analog input channel specification register 0 (ADS0) is changed ...
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... In particular, do not cross an analog signal line with a digital signal line, or wire an analog signal line in the vicinity of a digital signal line. Otherwise, the A/D conversion characteristics may be affected by the noise of the digital line. Connect AV and V at one location on the board where the voltages are stable. ...
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... REF Connect a capacitor to the AV REF has been stopped and then is started, the voltage applied to the AV accuracy of the A/D conversion to drop. To prevent this, also connect a capacitor to the AV Figure 11-19 shows an example of connecting a capacitor. Figure 11-19. Example of Connecting Capacitor Remark C1: 4.7 µ µ F (reference value) C2: 0.01 µ ...
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... Figure 11-20 shows the internal equivalent circuit of the ANI0 to ANI3 pins. If the impedance of the signal source is high, connect capacitors with a high capacitance to the pins ANI0 to ANI3. An example of this is shown in Figure 11-21. In this case, however, the microcontroller cannot follow an analog signal with a high differential coefficient because a lowpass filter is created ...
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... CHAPTER 11 8-BIT A/D CONVERTER ( µ PD780024AS SUBSERIES) Figure 11-21. Example of Connection When Signal Source Impedance Is High Reference <Sensor internal circuit> voltage input Output impedance of sensor R0 C0 ≤ 0.1 F µ Lowpass filter is created. Remark (14) Input impedance of ANI0 to ANI3 pins This A/D converter executes sampling by charging the internal sampling capacitor for approximately 1/10 of the conversion time ...
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CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) 12.1 Functions of A/D Converter A/D converter is a 10-bit resolution converter that converts analog inputs into digital signals. It can control analog input channels (ANI0 to ANI3). ...
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CHAPTER 12 10-BIT A/D CONVERTER ( µ PD780034AS SUBSERIES) Figure 12-1. Block Diagram of 10-Bit A/D Converter ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ADTRG/INTP3/P03 ADS01 ADS00 ADCS0 TRG0 FR02 FR01 FR00 EGA01 EGA00 Analog input channel specification register 0 (ADS0) Note The ...