UPD78F0034AGK-8A8 NEC, UPD78F0034AGK-8A8 Datasheet

no-image

UPD78F0034AGK-8A8

Manufacturer Part Number
UPD78F0034AGK-8A8
Description
8-bit CMOS single-chip microcomputer
Manufacturer
NEC
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0034AGK-8A8
Manufacturer:
NEC
Quantity:
1 864
Part Number:
UPD78F0034AGK-8A8
Manufacturer:
NEC
Quantity:
1 000
User’s Manual
78K/0 Series
Instructions
Common to 78K/0 Series
Document No.
U12326EJ4V0UM00 (4th edition)
Date Published October 2001 N CP(K)
©
1995
Printed in Japan

Related parts for UPD78F0034AGK-8A8

UPD78F0034AGK-8A8 Summary of contents

Page 1

User’s Manual 78K/0 Series Instructions Common to 78K/0 Series Document No. U12326EJ4V0UM00 (4th edition) Date Published October 2001 N CP(K) © 1995 Printed in Japan ...

Page 2

User's Manual U12326EJ4V0UM ...

Page 3

... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...

Page 4

... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • ...

Page 5

... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • ...

Page 6

Page Throughout 6 Major Revisions in This Edition Description Deletion of all information except for information common to the 78K/0 Series (for individual product information, refer to the user’s manual of each product). The mark shows major revised points. User's ...

Page 7

Target Readers This manual is intended for users who wish to understand the functions of 78K/0 Series products and to design and develop its application systems and programs. Purpose This manual is intended to give users an understanding of the ...

Page 8

Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Documents Common to 78K/0 Series User’s Manual Instructions Note Application Note Basic I Basic II Basic III Note ...

Page 9

CHAPTER 1 MEMORY SPACE ............................................................................................................... 12 1.1 Memory Spaces ................................................................................................................12 1.2 Internal Program Memory (Internal ROM) Space .......................................................... 12 1.3 Vector Table Area ............................................................................................................. 12 1.4 CALLT Instruction Table Area ......................................................................................... 12 1.5 CALLF Instruction Entry Area ......................................................................................... 12 1.6 ...

Page 10

CHAPTER 5 EXPLANATION OF INSTRUCTIONS ................................................................................. 46 5.1 8-Bit Data Transfer Instructions ...................................................................................... 48 5.2 16-Bit Data Transfer Instructions .................................................................................... 51 5.3 8-Bit Operation Instructions ............................................................................................ 54 5.4 16-Bit Operation Instructions .......................................................................................... 63 5.5 Multiply/Divide Instructions ............................................................................................ 67 5.6 Increment/Decrement ...

Page 11

Figure No. 2-1 Program Counter Configuration .............................................................................................................. 14 2-2 Program Status Word Configuration ....................................................................................................... 14 2-3 Stack Pointer Configuration .................................................................................................................... 16 2-4 Data to Be Saved to Stack Memory ....................................................................................................... 16 2-5 Data to Be Reset from Stack Memory .................................................................................................... ...

Page 12

Memory Spaces The 78K/0 Series product program memory map varies depending on the internal memory capacity. For details of memory-mapped address area, refer to the user’s manual of each product. 1.2 Internal Program Memory (Internal ROM) Space Each 78K/0 ...

Page 13

RAM for VFD display There are some products in the 78K/0 Series to which RAM for VFD display is allocated. This RAM can also be used as an ordinary RAM area. (4) Internal expansion RAM There are some products ...

Page 14

Control Registers The control registers control the program sequence, statuses and stack memory. A program counter, a program status word and a stack pointer are the control registers. 2.1.1 Program counter (PC) The program counter is a 16-bit register ...

Page 15

Interrupt enable flag (IE) This flag controls the interrupt request acknowledgement operations of the CPU. When the IE flag is set to interrupt disable (DI), and interrupts other than non-maskable interrupts are all disabled. When IE ...

Page 16

Stack pointer (SP) This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 2-3. Stack Pointer Configuration 15 The SP ...

Page 17

General-Purpose Registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. These registers consist of 4 banks, each bank consisting of eight 8-bit registers ( and H). In ...

Page 18

Figure 2-6. General-Purpose Register Configuration FEFFH BANK0 FEF8H FEF7H BANK1 FEF0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H FEFFH BANK0 FEF8H FEF7H BANK1 FEF0H FEEFH BANK2 FEE8H FEE7H BANK3 FEE0H 18 CHAPTER 2 REGISTERS (a) Absolute names 16-bit processing RP3 RP2 ...

Page 19

Special Function Registers (SFRs) Unlike a general-purpose register, each special-function register has a special function. Special function registers are allocated in the 256-byte area FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, by operation, transfer ...

Page 20

Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another ...

Page 21

Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the “CALL !addr16” or “BR !addr16” or “CALLF !addr11” instruction is executed. The CALL !addr16 ...

Page 22

Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower-5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and ...

Page 23

Register addressing [Function] The register pair (AX) contents to be specified by an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the “BR AX” instruction is executed. [Illustration ...

Page 24

... A register for storage of digit data that undergoes digit rotation [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of the A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing ...

Page 25

Register addressing [Function] Register addressing accesses a general-purpose register as an operand. The general-purpose register to be accessed is specified by the register bank selection flags (RBS0 and RBS1) and the register specification codes (Rn and RPn) in the ...

Page 26

Direct addressing [Function] Direct addressing directly addresses the memory indicated by the immediate data in the instruction word. [Operand format] Identifier addr16 Label or 16-bit immediate data [Description example] MOV A, !FE00H; When setting !addr16 to FE00H Instruction code ...

Page 27

Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte fixed space FE20H to FF1FH. An internal high-speed RAM ...

Page 28

Special-function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs ...

Page 29

Register indirect addressing [Function] Register indirect addressing addresses memory with register pair contents specified as an operand. The register pair to be accessed is specified by the register bank selection flags (RBS0 and RBS1) and the register pair specification ...

Page 30

Based addressing [Function] 8-bit immediate data is added to the contents of the HL register pair as a base register and the sum is used to address the memory. The HL register pair to be accessed is in the ...

Page 31

Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN instructions are executed or the register is saved/reset upon generation ...

Page 32

This chapter lists the instructions in the 78K/0 Series instruction set. The instructions are common to all 78K/0 Series products. 4.1 Operation For the operation list for each product, refer to the user’s manual of each product. 4.1.1 Operand identifiers ...

Page 33

Description of “operation” column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register ...

Page 34

Description of number of clocks 1 instruction clock cycle is 1 CPU clock cycle (f 4.1.5 Instructions listed by addressing type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ...

Page 35

Operand #byte A r 1st Operand A ADD MOV ADDC XCH SUB ADD SUBC ADDC AND SUB OR SUBC XOR AND CMP OR XOR CMP r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP B, C sfr ...

Page 36

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word 1st Operand AX ADDW SUBW CMPW rp MOVW MOVW sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW SP MOVW MOVW Note Only when rp = ...

Page 37

Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ 2nd Operand 1st Operand Basic Instructions Compound Instructions (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP CHAPTER ...

Page 38

Instruction Codes 4.2.1 Description of instruction code table reg ...

Page 39

Instruction code list Instruction Mnemonic Operands Group 8-Bit Data MOV r,#byte Transfer saddr,#byte sfr,#byte Note A,r Note r,A A,saddr saddr,A A,sfr sfr,A A,!addr16 !addr16,A PSW,#byte A,PSW PSW,A A,[DE] [DE],A A,[HL] [HL],A A,[HL+byte] [HL+byte],A A,[HL+B] [HL+B],A A,[HL+C] [HL+C],A Note XCH ...

Page 40

Instruction Mnemonic Operands Group 16-Bit Data MOVW rp,#word Transfer saddrp,#word sfrp,#word AX,saddrp saddrp,AX AX,sfrp sfrp,AX Note 1 AX,rp Note 1 rp,AX AX,!addr16 !addr16,AX Note 1 XCHW AX,rp 8-Bit ADD A,#byte Operation saddr,#byte Note 2 A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] ...

Page 41

Instruction Mnemonic Operands Group 8-Bit SUB A,#byte Operation saddr,#byte Note A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C] SUBC A,#byte saddr,#byte Note A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C] AND A,#byte saddr,#byte Note A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] ...

Page 42

Instruction Mnemonic Operands Group 8-Bit OR A,#byte Operation saddr,#byte Note A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C] XOR A,#byte saddr,#byte Note A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] A,[HL+B] A,[HL+C] CMP A,#byte saddr,#byte Note A,r r,A A,saddr A,!addr16 A,[HL] A,[HL+byte] ...

Page 43

Instruction Mnemonic Operands Group 16-Bit ADDW AX,#word Operation SUBW AX,#word CMPW AX,#word Multiply/ MULU X divide DIVUW C Increment/ INC r decrement saddr DEC r saddr INCW rp DECW rp Rotate ROR A,1 ROL A,1 RORC A,1 ROLC A,1 ROR4 ...

Page 44

Instruction Mnemonic Operands Group Bit OR1 CY,saddr.bit Manipulation CY,sfr.bit CY,A.bit CY,PSW.bit CY,[HL].bit XOR1 CY,saddr.bit CY,sfr.bit CY,A.bit CY,PSW.bit CY,[HL].bit SET1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit SET1 CY CLR1 CY NOT1 CY Call Return CALL !addr16 ...

Page 45

Instruction Mnemonic Operands Group Unconditional BR !addr16 Branch $addr16 AX Conditional BC $addr16 Branch BNC $addr16 BZ $addr16 BNZ $addr16 BT saddr.bit,$addr16 1 B sfr.bit,$addr16 A.bit,$addr16 PSW.bit,$addr16 [HL].bit,$addr16 BF saddr.bit,$addr16 ...

Page 46

CHAPTER 5 This chapter explains the instructions of 78K/0 Series products. Each instruction is described with a mnemonic, including description of multiple operands. The basic configuration of instruction description is shown on the next page. For the number of instruction ...

Page 47

CHAPTER 5 EXPLANATION OF INSTRUCTIONS Mnemonic MOV [Instruction format] MOV dst, src: Indicates the basic description format of the instruction. dst ← src: Indicates instruction operation using symbols. [Operation] [Operand] Indicates operands that can be specified by this instruction. Refer ...

Page 48

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.1 8-Bit Data Transfer Instructions The following instructions are 8-bit data transfer instructions. MOV ... 49 XCH ... 50 48 User's Manual U12326EJ4V0UM ...

Page 49

CHAPTER 5 EXPLANATION OF INSTRUCTIONS MOV [Instruction format] MOV dst, src dst ← src [Operation] [Operand] Mnemonic Operand(dst,src) MOV r, #byte saddr, #byte sfr, #byte saddr saddr sfr sfr !addr16 !addr16, ...

Page 50

CHAPTER 5 EXPLANATION OF INSTRUCTIONS XCH [Instruction format] XCH dst, src dst ↔ src [Operation] [Operand] Mnemonic Operand(dst,src) XCH saddr A, sfr A, !addr16 A, [DE] Note Except [Flag [Description] • ...

Page 51

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.2 16-Bit Data Transfer Instructions The following instructions are 16-bit data transfer instructions. MOVW ... 52 XCHW ... 53 User's Manual U12326EJ4V0UM 51 ...

Page 52

CHAPTER 5 EXPLANATION OF INSTRUCTIONS MOVW [Instruction format] MOVW dst, src dst ← src [Operation] [Operand] Mnemonic Operand(dst,src) MOVW rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX AX, sfrp Note Only when ...

Page 53

CHAPTER 5 EXPLANATION OF INSTRUCTIONS XCHW [Instruction format] XCHW dst, src dst ↔ src [Operation] [Operand] Mnemonic Operand(dst,src) XCHW AX, rp Note Only when [Flag [Description] • The 1st and 2nd ...

Page 54

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.3 8-Bit Operation Instructions The following are 8-bit operation instructions. ADD ... 55 ADDC ... 56 SUB ... 57 SUBC ... 58 AND ... 59 OR ... 60 XOR ... 61 CMP ... 62 54 ...

Page 55

CHAPTER 5 EXPLANATION OF INSTRUCTIONS ADD [Instruction format] ADD dst, src dst, CY ← dst + src [Operation] [Operand] Mnemonic Operand(dst,src) ADD A, #byte saddr, #byte saddr Note Except [Flag ...

Page 56

CHAPTER 5 EXPLANATION OF INSTRUCTIONS ADDC [Instruction format] ADDC dst, src dst, CY ← dst + src + CY [Operation] [Operand] Mnemonic Operand(dst,src) ADDC A, #byte saddr, #byte saddr Note Except [Flag] ...

Page 57

CHAPTER 5 EXPLANATION OF INSTRUCTIONS SUB [Instruction format] SUB dst, src dst, CY ← dst – src [Operation] [Operand] Mnemonic Operand(dst,src) SUB A, #byte saddr, #byte saddr Note Except [Flag ...

Page 58

CHAPTER 5 EXPLANATION OF INSTRUCTIONS SUBC [Instruction format] SUBC dst, src dst, CY ← dst – src – CY [Operation] [Operand] Mnemonic Operand(dst,src) SUBC A, #byte saddr, #byte saddr Note Except [Flag] ...

Page 59

CHAPTER 5 EXPLANATION OF INSTRUCTIONS AND [Instruction format] AND dst, src dst ← dst ∧ src [Operation] [Operand] Mnemonic Operand(dst,src) AND A, #byte saddr, #byte saddr Note Except [Flag ...

Page 60

CHAPTER 5 EXPLANATION OF INSTRUCTIONS OR [Instruction format] OR dst, src dst ← dst ∨ src [Operation] [Operand] Mnemonic Operand(dst,src #byte saddr, #byte saddr Note Except [Flag ...

Page 61

CHAPTER 5 EXPLANATION OF INSTRUCTIONS XOR [Instruction format] XOR dst, src dst ← dst ∨ src [Operation] [Operand] Mnemonic Operand(dst,src) XOR A, #byte saddr, #byte saddr Note Except [Flag ...

Page 62

CHAPTER 5 EXPLANATION OF INSTRUCTIONS CMP [Instruction format] CMP dst, src [Operation] dst – src [Operand] Mnemonic Operand(dst,src) CMP A, #byte saddr, #byte saddr Note Except [Flag × × ...

Page 63

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.4 16-Bit Operation Instructions The following are 16-bit operation instructions. ADDW ... 64 SUBW ... 65 CMPW ... 66 User's Manual U12326EJ4V0UM 63 ...

Page 64

CHAPTER 5 EXPLANATION OF INSTRUCTIONS ADDW [Instruction format] ADDW dst, src dst, CY ← dst + src [Operation] [Operand] Mnemonic Operand(dst,src) ADDW AX, #word [Flag × × × [Description] • The destination operand (dst) specified by the ...

Page 65

CHAPTER 5 EXPLANATION OF INSTRUCTIONS SUBW [Instruction format] SUBW dst, src dst, CY ← dst – src [Operation] [Operand] Mnemonic Operand(dst,src) SUBW AX, #word [Flag × × × [Description] • The source operand (src) specified by the ...

Page 66

CHAPTER 5 EXPLANATION OF INSTRUCTIONS CMPW [Instruction format] CMPW dst, src [Operation] dst – src [Operand] Mnemonic Operand(dst,src) CMPW AX, #word [Flag × × × [Description] • The source operand (src) specified by the 2nd operand is ...

Page 67

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.5 Multiply/Divide Instructions The following are multiply/divide instructions. MULU ... 68 DIVUW ... 69 User's Manual U12326EJ4V0UM 67 ...

Page 68

CHAPTER 5 EXPLANATION OF INSTRUCTIONS MULU [Instruction format] MULU src AX ← A × src [Operation] [Operand] Mnemonic Operand(src) MULU X [Flag [Description] • The A register contents and the source operand (src) data are multiplied as ...

Page 69

CHAPTER 5 EXPLANATION OF INSTRUCTIONS DIVUW [Instruction format] DIVUW dst AX (quotient), dst (remainder) ← AX [Operation] [Operand] Mnemonic Operand(dst) DIVUW C [Flag [Description] • The AX register contents are divided by the destination operand (dst) contents ...

Page 70

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.6 Increment/Decrement Instructions The following are increment/decrement instructions. INC ... 71 DEC ... 72 INCW ... 73 DECW ... 74 70 User's Manual U12326EJ4V0UM ...

Page 71

CHAPTER 5 EXPLANATION OF INSTRUCTIONS INC [Instruction format] INC dst dst ← dst + 1 [Operation] [Operand] Mnemonic Operand(dst) INC r saddr [Flag × × [Description] • The destination operand (dst) contents are incremented by only one. ...

Page 72

CHAPTER 5 EXPLANATION OF INSTRUCTIONS DEC [Instruction format] DEC dst dst ← dst – 1 [Operation] [Operand] Mnemonic Operand(dst) DEC r saddr [Flag × × [Description] • The destination operand (dst) contents are decremented by only one. ...

Page 73

CHAPTER 5 EXPLANATION OF INSTRUCTIONS INCW [Instruction format] INCW dst dst ← dst + 1 [Operation] [Operand] Mnemonic Operand(dst) INCW rp [Flag [Description] • The destination operand (dst) contents are incremented by only one. • Because this ...

Page 74

CHAPTER 5 EXPLANATION OF INSTRUCTIONS DECW [Instruction format] DECW dst dst ← dst – 1 [Operation] [Operand] Mnemonic Operand (dst) DECW rp [Flag [Description] • The destination operand (dst) contents are decremented by only one. • Because ...

Page 75

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.7 Rotate Instructions The following are rotate instructions. ROR ... 76 ROL ... 77 RORC ... 78 ROLC ... 79 ROR4 ... 80 ROL4 ... 81 User's Manual U12326EJ4V0UM 75 ...

Page 76

CHAPTER 5 EXPLANATION OF INSTRUCTIONS ROR [Instruction format] ROR dst, cnt [Operation] (CY, dst 7 [Operand] Mnemonic Operand(dst,cnt) ROR A, 1 [Flag × [Description] • The destination operand (dst) contents specified by the 1st operand are rotated ...

Page 77

CHAPTER 5 EXPLANATION OF INSTRUCTIONS ROL [Instruction format] ROL dst, cnt [Operation] (CY, dst 0 [Operand] Mnemonic Operand(dst,cnt) ROL A, 1 [Flag × [Description] • The destination operand (dst) contents specified by the 1st operand are rotated ...

Page 78

CHAPTER 5 EXPLANATION OF INSTRUCTIONS RORC [Instruction format] RORC dst, cnt (CY ← dst [Operation] [Operand] Mnemonic Operand(dst,cnt) RORC A, 1 [Flag × [Description] • The destination operand (dst) contents specified by the 1st operand are rotated ...

Page 79

CHAPTER 5 EXPLANATION OF INSTRUCTIONS ROLC [Instruction format] ROLC dst, cnt (CY ← dst [Operation] [Operand] Mnemonic Operand(dst,cnt) ROLC A, 1 [Flag × [Description] • The destination operand (dst) contents specified by the 1st operand are rotated ...

Page 80

CHAPTER 5 EXPLANATION OF INSTRUCTIONS ROR4 [Instruction format] ROR4 dst ← (dst) [Operation] A 3-0 [Operand] Mnemonic Operand(dst) ROR4 [HL] Note Specify an area other than the SFR area as operand [HL]. [Flag [Description] • The lower ...

Page 81

CHAPTER 5 EXPLANATION OF INSTRUCTIONS ROL4 [Instruction format] ROL4 dst ← (dst) [Operation] A 3-0 [Operand] Mnemonic Operand(dst) ROL4 [HL] Note Specify an area other than the SFR area as operand [HL]. [Flag [Description] • The lower ...

Page 82

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.8 BCD Adjust Instructions The following are BCD adjust instructions. ADJBA ... 83 ADJBS ... 84 82 User's Manual U12326EJ4V0UM ...

Page 83

CHAPTER 5 EXPLANATION OF INSTRUCTIONS ADJBA [Instruction format] ADJBA [Operation] Decimal Adjust Accumulator for Addition [Operand] None [Flag × × × [Description] • The A register, CY flag and AC flag are decimally adjusted from their contents. ...

Page 84

CHAPTER 5 EXPLANATION OF INSTRUCTIONS ADJBS [Instruction format] ADJBS [Operation] Decimal Adjust Accumulator for Subtraction [Operand] None [Flag × × × [Description] • The A register, CY flag and AC flag are decimally adjusted from their contents. ...

Page 85

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.9 Bit Manipulation Instructions The following are bit manipulation instructions. MOV1 ... 86 AND1 ... 87 OR1 ... 88 XOR1 ... 89 SET1 ... 90 CLR1 ... 91 NOT1 ... 92 User's Manual U12326EJ4V0UM 85 ...

Page 86

CHAPTER 5 EXPLANATION OF INSTRUCTIONS MOV1 [Instruction format] MOV1 dst, src dst ← src [Operation] [Operand] Mnemonic Operand(dst,src) MOV1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag] dst = × [Description] • Bit ...

Page 87

CHAPTER 5 EXPLANATION OF INSTRUCTIONS AND1 [Instruction format] AND1 dst, src dst ← dst ∧ src [Operation] [Operand] Mnemonic Operand(dst,src) AND1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag × [Description] • Logical product ...

Page 88

CHAPTER 5 EXPLANATION OF INSTRUCTIONS OR1 [Instruction format] OR1 dst, src dst ← dst ∨ src [Operation] [Operand] Mnemonic Operand(dst,src) OR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag × [Description] • The logical ...

Page 89

CHAPTER 5 EXPLANATION OF INSTRUCTIONS XOR1 [Instruction format] XOR1 dst, src dst ← dst ∨ src [Operation] [Operand] Mnemonic Operand(dst,src) XOR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag × [Description] • The exclusive ...

Page 90

CHAPTER 5 EXPLANATION OF INSTRUCTIONS SET1 [Instruction format] SET1 dst dst ←1 [Operation] [Operand] Mnemonic Operand(dst) SET1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit CY [Flag] dst = PSW.bit × × × [Description] • The destination operand (dst) is ...

Page 91

CHAPTER 5 EXPLANATION OF INSTRUCTIONS CLR1 [Instruction format] CLR1 dst dst ← 0 [Operation] [Operand] Mnemonic Operand(dst) CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit CY [Flag] dst = PSW.bit × × × [Description] • The destination operand (dst) ...

Page 92

CHAPTER 5 EXPLANATION OF INSTRUCTIONS NOT1 [Instruction format] NOT1 dst dst ← dst [Operation] [Operand] Mnemonic Operand(dst) NOT1 CY [Flag × [Description] • The CY flag is inverted. [Description example] NOT1 CY; The CY flag is inverted. ...

Page 93

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.10 Call Return Instructions The following are call return instructions. CALL ... 94 CALLF ... 95 CALLT ... 96 BRK ... 97 RET ... 98 RETI ... 99 RETB ... 100 User's Manual U12326EJ4V0UM 93 ...

Page 94

CHAPTER 5 EXPLANATION OF INSTRUCTIONS CALL [Instruction format] CALL target (SP–1) ← (PC+3) [Operation] (SP–2) ← (PC+3) ← SP–2, SP ← target PC [Operand] Mnemonic Operand(target) CALL !addr16 [Flag [Description] • This is a subroutine call with ...

Page 95

CHAPTER 5 EXPLANATION OF INSTRUCTIONS CALLF [Instruction format] CALLF Target (SP–1) ← (PC+2) [Operation] (SP–2) ← (PC+2) ← SP–2, SP ← target PC [Operand] Mnemonic Operand(target) CALLF !addr11 [Flag [Description] • This is a subroutine call which ...

Page 96

CHAPTER 5 EXPLANATION OF INSTRUCTIONS CALLT [Instruction format] CALLT [addr5] (SP–1) ← (PC+1) [Operation] (SP–2) ← (PC+1) ← SP–2, SP ← (00000000, addr5+ ← (00000000, addr5 [Operand] Mnemonic Operand([addr5]) CALLT [addr5] [Flag [Description] ...

Page 97

CHAPTER 5 EXPLANATION OF INSTRUCTIONS BRK [Instruction format] BRK (SP–1) ← PSW, [Operation] (SP–2) ← (PC+1) (SP–3) ← (PC+1) ← ← SP–3, SP ← (3FH ← (3EH [Operand] None [Flag [Description] ...

Page 98

CHAPTER 5 EXPLANATION OF INSTRUCTIONS RET [Instruction format] RET ← (SP), [Operation ← (SP+1 ← SP+2 [Operand] None [Flag [Description] • This is a return instruction from the subroutine call made with ...

Page 99

CHAPTER 5 EXPLANATION OF INSTRUCTIONS RETI [Instruction format] RETI ← (SP), [Operation ← (SP+1 PSW ← (SP+2), ← SP+3, SP NMIS ← 0 [Operand] None [Flag [Description] • This is ...

Page 100

CHAPTER 5 EXPLANATION OF INSTRUCTIONS RETB [Instruction format] RETB ← (SP), [Operation ← (SP+1 PSW ← (SP+2), ← SP+3 SP [Operand] None [Flag [Description] • This is a return instruction ...

Page 101

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.11 Stack Manipulation Instructions The following are stack manipulation instructions. PUSH ... 102 POP ... 103 MOVW SP, src ... 104 MOVW AX, SP ... 104 User's Manual U12326EJ4V0UM 101 ...

Page 102

CHAPTER 5 EXPLANATION OF INSTRUCTIONS PUSH [Instruction format] PUSH src [Operation] When src = rp (SP–1) ← src (SP–2) ← src ← SP–2 SP [Operand] Mnemonic Operand(src) PUSH PSW rp [Flag [Description] • The data of the ...

Page 103

CHAPTER 5 EXPLANATION OF INSTRUCTIONS POP [Instruction format] POP dst [Operation] When dst = rp ← (SP), dst L ← (SP+1), dst H SP ← SP+2 [Operand] Mnemonic Operand(dst) POP PSW rp [Flag] dst = [Description] • ...

Page 104

CHAPTER 5 EXPLANATION OF INSTRUCTIONS MOVW SP, src MOVW AX, SP [Instruction format] MOVW dst, src dst ← src [Operation] [Operand] Mnemonic Operand(dst,src) MOVW SP, #word SP, AX AX, SP [Flag [Description] • This is an instruction ...

Page 105

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.12 Unconditional Branch Instruction The unconditional branch instruction is shown below. BR ... 106 User's Manual U12326EJ4V0UM 105 ...

Page 106

CHAPTER 5 EXPLANATION OF INSTRUCTIONS BR [Instruction format] BR target PC ← target [Operation] [Operand] Mnemonic Operand(target) BR !addr16 AX $addr16 [Flag [Description] • This is an instruction to branch unconditionally. • The word data of the ...

Page 107

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.13 Conditional Branch Instructions Conditional branch instructions are shown below. BC ... 108 BNC ... 109 BZ ... 110 BNZ ... 111 BT ... 112 BF ... 113 BTCLR ... 114 DBNZ ... 115 User's ...

Page 108

CHAPTER 5 EXPLANATION OF INSTRUCTIONS BC [Instruction format] BC $addr16 PC ← PC+2+jdisp8 [Operation] [Operand] Mnemonic Operand($addr16) BC $addr16 [Flag [Description] • When data is branched to the address specified ...

Page 109

CHAPTER 5 EXPLANATION OF INSTRUCTIONS BNC [Instruction format] BNC $addr16 PC ← PC+2+jdisp8 [Operation] [Operand] Mnemonic Operand($addr16) BNC $addr16 [Flag [Description] • When data is branched to the address specified ...

Page 110

CHAPTER 5 EXPLANATION OF INSTRUCTIONS BZ [Instruction format] BZ $addr16 PC ← PC+2+jdisp8 [Operation] [Operand] Mnemonic Operand($addr16) BZ $addr16 [Flag [Description] • When data is branched to the address specified ...

Page 111

CHAPTER 5 EXPLANATION OF INSTRUCTIONS BNZ [Instruction format] BNZ $addr16 PC ← PC+2+jdisp8 [Operation] [Operand] Mnemonic Operand($addr16) BNZ $addr16 [Flag [Description] • When data is branched to the address specified ...

Page 112

CHAPTER 5 EXPLANATION OF INSTRUCTIONS BT [Instruction format] BT bit, $addr16 PC ← PC+b+jdisp8 if bit = 1 [Operation] [Operand] Mnemonic Operand(bit,$addr16) BT saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 [Flag [Description] • If ...

Page 113

CHAPTER 5 EXPLANATION OF INSTRUCTIONS BF [Instruction format] BF bit, $addr16 PC ← PC+b+jdisp8 if bit = 0 [Operation] [Operand] Mnemonic Operand(bit,$addr16) BF saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 [Flag [Description] • If ...

Page 114

CHAPTER 5 EXPLANATION OF INSTRUCTIONS BTCLR [Instruction format] BTCLR bit, $addr16 PC ← PC+b+jdisp8 if bit = 1, then bit ← 0 [Operation] [Operand] Mnemonic Operand(bit,$addr16) BTCLR saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 [Flag] bit =PSW.bit ...

Page 115

CHAPTER 5 EXPLANATION OF INSTRUCTIONS DBNZ [Instruction format] DBNZ dst, $addr16 dst ← dst–1, [Operation] then PC ← PC+b+jdisp16 if dst R1 [Operand] Mnemonic Operand(dst,$addr16) DBNZ B, $addr16 C, $addr16 saddr, $addr16 [Flag [Description] • One is ...

Page 116

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5.14 CPU Control Instructions The following are CPU control instructions. SEL RBn ... 117 NOP ... 118 EI ... 119 DI ... 120 HALT ... 121 STOP ... 122 116 User's Manual U12326EJ4V0UM ...

Page 117

CHAPTER 5 EXPLANATION OF INSTRUCTIONS SEL RBn [Instruction format] SEL RBn RBS0, RBS1 ← 0-3) [Operation] [Operand] Mnemonic Operand(RBn) SEL RBn [Flag [Description] • The register bank specified by the operand (RBn) is made ...

Page 118

CHAPTER 5 EXPLANATION OF INSTRUCTIONS NOP [Instruction format] NOP [Operation] no operation [Operand] None [Flag [Description] • Only the time is consumed without processing. 118 User's Manual U12326EJ4V0UM No Operation No Operation ...

Page 119

CHAPTER 5 EXPLANATION OF INSTRUCTIONS EI [Instruction format ← 1 [Operation] [Operand] None [Flag [Description] • The maskable interrupt acknowledgeable status is set (by setting the interrupt enable flag (IE) to (1)). • No interrupts ...

Page 120

CHAPTER 5 EXPLANATION OF INSTRUCTIONS DI [Instruction format ← 0 [Operation] [Operand] None [Flag [Description] • Maskable interrupt acknowledgment by vectored interrupt is disabled (with the interrupt enable flag (IE) cleared (0)). • No interrupts ...

Page 121

CHAPTER 5 EXPLANATION OF INSTRUCTIONS HALT [Instruction format] HALT [Operation] Set HALT Mode [Operand] None [Flag [Description] • This instruction is used to set the HALT mode to stop the CPU operation clock. The total power consumption ...

Page 122

CHAPTER 5 EXPLANATION OF INSTRUCTIONS STOP [Instruction format] STOP [Operation] Set STOP Mode [Operand] None [Flag [Description] • This instruction is used to set the STOP mode to stop the main system clock oscillator and to stop ...

Page 123

APPENDIX A The following table shows the revision history of the previous editions. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. Edition Major Revision from Previous Edition 2nd Addition of the following ...

Page 124

APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) [8-bit data transfer instructions] MOV ... 49 XCH ... 50 [16-bit data transfer instructions] MOVW ... 52 XCHW ... 53 [8-bit operation instructions] ADD ... 55 ADDC ... 56 SUB ... 57 SUBC ...

Page 125

APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) [Unconditional branch instruction] BR ... 106 [Conditional branch instructions] BC ... 108 BNC ... 109 BZ ... 110 BNZ ... 111 BT ... 112 BF ... 113 BTCLR ...114 DBNZ ... 115 [CPU ...

Page 126

APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) [A] ADD ... 55 ADDC ... 56 ADDW ... 64 ADJBA ... 83 ADJBS ... 84 AND ... 59 AND1 ... 87 [B] BC ... 108 BF ... 113 BNC ... 109 ...

Page 127

APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) [S] SEL RBn ... 117 SET1 ... 90 STOP ... 122 SUB ... 57 SUBC ... 58 SUBW ... 65 [X] XCH ... 50 XCHW ... 53 XOR ... 61 XOR1 ... ...

Page 128

User's Manual U12326EJ4V0UM ...

Page 129

... Fax: +82-2-528-4411 Taiwan NEC Electronics Taiwan Ltd. Fax: +886-2-2719-5951 Good Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation ...

Related keywords