UPD75P0016GB-3B4 NEC, UPD75P0016GB-3B4 Datasheet
UPD75P0016GB-3B4
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UPD75P0016GB-3B4 Summary of contents
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... V = 2 Supports QTOP™ microcontroller Remark QTOP Microcontroller is the general name for a total support service that includes imprinting, marking, screening, and verifying one-time PROM single-chip microcontrollers offered by NEC. ORDERING INFORMATION Part number PD75P0016CU PD75P0016GB-3BS-MTX Caution On-chip pull-up resistors by mask option cannot be provided. ...
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... In 8-bit operation banks 8 Connection of on-chip pull-up resistor specifiable by software Direct LED drive capability Connection of on-chip pull-up resistor specifiable by software Direct LED drive capability 13 V withstand voltage 34 4 channels • 8-bit timer/event counter: 1 channel • 8-bit timer counter: 1 channel • ...
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PIN CONFIGURATION ........................................................................................................................ 4 2. BLOCK DIAGRAM ............................................................................................................................. 6 3. PIN FUNCTIONS ................................................................................................................................ 7 3.1 Port Pins ..................................................................................................................................................... 7 3.2 Non-port Pins ............................................................................................................................................. 8 3.3 I/O Circuits for Pins ................................................................................................................................... 9 3.4 Handling of Unused Pins ........................................................................................................................ 11 4. ...
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... P12/INT2 P11/INT1 P10/INT0 PP Note Note Directly connect V 44-pin plastic QFP (10 10 mm, 0.8-mm pitch) PD75P0016GB-3BS-MTX P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 P53/D7 P52/D6 P51/D5 P50/D4 Note Directly connect P40/D0 3 P41/ P42/ P43/D3 6 P50/ P51/D5 ...
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... Port7 P80, P81 : Port8 KR0-KR7 : Key Return 0 Positive Power Supply Ground Programming Power Supply Connection SCK : Serial Clock SI : Serial Input SO : Serial Output SB0, SB1 : Serial Data Bus 0,1 RESET : Reset TI0 : Timer Input 0 PTO0, PTO1 : Programmable Timer Output 0, 1 BUZ ...
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BLOCK DIAGRAM BASIC INTERVAL TIMER/ WATCHDOG TIMER PROGRAM INTBT COUNTER (14) 8-BIT TI0/P13 TIMER/EVENT PTO0/P20 COUNTER #0 INTT0 TOUT0 8-BIT TIMER PTO1/P21 COUNTER #1 INTT1 PROGRAM SI/SB1/P03 MEMORY CLOCKED (PROM) SO/SB0/P02 SERIAL 16384 8 BITS INTERFACE SCK/P01 INTCSI TOUT0 ...
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... Low-level input current leakage increases when input instructions or bit manipulation instructions are executed. Function This is a 4-bit input port (PORT0). For P01 to P03, on-chip pull-up resistor connections are software-specifiable in 3-bit units. This is a 4-bit input port (PORT1). On-chip pull-up resistor connections are software- specifiable in 4-bit units ...
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... Data bus pin for program memory (PROM) write/verify. Programmable voltage supply in program memory (PROM) write/verify mode. In normal operation mode, connect directly to V Apply +12 PROM write/verify mode. Positive power supply Ground potential pin will not operate normally unless connected Data Sheet U10328EJ3V1DS00 PD75P0016 When I/O circuit Note 1 ...
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I/O Circuits for Pins The I/O circuits for the PD75P0016’s pin are shown in schematic diagrams below. TYPE P-ch IN N-ch CMOS standard input buffer TYPE B IN Schmitt trigger input with hysteresis characteristics. TYPE B-C ...
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TYPE F-B P.U.R. enable output V DD disable (P) data output disable output disable (N) P.U.R. : Pull-Up Resistor TYPE M-C P.U.R. enable data N-ch output disable P.U.R. : Pull-Up Resistor 10 TYPE M P.U.R. data output P-ch ...
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... Connect Input mode : individually connect via resistor Output mode : open Connect Input mode : individually connect via resistor Output mode : open Connect Open Make sure to connect directly Data Sheet U10328EJ3V1DS00 PD75P0016 ...
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SWITCHING BETWEEN MK I AND MK II MODES Setting a stack bank selection (SBS) register for the PD75P0016 enables the program memory to be switched between the Mk I mode and the Mk II mode. This capability enables the ...
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Setting of Stack Bank Selection (SBS) Register Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is ...
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... Mask options Pull-up resistor for Yes (On-chip/not on-chip can be specified.) port 4 and port 5 Wait time when Yes (2 RESET Feedback resistor Yes (can select usable or unusable.) for subsystem clock Pin connection Pins 6-9 (CU) P33-P30 Pins 23-26 (GB) Pin 20 (CU) IC Pin 38 (GB) Pins 34-37 (CU) P53-P50 Pins 8-11 (GB) ...
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MEMORY CONFIGURATION 7 6 0000H MBE RBE Internal reset start address (higher 6 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE INTBT/INT4 start address (higher 6 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE RBE ...
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General register Stack area Data area static RAM (512 4) Peripheral hardware area Note For the stack area, one memory bank can be selected from memory bank Figure 6-2. Data Memory Map Data memory 000H (32 ...
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INSTRUCTION SET (1) Representation and coding formats for operands In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s operand representations (for further description, refer to the RA75X Assembler Package User’s Manual ...
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Operation legend register; 4-bit accumulator register register register register register register register XA : Register ...
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Description of symbols used in addressing area MB = MBE • MBS *1 MBS = MBE = (000H-07FH (F80H-FFFH) *3 MBE = 1 : ...
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Description of machine cycles S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below. • No skip .......................................................................... • Skipped instruction is 1-byte or 2-byte ...
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Group Mnemonic Operand Transfer MOV reg1 XA HL rp2 @HL A, @HL+ A, @HL– A, @rpa1 XA, @HL @HL, A @HL mem XA, mem mem, A ...
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Group Mnemonic Operand Bit transfer MOV1 CY, fmem.bit CY, pmem.@L CY mem.bit fmem.bit, CY pmem.@ mem.bit, CY Operation ADDS A, #n4 XA, #n8 A, @HL XA, rp’ rp’1, XA ADDC A, @HL XA, rp’ rp’1, ...
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Group Mnemonic Operand Accumulator RORC A manipulate NOT A Increment/ INCS reg decrement rp1 @HL mem DECS reg rp’ Compare SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp’ Carry flag SET1 CY manipulate CLR1 CY ...
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Group Mnemonic Operand Memory bit SET1 mem.bit manipulate fmem.bit pmem.@ mem.bit CLR1 mem.bit fmem.bit pmem.@ mem.bit SKT mem.bit fmem.bit pmem.@ mem.bit SKF mem.bit fmem.bit pmem.@ mem.bit SKTCLR fmem.bit pmem.@ mem.bit ...
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Group Mnemonic Operand Note 1 Branch BR addr addr1 !addr $addr $addr1 PCDE PCXA BCDE BCXA Note 1 BRA !addr1 BRCB !caddr Notes 1. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the ...
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Group Mnemonic Operand Note Subroutine CALLA !addr1 stack control Note CALL !addr Note CALLF !faddr Note RET Note RETS Note RETI Note Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I ...
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Group Mnemonic Operand Subroutine PUSH rp stack control BS POP rp BS Interrupt EI control Note 1 I PORTn XA, PORTn Note 1 OUT PORTn, A PORTn, XA CPU control HALT STOP NOP Special SEL ...
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... D4/P50-D7/P53 (higher Caution Pins not used for program memory write/verify should be processed as follows. • All unused pins except XT2 ...... Connect to Vss via a pull-down resistor • XT2 pin ........................................ Leave open 8.1 Operation Modes for Program Memory Write/Verify When + applied to the PD75P0016’s V are in effect ...
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Steps in Program Memory Write Operation High-speed program memory write can be executed via the following steps. (1) Pull down unused pins (2) Apply + the V and V DD (3) Wait 10 s. ...
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Steps in Program Memory Read Operation The PD75P0016 can read out the program memory contents via the following steps. (1) Pull down unused pins to V via resistors. Set the X1 pin to low. SS (2) Apply +5 V ...
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... One-Time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends the screening process, that is, after the required data is written to the PROM and the PROM is stored under the high- temperature conditions shown below, the PROM should be verified. ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25˚C) A Parameter Symbol Supply voltage V DD PROM supply voltage V PP Input voltage V Other than port Port 4, 5 (N-ch open drain) I2 Output voltage ...
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Main System Clock Oscillation Circuit Characteristics (T Recommended Resonator constants Ceramic X1 X2 resonator C1 C2 Crystal resonator External clock X1 X2 Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of ...
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... Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency necessary to set the oscillation frequency of the resonator in the application circuit. For this necessary to directly contact the manufacturer of the resonator being used – ...
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DC Characteristics (T = – 85˚ Parameter Symbol Low-level I Per pin OL output current Total of all pins High-level input V Ports IH1 voltage V Ports RESET IH2 ...
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DC Characteristics (T = – 85˚ Parameter Symbol Note 1 Supply current I Note 2 6.0 MHz DD1 crystal oscillation DD2 I Note 2 4.19 MHz DD1 crystal oscillation ...
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... RESET low-level width t RSL Notes 1. The cycle time of the CPU clock ( ) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC), and processor clock control register (PCC). The figure on the right shows the supply voltage V operates with the main system clock ...
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Serial Transfer Operation 2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (T Parameter Symbol SCK cycle time t KCY1 SCK high-, low-level widths t , KL1 t KH1 Note 1 SI setup time t SIK1 (vs. SCK ...
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SBI mode (SCK ··· internal clock output (master)): (T Parameter Symbol SCK cycle time t KCY3 SCK high-, low-level widths t KL3 t KH3 SB0, 1 setup time t SIK3 (vs. SCK ) SB0, 1 hold time (vs. SCK ) ...
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AC Timing Test Points (except X1 and XT1 inputs) V (MIN (MAX (MIN (MAX.) OL Clock timing X1 input XT1 input TI0 timing TI0 40 V (MIN (MAX (MIN.) OH ...
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Serial Transfer Timing 3-wire serial I/O mode SCK SI SO 2-wire serial I/O mode SCK SB0 KCY1 KL1, 2 KH1 SIK1, 2 KSI1, 2 Input data t KSO1, 2 Output data t ...
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Serial Transfer Timing Bus release signal transfer SCK t t KSB SBL SB0, 1 Command signal transfer SCK t KSB SB0, 1 Interrupt input timing INT0 KR0-7 RESET input timing RESET 42 t KCY3 ...
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Data Retention Characteristics of Data Memory in STOP Mode and at Low Supply Voltage (T = –40 to +85˚C) A Parameter Symbol Release signal setup time t SREL Oscillation stabilization t WAIT Note 1 wait time Notes 1. The oscillation ...
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... MD3 hold time (vs. MD0 ) t M3HR MD3 data output float t DFR delay time Notes 1. Symbol of corresponding PD27C256A 2. The internal address signal is incremented by one at the rising edge of the fourth X1 input and is not connected to a pin 6.0 0. Conditions Other than X1, X2 pins X1, X2 ...
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Program Memory Write Timing t VPS VDS D0/P40-D3/P43 Data input D4/P50-D7/P53 MD0/P30 t PW MD1/P31 PCR ...
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CHARACTERISTICS CURVES (REFERENCE VALUE 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 (Main system clock : 6.0 MHz crystal resonator) DD PCC = 0011 PCC = 0010 PCC = 0001 ...
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(Main system clock : 4.19 MHz crystal resonator 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 Data Sheet U10328EJ3V1DS00 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 ...
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PACKAGE DRAWINGS 42PIN PLASTIC SHRINK DIP (600 mil NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to ...
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PIN PLASTIC QFP ( 10 NOTE Each lead centerline is located within 0.16 mm (0.007 inch) of its true position (T.P.) at maximum material condition ...
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... Solder the PD75P0016 under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 12-1. Soldering Conditions of Surface Mount Type PD75P0016GB-3BS-MTX: 44-pin plastic QFP (10 ...
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APPENDIX A. FUNCTION LIST OF PD75008, 750008, 75P0016 Item Program memory Mask ROM 0000H - 1F7FH (8064 Data memory 000H - 1FFH (512 CPU 75X Standard CPU General register 4 bits Instruction When main system • 0.95, 1.91, 15.3 s ...
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Item Serial interface Compatible with 3 kinds of mode • 3-wire serial I/O mode ... MSB/LSB-first can be switched • 2-wire serial I/O mode • SBI mode SOS register Feedback resistor On-chip feedback resistor cut flag (SOS.0) specifiable by mask ...
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APPENDIX B. DEVELOPMENT TOOLS The following development tools are provided for system development using the PD75P0016. The 75XL series uses a common relocatable assembler, in combination with a device file matching each machine. RA75X relocatable assembler Host machine PC-9800 series ...
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... PA-75P0016GB This is a PROM programmer adapter for the PD75P0016GB-3BS-MTX. It can be used when connected to a PG-1500. Software PG-1500 controller Establishes serial and parallel connections between the PG-1500 and a host machine for host- machine control of the PG-1500. Host machine PC-9800 Series IBM PC/AT or compatible Note Ver ...
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... PD750008 subseries, the IE-75000-R is used with a separately sold emulation board IE- 75300-R-EM and emulation probe EP-75008CU-R or EP-75008GB-R. These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer. The IE-75000-R can include a connected emulation board (IE-75000-R-EM). ...
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OS for IBM PCs The following operating systems for the IBM PC are supported. PC DOS MS-DOS IBM DOS Note Supports English version only. Caution Ver 5.0 and above include a task swapping function, but this software is not able ...
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... Document name SEMICONDUCTOR SELECTION GUIDE Products & Package (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices Electrostatic Discharge (ESD) Guide for Products Related to Microcomputer : Other Companies Caution The above related documents are subject to change without notice ...
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... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability Ordering information Product release schedule ...
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... The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...