NSC800N-3I National Semiconductor, NSC800N-3I Datasheet
NSC800N-3I
Related parts for NSC800N-3I
NSC800N-3I Summary of contents
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... C screening in accordance with Method 5004 of MIL-STD-883 Block Diagram NSC800 trademark of National Semiconductor Corp TRI-STATE is a registered trademark of National Semiconductor Corp Z80 is a registered trademark of Zilog Corp C 1995 National Semiconductor Corporation TL C 5171 Features Fully compatible with Z80 instruction set ...
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ABSOLUTE MAXIMUM RATINGS 2 0 OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS 5 0 TIMING WAVEFORMS NSC800 HARDWARE 6 0 PIN DESCRIPTIONS 6 1 Input Signals 6 2 Output Signals 6 3 Input ...
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... Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature b Voltage on Any Pin with Respect to Ground Maximum V CC Power Dissipation Lead Temp (Soldering 10 seconds Electrical Characteristics ...
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AC Electrical Characteristics NSC800-1 Symbol Parameter Min t Period at XIN and XOUT 500 X Pins T Period at Clock Output 1000 6667 400 6667 ( Clock Rise Time R t Clock ...
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AC Electrical Characteristics NSC800-1 Symbol Parameter Min T A(8–15) Hold Time During 0 H(ADH)1 Opcode Fetch T A(8–15) Hold Time During 400 H(ADH)2 Memory and WR T AD(0–7) Hold Time 100 H(ADL) T Write Data ...
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Timing Waveforms Opcode Fetch Cycle Memory Read and Write Cycle 5171 – 5171 – 4 ...
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Timing Waveforms (Continued) Note 1 This t state is the last t state of the last M cycle of any instruction Note 2 Response to INTR input Note 3 Response to PS input Waveform not drawn to proportion ...
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NSC800 HARDWARE 6 0 Pin Descriptions 6 1 INPUT SIGNALS Reset Input (RESET IN) Active low Sets A (8–15) and AD (0 –7) to TRI-STATE (high impedance) Clears the con- tents and R registers disables interrupts and ...
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Pin Descriptions (Continued) Status (SO S1) Bus status outputs provide encoded infor- mation regarding the current M cycle as follows Status Machine Cycle Opcode Fetch Memory Read Memory ...
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Functional Description This section reviews the CPU architecture shown below fo- cusing on the functional aspects from a hardware perspec- tive including timing details Note Applicable pinout for 40-pin dual-in-line package within parentheses FIGURE 1 NSC800 CPU Functional ...
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Functional Description 8 1 REGISTER ARRAY The NSC800 register array is divided into two parts the dedicated registers and the working registers as shown in Figure 2 Main Reg Set Alternate Reg Set Accumulator Flags Accumulator Flags A ...
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Functional Description 8 3 CPU WORKING AND ALTERNATE REGISTER SETS CPU Working Registers The portion of the register array shown in Figure 4b repre- sents the CPU working registers These sixteen 8-bit regis- ters are ...
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Functional Description Carry (C) A carry from the highest order bit of the accumulator during an add instruction or a borrow generated during a subtrac- tion instruction sets the carry flag Specific shift and rotate ...
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Functional Description Zero Flag (Z) Loading a zero in the accumulator or when a zero results from an operation sets the zero flag The following operations affect the zero flag Adds (16-bit with carry 8-bit ...
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Timing and Control 9 1 INTERNAL CLOCK GENERATOR An inverter oscillator contained on the NSC800 chip pro- vides all necessary timing signals The chip operation fre- quency is equal to one half of the frequency of this oscilla- ...
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Timing and Control (Continued CPU TIMING The NSC800 uses a multiplexed bus for data and address- es The 16-bit address bus is divided into a high-order 8-bit address bus that handles bits 8–15 of the address ...
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Timing and Control (Continued) During the opcode fetch the CPU places the contents of the PC on the address bus The falling edge of ALE indi- cates a valid address on the AD(0–7) lines The WAIT input is ...
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Timing and Control (Continued) Figure 10 shows the timing for memory read (other than opcode fetchs) and write cycles with and without a wait t state The RD stobe is widened by (half the machine 2 state) for ...
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Timing and Control (Continued INITIALIZATION RESET IN initializes the NSC800 RESET OUT initializes the peripheral components The Schmitt trigger at the RESET IN input facilitates using an R-C network reset scheme dur- ing power up (see ...
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Timing and Control (Continued during BREQ will indicate same machine cycle as during the cycle when BREQ was accepted t time states during which bus and control signals are in high impedance mode ...
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Timing and Control (Continued) Note 1 This is the only machine cycle that does not have INTA strobe but will accept a wait strobe FIGURE 16 Non-Maskable and Restart Interrupt Machine Cycle The NSC800 ...
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Timing and Control (Continued) A reset to the CPU will force both IFF and IFF 1 state disabling maskable interrupts They can be enabled instruction at any time by the programmer When an EI instruction ...
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Timing and Control (Continued) 23 ...
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Timing and Control (Continued) so that the complete state of the CPU just prior to the non- maskable interrupt may be restored The method of restor- ing the status of IFF is through the execution of a Return ...
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NSC800 SOFTWARE 10 0 Introduction This chapter provides the reader with a detailed description of the NSC800 software Each NSC800 instruction is de- scribed in terms of opcode function flags affected timing and addressing mode 11 0 Addressing Modes The ...
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Addressing Modes (Continued DIRECT ADDRESSING Direct addressing is the most straightforward way of ad- dressing supplies a location in the memory space Direct addressing 16-bits of memory address information in two bytes of data as part ...
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Addressing Modes (Continued MODIFIED PAGE ZERO A subset of NSC800 instructions (the Restart instructions) provides a code-efficient single-byte instruction that allows CALLs to be performed to any one of eight dedicated loca- tions in page zero ...
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Instruction Set This section details the entire NSC800 instruction set in terms of Opcode Instruction Function Timing Addressing Mode 12 1 Instruction Set Index Alphabetical Assembly Mnemonic ADC A m Add with carry memory location contents to Accumulator ...
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Instruction Set Index Alphabetical Assembly Mnemonic DI Disable interrupts DJNZ d Decrement B and jump relative B EI Enable interrupts EX (SP) ss Exchange the location (SP) with register A’F’ Exchange the contents of AF ...
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Instruction Set Index Alphabetical Assembly Mnemonic OR m Logical ‘OR’ of memory location contents and accumulator Logical ‘OR’ of immediate data n and Accumulator OR r Logical ‘OR’ of register r and Accumulator OTDR Load ...
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Instruction Set (Continued INSTRUCTION SET MNEMONIC NOTATION In the following instruction set listing the notations used are shown below b Designates one bit in a register or memory location Bit address mode uses this indicator cc ...
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Loads REGISTER TO REGISTER Load register r with flags affected ...
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Loads (Continued Load memory from the Accumulator flags affected (BC ...
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Loads REGISTER TO REGISTER Load 16-bit register pair with immediate data flags affected ...
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Loads (Continued) PUSH qq Push the contents of register pair qq onto the memory stack (SP – flags affected H (SP – PUSH ...
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Arithmetic REGISTER ADDRESSING ARITHMETIC Hex Hex Value Value Before Before Upper Lower DAA DAA Digit Digit (Bits 7-4) (Bits 3-0) 0 0-9 0 0-9 0 0-8 0 A-F 0 0-9 1 0-3 ...
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Arithmetic (Continued Timing M cycles 1 T states 4 Addressing Mode Source Register Destination Implied OR r Logically OR the contents of the ...
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Arithmetic (Continued Timing M cycles 1 T states 4 Addressing Mode Implied NEG Negate the Accumulator (2’s complement ...
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Arithmetic (Continued Timing M cycles 2 T states Addressing Mode Source Immediate Destination Implied SUB n Subtract ...
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Arithmetic (Continued Timing M cycles 2 T states Addressing Mode Source Immediate Destination Implied CP n Compare ...
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Arithmetic (Continued SUB (HL) Timing M cycles 2 T states Addressing Mode Source Register Indirect Destination Implied 7 ...
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Arithmetic (Continued) XOR m 1 The data in memory location m is exclusively OR’ed with 1 the data in the Accumulator Set if result is negative Set if result is ...
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Arithmetic (Continued DEC (HL) Timing M cycles 3 T states Addressing Mode Source Register Indexed Destination dexed ...
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Arithmetic (Continued) DEC rr Decrement the contents of the 16-bit register flags affected DEC BC DEC ...
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Bit Set Reset and Test BIT Bit b in memory location m is tested via the Z flag Undefined 1b Z Inverse of tested bit H Set P V Undefined N ...
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Rotate and Shift (Continued RRC (Note alternate for A register below) Timing M cycles 2 ...
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Rotate and Shift (Continued) MEMORY RLC m 1 Rotate date in memory location m left circular 1 S Set if result is negative Z Set if result is zero H Reset P V Set if result parity is ...
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Rotate and Shift (Continued Rotate the data in memory location m right through the 1 carry S Set if result is negative Z Set if result is zero H Reset P V Set if result ...
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Rotate and Shift (Continued SRL (HL Timing M cycles 4 T states 15 (4 ...
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Exchanges (Continued) EXX Exchange the contents of the BC DE and HL registers with their corresponding alternate register BC B’C’ No flags affected DE D’E’ HL H’L’ ...
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Memory Block Moves and Searches Timing M cycles 4 T states ...
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Input Output IN A (n) Input data to the Accumulator from the I O device at ad- dress N A (n) No flags affected ...
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Input Output (Continued) OUT (n) A Output the Accumulator to the I O device at address n ( flags affected ...
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Input Output (Continued) INDR Data is input from the I O device at address (C) to memory location (HL) then the HL memory pointer is byte counter B are decremented The cycle is repeated until B (Note that ...
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CPU Control (Continued The CPU is placed in interrupt mode 1 No flags affected ...
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Program Control (Continued) DJNZ d Decrement the B register and conditionally jump to program location calculated with respect to the program counter and the displacement d based on the contents of the B register ...
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Program Control (Continued) RETN Unconditional return from non-maskable interrupt handling subroutine Functionally similar to RET instruction except interrupt enable state is restored to that prior to non-mask- able interrupt PC (SP) No flags affected L PC (SP 1) ...
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Instruction Set Alphabetical Order ADC A (HL) 8E ADC A ( 8Ed a ADC A ( 8Ed a ADC ADC ADC ADC ...
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Instruction Set Alphabetical Order BIT BIT BIT BIT 6 (HL BIT 6 ( CBd76 a BIT 6 ( CBd76 a ...
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Instruction Set Alphabetical Order INIR (HL (IX (IY DAnn FAnn D2nn JP nn C3nn C2nn JP ...
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Instruction Set Alphabetical Order ...
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Instruction Set Alphabetical Order RES RES RES RES RES RES RES ...
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Instruction Set Alphabetical Order RRC RRC RRC RRC RRC RRC RRCA 0F RRD ED 67 RST 0 C7 RST 08H ...
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Instruction Set Alphabetical Order SET SET SET SET SET SET SLA (HL ...
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Instruction Set Numerical Order Op Code Mnemonic 3F CCF (HL) 47 ...
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Instruction Set Numerical Order Op Code Mnemonic CB13 RL E CB14 RL H CB15 RL L CB16 RL (HL) CB17 RL A CB18 RR B CB19 RR C CB1A RR D CB1B RR E CB1C RR H CB1D ...
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Instruction Set Numerical Order Op Code Mnemonic CBB7 RES 6 A CBB8 RES 7 B CBB9 RES 7 C CBBA RES 7 D CBBB RES 7 E CBBC RES 7 H CBBD RES 7 L CBBE RES 7 ...
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Instruction Set Numerical Order Op Code Mnemonic DDF9 DEn SCB RST 18H E0 RET PO E1 POP HL E2nn (SP) HL E4nn CALL PUSH ...
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Data Acquisition System A natural application for the NSC800 is one that requires remote operation Since power consumption is low if the system consists of only CMOS components the entire package can conceivably operate from only a battery ...
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Data Acquisition System (Continued) 70 ...
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Data Acquisition System ing When in the power-save mode the system power re- quirements are decreased by about 50% thus extending battery life Communication with the peripheral devices (MM58167 and ADC0816) is accomplished through the I O ports ...
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... NSC800M 883B MIL-STD-833 Class C Screening National Semiconductor offers the NSC800D and NSC800E with full class B screening per MIL-STD-883 for Military Aerospace programs requiring high reliability In addition this screening is available for all of the key NSC800 periph- eral devices Test Internal Visual ...
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Ordering Information NSC800 Note 1 Do not specify a temperature option all parts are screened to military temperature 17 0 Reliability Information Gate Count 2750 Transistor Count 11 000 Reliability Screening a ...
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... Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number NSC800N NS Package Number N40A Hermetic Dual-In-Line Package (D) Order Number NSC800D NS Package Number D40C 74 ...
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Physical Dimensions inches (millimeters) (Continued) Leadless Chip Carrier Package (E) Order Number NSC800E NS Package Number E44A 75 ...
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