FW82840 Intel Corporation, FW82840 Datasheet

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FW82840

Manufacturer Part Number
FW82840
Description
82840 Memory Controller Hub (MCH)
Manufacturer
Intel Corporation
Datasheet

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R
®
Intel
840 Chipset: 82840 Memory Controller
Hub (MCH)
Datasheet
September 2000
Document Number:
298020-002

Related parts for FW82840

FW82840 Summary of contents

Page 1

R ® Intel 840 Chipset: 82840 Memory Controller Hub (MCH) Datasheet September 2000 Document Number: 298020-002 ...

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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation www.intel.com or call 1-800-548-4725 *Third-party brands and names are the property of their respective owners. Copyright © Intel Corporation 2000 bus/protocol and was developed by Intel. Implementations Datasheet ...

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R Contents 1. Overview.....................................................................................................................................13 ® 1.1. Intel 840 Chipset System Architecture .........................................................................13 1.2. 82840 MCH Overview ....................................................................................................16 1.3. Terminology ...................................................................................................................18 2. Signal Description.......................................................................................................................21 2.1. Host Interface Signals ....................................................................................................22 2.2. Direct Rambus* Interface A ...........................................................................................24 2.3. Direct Rambus* Interface B ...........................................................................................25 ...

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DRD—RDRAM Device Register Data Register (Device 0) .............................. 59 3.4.21. RICM—RDRAM Initialization Control Management Register (Device 0).......... 59 3.4.22. MCH Expansion RAC A/B Configuration Registers .......................................... 61 3.4.23. SMRAM—System Management RAM Control Register (Device 0) ................ 61 3.4.24. ESMRAMC—Extended ...

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R 3.6. Hub interface B Bridge Registers (Device 2) .................................................................95 3.6.1. VID2—Vendor Identification Register (Device 2) ..............................................96 3.6.2. DID2—Device Identification Register (Device 2)...............................................96 3.6.3. PCICMD2—PCI-PCI Command Register (Device 2)........................................97 3.6.4. PCISTS2—PCI-PCI Status Register (Device 2)................................................98 3.6.5. RID2—Revision Identification Register (Device ...

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Functional Description.............................................................................................................. 119 5.1. Host Interface .............................................................................................................. 119 5.1.1. Frame Buffer Memory Support ....................................................................... 125 5.2. AGP Interface .............................................................................................................. 125 5.2.1. AGP Target Operations .................................................................................. 125 5.2.2. AGP Transaction Ordering ............................................................................. 127 5.2.3. AGP Electricals ............................................................................................... 127 5.2.4. The ...

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R Figures  Figure 1. Intel 840 Chipset System Block Diagram ................................................................14 Figure 2. PAM Registers...........................................................................................................55 Figure 3. System Address Map ..............................................................................................107 Figure 4. Detailed DOS Compatible Area Address Map.........................................................110 Figure 5. Detailed Extended Memory Range Address Map ...................................................110 Figure ...

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Tables Table 1. Maximum Memory Vs DRAM Densities ..................................................................... 17 Table 2. MCH Configuration Space (Device 0) ........................................................................ 41 Table 3. Attribute Bit Assignment............................................................................................. 54 Table 4. PAM Registers and Associated Memory Segments .................................................. 55 Table 5. MCH Configuration Space ...

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R Revision History Rev. • Initial Release -001 • Minor edits throughout for clarity. -002 • Removed references to MRH-S and SDRAM • Removed references to using two MRH-Rs per channel. Datasheet Draft/Changes 82840 MCH Date October 1999 September 2000 ...

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R ® Intel 82840 MCH Product Features ! Processor/Host Bus Support  Supports up to two Pentium  III processors at 100 MHz or or Pentium 133 MHz system bus frequency  Supports full symmetric multiprocessor (SMP) protocol  Supports ...

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Simplified Block Diagram CHA_RQ[7:5] or CHA_ROW[2:0] CHA_RQ[4:0] or CHA_COL[4:0] CHA_CTM, CHA_CTM# CHA_CFM, CHA_CFM# CHB_RQ[7:5] or CHB_ROW[2:0] CHB_RQ[4:0] or CHB_COL[4:0] CHB_CTM, CHB_CTM# CHB_CFM, CHB_CFM# 12 HA[35:3]# HD[63:0]# ADS# BNR# BPRI# AP[1:0]# BERR# BREQ0# DBSY# DEP[7:0]# DEFER# System Bus DRDY# Interface HIT# ...

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R 1. Overview ® The Intel 840 chipset is a high-bandwidth chipset designed for workstation and server platforms based   on Intel Pentium main components and additional optional components that provide expansion capability. The 82840 Memory Controller Hub (MCH) ...

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Figure 1. Intel 840 Chipset System Block Diagram Six 33 MHz PCI Slots Or Two 66 MHz PCI Slots 4 IDE Drives 2 USB Ports GPIO AC'97 Codec(s) (optional) Super I/O Shaded blocks are ® Intel ...

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R 82806AA PCI 64 Hub (P64H) The PCI-64 Hub(P64H peripheral chip that performs PCI bridging functions between the hub interface and the PCI Bus and is used as an integral part of the Intel primary hub interface to ...

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MCH Overview The 82840 Memory Hub (MCH) component provides the processor interface, DRAM interface, and AGP interface in a 82840 workstation or server platform. It supports dual channels of Direct Rambus DRAM operating in lock-step. It also supports ...

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R DRAM Interface The MCH directly supports dual channels of Direct Rambus* memory operating in lock-step using Rambus* Signaling Level (RSL) technology. Only 300 MHz and 400 MHz Direct Rambus* devices are supported in any of 64, 128 or 256Mb ...

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The AGP interface supports 4x AGP signaling and 4x Fast Writes. AGP semantic (PIPE# or SBA[7:0]) cycles to DRAM are not snooped on the host bus. AGP FRAME# cycles to DRAM are snooped on the host bus. The MCH supports ...

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R Term Single Channel-pair Mode Multiple Channel-pair Mode Single Device-pair Multiple Device-pair Datasheet Description In this mode, the 82840 MCH is configured to directly support RDRAM devices on its dual Rambus* channel. There is no MRH-R used on the memory ...

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R 2. Signal Description This section provides a detailed description of MCH signals. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of a signal name indicates that the active, or ...

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Host Interface Signals Name Type ADS# GTL+ AP[1:0]# GTL+ BERR# GTL+ BNR# GTL+ BREQ0# GTL+ BPRI# GTL+ CPURST# GTL+ DBSY# GTL+ DEFER# GTL+ DEP[7:0]# GTL+ DRDY# GTL+ HA[35:3]# GTL+ HD[63:0]# GTL+ HIT# GTL+ HITM# GTL+ 22 I/O Address Strobe: ...

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R Name Type HLOCK# GTL+ HREQ[4:0]# I/O GTL+ HTRDY# GTL+ IERR# CMOS RP# I/O GTL+ RS[2:0]# GTL+ RSP# GTL+ The following is the list of processor bus interface signals that are NOT supported by MCH. Signal AERR# BINIT# Datasheet I ...

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Direct Rambus* Interface A Signal CHA_DQA[8:0] CHA_DQB[8:0] CHA_RQ[7:5]/ CHA_ROW[2:0] CHA_RQ[4:0]/ CHA_COL[4:0] CHA_CTM CHA_CTM# CHA_CFM CHA_CFM# CHA_EXP[1:0] CHA_CMD CHA_SCK CHA_SIO 24 Type I/O Rambus Data Byte A (CHA): Bi-directional 9-bit data bus A on the Rambus* RSL interface A. Data ...

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R 2.3. Direct Rambus* Interface B Signal Name CHB_DQA[8:0] CHB_DQB[8:0] CHB_RQ[7:50]/ CHB_ROW[2:0] CHB_RQ[4:0]/ CHB_COL[4:0] CHB_CTM CHB_CTM# CHB_CFM CHB_CFM# CHB_EXP[1:0] CHB_CMD CHB_SCK CHB_SIO Datasheet Type I/O Rambus Data Byte A (CHB): Bi-directional 9-bit data bus A on the Rambus* RSL interface ...

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Hub Interface A Signals Name HLA_STB HLA_STB# HLA[11:0] HLAZCOMP 2.5. Hub interface B Signals Name HLB_STB[1:0] HLB_STB[1:0]# HLB[19:0] HLBRCOMP 2.6. AGP Interface Signals For more details on the operation of these signals, refer to the AGP Interface Specification, Revision ...

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R Name Type PIPE# I AGP SBA[7:0] I AGP 2.6.2. AGP Flow Control Signals Name Type RBF# I AGP WBF# I AGP Datasheet Description Pipeline: PIPE# Operation: This signal is asserted by the AGP master to indicate a full-width adress ...

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AGP Status Signals Name Type ST[2:0] O AGP 2.6.4. AGP Clocking Signals—Strobes Name Type AD_STB0 s/t/s AGP AD_STB0# s/t/s AGP AD_STB1 s/t/s AGP AD_STB1# s/t/s AGP 28 Status Bus: PIPE# and SBA Operation: These signals provide information from the ...

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R Name Type SB_STB AGP SB_STB# AGP 2.6.5. AGP FRAME# Signals For transactions on the AGP interface carried using AGP FRAME# protocol, these signals operate similar to their semantics in the PCI 2.1 specification. The exact role of all AGP ...

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Name Type G_TRDY# AGP G_STOP# AGP G_DEVSEL# AGP G_REQ# AGP G_GNT# AGP G_AD[31:0] AGP 30 I/O Target Ready: s/t/s PIPE# and SBA Operation: Not used while enqueueing requests via AGP SBA and PIPE#, but used during the data phase of ...

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R Name Type G_C/BE[3:0]# AGP G_PAR AGP G_SERR# AGP NOTES: 1. PCIRST# from the ICH is connected to RSTIN# and is used to reset AGP interface logic within the MCH. The AGP agent will also use PCIRST# provided by the ...

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Name RSTIN# TEST# OVERT# 2.8. Voltage References, PLL Power Signal Name GTLREF[A:B] AGPRCOMP CHA_REF[1:0] CHB_REF[1:0] AGPREF HLAREF HLBREF VCC1_8 VDDQ VTT VSS 32 Type I Reset In: When asserted, RSTIN# asynchronously resets the MCH logic. This CMOS signal is connected ...

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R 2.9. Strap Signals This section provides the strap options invoked by various MCH signal pins. Name HLA10 Host Bus Frequency: This signal is latched on the rising edge of RSTIN#. It indicates what the host FSB frequency is to ...

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This page is left intentionally blank. Datasheet ...

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R 3. Register Description This chapter describes the MCH PCI configuration registers. A detailed bit description is provided. The MCH contains two sets of software accessible registers, accessed via the Host I/O address space: • Control registers I/O mapped into ...

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Symbol Description Reserved In addition to reserved bits within a register, the MCH contains address locations in the Registers configuration space of the Host-hub interface A Bridge/DRAM Controller, Host-AGP Bridge and Host-Hub interface B Bridge entities that are marked “Reserved”. ...

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R PCI Bus Configuration Mechanism The PCI Bus defines a slot based "configuration space" that allows each device to contain functions, with each function containing up to 256 8-bit configuration registers. The PCI specification defines two bus ...

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Logical PCI Bus #0 Configuration Mechanism The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the CONF_ADDR register. If the Bus Number field of CONF_ADDR is 0 the configuration cycle is targeting a PCI Bus ...

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R 3.3. I/O Mapped Registers The MCH contains a set of registers that reside in the host I/O address space − the Configuration Address (CONF_ADDR) Register and the Configuration Data (CONF_DATA) Register. The Configuration Address Register enables/disables the configuration space ...

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Bit 15:11 Device Number: This field selects one agent on the PCI bus selected by the Bus Number. When the Bus Number field is “00”, the MCH decodes the Device Number field. The MCH is always Device Number 0 for ...

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R 3.4. Host-Hub interface A Bridge/DRAM Controller Device Registers (Device 0) An “s” in the Default Value field means that the power-up default value for that bit is determined by a strap. Table 2. MCH Configuration Space (Device 0) Address ...

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Address Offset 74–75h 76–77h 78–79h 7A–7Bh 7C–7Dh 7E–7Fh 80–87h 88h 89–8Fh 90–93h 94–97h 94–96h 98–9Ch 9Dh 9Eh ESMRAMC 9Fh A0–A3h A4–A7h AGPSTAT A8–ABh AGPCMD AC–AFh B0–B3h AGPCTRL B4h B5–B7h B8–BBh ATTBASE BCh BDh BEh BFh DRAMRC C0–C3h C4–C5h C6–C7h C8–C9h ...

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R Address Offset D0–DDh DE–DFh E0–E1h HERRCTL_STS Host Error Control/Status E2–E3h DERRCTL_STS DRAM ERROR Control/Status E4–E7h E8–EBh AGPBCTRL EC–F5h F6 AGPAPPEND F7 GTLNCLAMP F8–FFh Datasheet Symbol Register Name — Reserved SKPD Scratchpad Data EAP Error Address Pointer AGP Buffer Strength ...

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VID—Vendor Identification Register (Device 0) Address Offset: Default Value: Attribute: Size: The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no ...

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R 3.4.3. PCICMD—PCI Command Register (Device 0) Address Offset: Default: Access: Size Since MCH Device 0 does not physically reside on PCI0 many of the bits are not implemented. Writes to Not Implemented bits have no affect. Bit 15:10 Reserved. ...

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PCISTS—PCI Status Register (Device 0) Address Offset: Default Value: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0s on the hub interface. Bits 15:12 are read/write clear. All other bits ...

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R 3.4.5. RID—Revision Identification Register (Device 0) Address Offset: Default Value: Access: Size: This register contains the revision number of the MCH Device 0. These bits are read only and writes to this register have no effect. Bit 7:0 Revision ...

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MLT—Master Latency Timer Register (Device 0) Address Offset: Default Value: Access: Size: The hub interface does not use a Master Latency Timer. Therefore, this register is not implemented. Bit 7:0 These bits are hardwired to 0. Writes have no ...

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R Bit 31:28 Upper Programmable Base Address bits—R/W: These bits are used to locate the range size selected via bits 27:4 of this register. Default = 0000 27:22 Lower “Hardwired”/Programmable Base Address bits: These bits behave as a “hardwired” or ...

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SVID—Subsystem Vendor ID (Device 0) Offset: Default: Access: Size: This value is used to identify the vendor of the subsystem. Bit 15:0 Subsystem Vendor ID—R/WO: The default value is 00h. This field should be programmed during boot- up. After ...

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R 3.4.14. GAR[15:0]—RDRAM Group Architecture Register (Device 0) Address Offset: Default Value: Access: Size: This 8-bit register defines the page size, the #of banks, and DRAM technology of each device group in the RDRAM channel. There are 16 GAR registers ...

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MCHCFG—MCH Configuration Register (Device 0) Offset: Default: Access: Size: Bit 15:14 Reserved 13: Host Frequency—RO: These bits are used to determine the host frequency. These bits are set by an external strapping option at reset and are Read Only. ...

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R Bit 5 MDA Present (MDAP)—R/W: This bit works with the VGA Enable bit in the BCTRL register of device 1and 2 to control the routing of host initiated transactions targeting MDA compatible I/O and memory address ranges. This bit ...

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PAM0–PAM6—Programmable Attribute Map Registers (Device 0) Address Offset: Default Value: Attribute: Size: The MCH allows programmable memory attributes on 13 Legacy memory segments of various sizes in the 640 address range. Seven Programmable Attribute Map ...

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example, consider a BIOS that is implemented on the expansion bus. During the initialization process, the BIOS can be shadowed in main memory to increase the system performance. When BIOS is shadowed in main memory, it should ...

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DOS Application Area (00000h–9FFFh) The DOS area is 640 KB and it is divided into two parts. The 512 KB area 7FFFFh is always mapped to the main memory controlled by the MCH, while the 128 KB ...

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R 3.4.18. GBA0–GBA15—RDRAM Group Boundary Address Register (Device 0) Address Offset: Default: Access: Size Note: This register is locked and becomes Read Only when the D_CLK bit in the SMRAM register is set. This is done to improve SMM security. ...

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RDPS—RDRAM Pool Sizing Register (Device 0) Address Offset: Default Value: Access: Size: Bit 7 Pool Lock (LOCK Contents of the RDPS register becomes READ Only Contents of the RDPS register becomes READ/WRITE. 6 Reserved 5 ...

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R 3.4.20. DRD—RDRAM Device Register Data Register (Device 0) Address Offset: Default Value: Access: Size: Bit 31:0 Register Data (RD): Bits 31:0 contain the 32 bits of data to be written to a RDRAM register or the data read from ...

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Bit 21:20 Channel ID (CID): This field specifies the channel address for which the initialization or the channel reset operation is initialed. 19 Broadcast Address (BA Initialization operation (IOP) is broadcast to all devices. When this bit is ...

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R 3.4.22. MCH Expansion RAC A/B Configuration Registers Address Offset Default: Access: Size: To enable the E-clamp of MCH RAC A, first write a 32-bit value into the DRD register (offset 90–93h). Then, issue an Initialization Opcode (IOP=11001b) through the ...

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Bit 3 Global SMRAM Enable (G_SMRAME): If set then Compatible SMRAM functions is enabled, providing 128 KB of DRAM accessible at the A0000h address while in SMM (ADS# with SMM decode). To enable Extended SMRAM function this ...

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R 3.4.25. ACAPID—AGP Capability Identifier Register (Device 0) Address Offset: Default Value: Access: Size: This register provides standard identifier for AGP capability. Bit 31:24 Reserved 23:20 Major AGP Revision Number: These bits provide a major revision number of AGP specification ...

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AGPSTAT—AGP Status Register (Device 0) Address Offset: Default Value: Access: Size: This register reports AGP device capability/status. Bit 31:24 Maximum Requests (RQ): Hardwired to 1Fh. This field contains the maximum number of AGP command requests the MCH is configured ...

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R 3.4.27. AGPCMD—AGP Command Register (Device 0) Address Offset: Default Value: Access: Size: This register provides control of the AGP operational parameters. Bit 31:10 Reserved. 9 Side Band Addressing Enable (SBA_EN Enable. Side band addressing mechanism is enabled. ...

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AGPCTRL—AGP Control Register (Device 0) Address Offset: Default Value: Access: Size: This register provides for additional control of the AGP interface. Bit 15:8 Reserved 7 GTLB Enable (and GTLB Flush Control)—R/ Enable. Normal operations of the Graphics ...

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R ATTBASE    Aperture Translation Table Base Register 3.4.30. (Device 0) Address Offset: Default Value: Access: Size: This register provides the starting address of the Graphics Aperture Translation Table Base located in the main DRAM. This value is ...

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LPTT—Low Priority Transaction Timer Register (Device 0) Address Offset: Default Value: Access: Size: LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the minimum tenure on the AGP for low priority ...

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R 3.4.33. RDTR—RDRAM Timing Register (Device 0) Address Offset: Default Value: Access: Size: RDTR defines the timing parameters for all devices in the Direct RDRAM channel. BIOS programs this register with the “least common denominator” values after reading configuration registers ...

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RDCR—RDRAM Refresh Control Register (Device 0) Address Offset: Default Value: Access: Size: This register is loaded by configuration software with the refresh timings when the Direct RDRAM Devices or the MRH-R Present bit is set in the RICM register ...

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R 3.4.35. TOM—Top of Low Memory Register (Device 0) Address Offset: Default Value: Access: Size: A memory hole is present under normal operating conditions from TOM up to the 4 GB address where TOM is the Top Of Lower Memory ...

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Bit 12 Host Uncorrectable Error (FSBBIERR MCH detected the assertion of either the BERR# signal or the IERR# signal on the processor bus. An SERR or SCI hub interface A message will be generated to ICH, if the ...

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R Bit 3 Invalid AGP Access Flag (IAAF AGP access was attempted outside of the graphics aperture and either to the 640 KB – range or above the top of memory. An SERR, SCI or ...

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Bit 15 SERR on Host Bus Error Enable (HBSERR Enable. Generation of the hub interface A SERR message is enabled for the parity errors on the address or request signals of the front side bus Disable ...

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R Bit 4 SERR on AGP Access Outside of Graphics Aperture (OOGF_SERR Enable. The generation of the hub interface A SERR message is enabled when an AGP access occurs to an address outside of the graphics aperture. 0 ...

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Bit 10 SMI on External Thermal Sensor Trip (THERM_SMI When this bit is set, the generation of the hub interface A SMI message is enabled when the MCH has detected a rising edge on the OVERT# or the ...

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R 3.4.39. SCICMD—SCI Command Register (Device 0) Address Offset: Default Value: Access: Size: This register enables various errors to generate a SCI message via the hub interface A. Note: An error can generate one and only one error message via ...

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Bit 4 SCI on AGP Access Outside of Graphics Aperture (OOGF_SCI Enable. The generation of the hub interface A SCI message is enabled when an AGP access occurs to an address outside of the graphics aperture ...

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R 3.4.41. HERRCTL_STS—Host Error Control/Status Register (Device 0) Address Offset: Default Value: Access: Size: This register enables and reflects the status of various errors checking functions which the MCH supports on the front side bus. Bit 15 Detected BERR (DBERR)—R/WC: ...

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DERRCTL_STS—DRAM Error Control/Status Register (Device 0) Address Offset: Default Value: Access: Size: This register enables and reflects the status of various errors checking functions which the MCH supports on the DRAM interface. Bit 15:12 Reserved 11 DRAM Correctable ECC ...

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R 3.4.44. AGPBCTRL—AGP Buffer Strength Control Register Address Offset: Default Value: Access: Size: This register controls the 3.3V AGP buffer strength. The proper setting is documented in the Intel BIOS Specification Update. Bit 31:24 AGP Buffer Strength Control 1: 23:16 ...

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AGP Bridge Registers (Device 1) Table 5 summarizes the MCH configuration space for Device 1. Table 5. MCH Configuration Space (Device 1) Address Offset 00–01h 02–03h 04–05h 06–07h 08 09 0Ah 0Bh 0Ch 0Dh 0Eh 0F–17h 18h 19h 1Ah ...

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R 3.5.1. VID1—Vendor Identification Register (Device 1) Address Offset: Default Value: Attribute: Size: The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have ...

Page 84

PCICMD1—PCI-PCI Command Register (Device 1) Address Offset: Default: Access: Size Bit 15:10 Reserved 9 Fast Back-to-Back—RO: (Not Applicable). Hardwired SERR Message Enable (SERRE1)—R/W. This bit is a global enable bit for Device 1 SERR messaging. The ...

Page 85

R 3.5.4. PCISTS1—PCI-PCI Status Register (Device 1) Address Offset: Default Value: Access: Size: PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with the primary side of the “virtual” PCI-PCI bridge in the MCH. Since ...

Page 86

SUBC1—Sub-Class Code Register (Device 1) Address Offset: Default Value: Access: Size: This register contains the Sub-Class Code for the MCH device 1. Bit 7:0 Sub-Class Code (SUBC1): This is an 8-bit value that indicates the category of Bridge for ...

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R 3.5.10. PBUSN1—Primary Bus Number Register (Device 1) Offset: Default: Access: Size: This register identifies that “virtual” PCI-PCI bridge is connected to bus #0. Bit 7:0 Primary Bus Number: Hardwired to 00h. 3.5.11. SBUSN1—Secondary Bus Number Register (Device 1) Offset: ...

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SMLT1—Secondary Master Latency Timer Register (Device 1) Address Offset: Default Value: Access: Size: This register controls the bus tenure of the MCH on AGP. SMLT1 controls the amount of time the MCH AGP/PCI bus master, can burst ...

Page 89

R 3.5.15. IOLIMIT1—I/O Limit Address Register (Device 1) Address Offset: Default Value: Access: Size: This register controls the host to AGP I/O access routing based on the following formula: IO_BASE ≤ address ≤ IO_LIMIT Only the upper 4 bits are ...

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Bit 11 Signaled Target Abort Status (STAS1)—RO: MCH does not generate target abort on AGP. Hardwired 10:9 DEVSEL# Timing (DEVT1)—RO: This 2-bit field indicates the timing of the DEVSEL# signal when the MCH responds as a target ...

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R 3.5.18. MLIMIT1—Memory Limit Address Register (Device 1) Address Offset: Default Value: Access: Size: This register controls the host to AGP non-prefetchable memory access routing based on the following formula: MEMORY_BASE1 ≤ address ≤ MEMORY_LIMIT1 The upper 12 bits of ...

Page 92

PMLIMIT1—Prefetchable Memory Limit Address Register (Device 1) Address Offset: Default Value: Access: Size: This register controls the host to AGP prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE1 ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT1 The upper 12 bits of ...

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R Bit 7 Fast Back to Back Enable—RO: Since there is only one target allowed on AGP this bit is meaningless.Hardwired to 0. The MCH will not generate FB2B cycles in 1x mode, but will generate FB2B cycles in 2x ...

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ERRCMD1—Error Command Register (Device 1) Address Offset: Default Value: Access: Size: Bit 7:1 Reserved 0 SERR on Receiving Target Abort (SERTA MCH generates an SERR message over hub interface A upon receiving a target abort on AGP. ...

Page 95

R 3.6. Hub interface B Bridge Registers (Device 2) Table 6 summarizes the MCH configuration space for device 2. Table 6. MCH Configuration Space (Device 2) Address Symbol Offset 00–01h 02–03h 04–05h PCICMD2 06–07h PCISTS2 08 09 0Ah SUBC2 0Bh ...

Page 96

VID2—Vendor Identification Register (Device 2) Address Offset: Default Value: Attribute: Size: The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no ...

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R 3.6.3. PCICMD2—PCI-PCI Command Register (Device 2) Address Offset: Default: Access: Size Bit 15:10 Reserved. 9 Fast Back-to-Back—RO: (Not applicable). Hardwired SERR Message Enable (SERRE2)—R/W: This bit is a global enable bit for Device 2 SERR messaging. ...

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PCISTS2—PCI-PCI Status Register (Device 2) Address Offset: Default Value: Access: Size: PCISTS2 reports the occurrence of error conditions associated with the primary side of the “virtual” PCI- PCI bridge in the MCH. Since this device does not physically reside ...

Page 99

R 3.6.6. SUBC2—Sub-Class Code Register (Device 2) Address Offset: Default Value: Access: Size: This register contains the Sub-Class Code for the MCH Device 2. Bit 7:0 Sub-Class Code (SUBC2): This is an 8-bit value that indicates the category of Bridge ...

Page 100

PBUSN2—Primary Bus Number Register (Device 2) Offset: Default: Access: Size: This register identifies that “virtual” PCI-PCI bridge is connected to bus #0. Bit 7:0 Primary Bus Number: Hardwired to 0. 3.6.11. SBUSN2—Secondary Bus Number Register (Device 2) Offset: Default: ...

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R 3.6.14. IOBASE2—I/O Base Address Register (Device 2) Address Offset: Default Value: Access: Size: This register controls the host to hub interface B I/O access routing based on the following formula: IO_BASE2 ≤ address ≤ IO_LIMIT2 Only the upper 4 ...

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SSTS2—Secondary PCI-PCI Status Register (Device 2) Address Offset: Default Value: Access: Size: SSTS2 reports the occurrence of error conditions associated with secondary side (i.e., hub interface B side ) of the “virtual” PCI-PCI bridge embedded within MCH. Bit 15 ...

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R 3.6.17. MBASE2—Memory Base Address Register (Device 2) Address Offset: Default Value: Access: Size: This register controls the host to hub interface B non-prefetchable memory access routing based on the following formula: MEMORY_BASE2 ≤ address ≤ MEMORY_LIMIT2 The upper 12 ...

Page 104

PMBASE2—Prefetchable Memory Base Address Register (Device 2) Address Offset: Default Value: Access: Size: This register controls the host to hub interface B prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE2 ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT2 The upper 12 ...

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R 3.6.21. BCTRL2—PCI-PCI Bridge Control Register (Device 2) Address Offset: Default: Access: Size This register provides extensions to the PCICMD2 register that are specific to PCI-PCI bridges. The BCTRL2 provides additional control for the secondary interface (i.e., hub interface B) ...

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Bit 0 Parity Error Response Enable—R/W: This bit controls MCH’s response to data phase parity errors on hub interface Address and data parity errors on hub interface B are reported via SERR# mechanism, if enabled by SERRE2 ...

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R 4. System Address Map A system based on the 82840 chipset supports addressable memory space and 64 KB+3 of addressable I/O space. The I/O and memory spaces are divided by system configuration software into regions. The ...

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DOS Compatibility Area This area is divided into the following address regions: • 0 640 KB DOS Area – • 640 768 KB Video Buffer Area – • 768 896 sections (total of 8 sections) ...

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R Accesses to this range can be directed to AGP by setting the VGAEN bit in the BCTRL1 (PCI-PCI Bridge Control) register in Device 1. In addition, accesses to this range can be directed to the hub interface B by ...

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Figure 4. Detailed DOS Compatible Area Address Map Standard PCI/ISA Video Memory (SMM Memory) 4.1.2. Extended Memory Area This memory area contains the main DRAM address range divided into regions as shown in Figure 5. Figure 5. Detailed ...

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R ISA Hole Memory Space (0_00F0_0000 to 0_00FF_FFFF) This memory hole is opened through the FDHC register (device 0, offset 58h). When it is enabled, accesses to this region are forward to hub interface A. Extended SMRAM Address Range The ...

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AGP Memory and Prefetchable Memory Plug-and-play software configures the AGP memory window to provide enough memory space. Accesses whose addresses fall within this window are decoded and forwarded to AGP for completion. Note that these registers (MBASE1, MLIMIT1, MBASE1,PMLIMIT1) must ...

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R 4.1.4. AGP DRAM Graphics Aperture Memory-mapped, graphics data structures can reside in a Graphics Aperture to main DRAM memory. This aperture is an address range defined by the APBASE and APSIZE configuration registers of the MCH device 0. The ...

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SMM Space Definition SMM space is defined by its addressed SMM space and its DRAM SMM space. The addressed SMM space is defined as the range of bus addresses used by the processor to access SMM space. DRAM SMM ...

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R 4.1.6. Memory Shadowing Any block of memory that can be designated as read-only or write-only can be “shadowed” into MCH DRAM memory. Typically, this is done to allow ROM code to execute more rapidly out of main DRAM. ROM ...

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MCH Decode Rules and Cross-Bridge Address Mapping The address map described above applies globally to accesses arriving on any of the four interfaces (i.e., Host bus, the hub interface A, hub interface B or AGP). 4.1.8.1. The Hub interface ...

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R 4.1.8.3. AGP Interface Decode Rules Cycles Initiated Using AGP FRAME# Protocol The MCH does not support any AGP FRAME# access targeting hub interface A. The MCH claims AGP- initiated memory read/write transactions decoded to the main DRAM range or ...

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Legacy VGA Ranges The legacy VGA memory range A0000h–BFFFFh is mapped either to hub interface A, hub interface B, or AGP. This behavior is configured by the programming of the VGA Enable bits in the BCTRL configuration registers in ...

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R 5. Functional Description 5.1. Host Interface The 82840 MCH is optimized to support the Pentium bus clock frequencies of 133 MHz or 100 MHz. The MCH supports up to two processors at FSB frequencies of 100/133 MHz using AGTL+ ...

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Transaction I/O Read I/O Write Reserved Memory Read and Invalidate Reserved Memory Code Read Memory Data Read Memory Write (no retry) Memory Write (can be retried) NOTES: 1. For Memory cycles, REQa[4:3]# = ASZ#. 2. REQb[4:3]# = DSZ#. For the ...

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R Table 9. Types of Responses Supported by the MCH RS2# RS1 Host Addresses Above 4 GB Host memory writes to address space above ...

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Partial Writes Partial Write transactions include: I/O and memory write operations of eight bytes or less (maximum of four bytes for I/O) within an aligned 8 byte span. The byte enable signals, BE[7:0]#, select which bytes in the span to ...

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R Interrupt Acknowledge Cycles A processor agent issues an Interrupt Acknowledge cycle in response to an interrupt from an 8259- compatible interrupt controller. The Interrupt Acknowledge cycle is similar to a partial read transaction, except that the address bus does ...

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Table 10 specifies the cycle type and definition as well as the action taken by the MCH when a special cycle is identified. Note that none of the host bus special cycles are propagated to either the AGP interface or ...

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R 5.1.1. Frame Buffer Memory Support To allow for high speed write capability for graphics, the Pentium II processor introduced WC (Write- combined memory type). USWC is uncacheable, speculative, write-combining. The USWC memory type provides a write-combining buffering mechanism for ...

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Table 11. AGP Commands Supported by the MCH When Acting as an AGP Target AGP Command Read Hi-Priority Read Reserved Reserved Write Hi-Priority Write Reserved Reserved Long Read Hi-Priority Long Read Flush Reserved Fence Reserved Reserved Reserved NOTES: N/A refers ...

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R 5.2.2. AGP Transaction Ordering The MCH observes transaction ordering rules as defined by the AGP Interface Specification, Revision 2.0. 5.2.3. AGP Electricals The 4x data transfers use 1.5V signaling levels as described in the AGP 2.0 Specification. The MCH ...

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Fast Writes The MCH supports 2x and 4x Fast Writes from the MCH to the graphics controller on AGP. Fast Write operation is compliant with Fast Writes as currently described in AGP 2.0. The MCH indicates that it supports ...

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R 5.2.8.1. MCH Initiator and Target Operations Table 13 summarizes MCH target operation for AGP FRAME# initiators. These cycles target only to main memory. Table 13. PCI Commands Supported by the MCH When Acting as A FRAME# Target PCI Command ...

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MCH as Target of AGP FRAME# Cycle (Supported Transactions) • Memory Read, Memory Read Line, and Memory Read Multiple. These commands are supported identically by the MCH. The MCH does not support reads of the hub interface bus from AGP. ...

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R 5.2.8.2. MCH Retry/Disconnect Conditions The MCH generates retry/disconnect according to the AGP Specification rules when being accessed as a target from the AGP FRAME# device. 5.2.8.3. Delayed Transaction When a AGP FRAME#-to-DRAM read cycle is retried by the MCH, ...

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RDRAM Interface The 82840 MCH directly supports Dual channels(interfaces) of Rambus* Direct memory operating in lock-step using RSL technology. The MCH support two different operation modes: • Single Channel-pair Mode. The MCH is configured to directly support RDRAM devices ...

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R Figure 7 shows the interconnections between MCH and its dual Direct RDRAM channels configured at multiple channel-pair mode. Figure 7. Multiple Channel-pair Mode 82840 MCH The maximum system memory supported by MCH depends on the Direct RDRAM device technology ...

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Table 15. Direct RDRAM Device Configurations CF# Device Tech 1 64Mbit 2 128Mbit 3 256Mbit 4 A brief overview of the registers that configure the Direct RDRAM interface is provided below: • Group Boundary Address Register (GBA). GBA registers define ...

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R 5.3.1.1. Rules for Populating RDRAM Devices MCH Rambus* channels can be implemented such that it is fully or partially loaded with RDRAM devices; however, they must be populated in either single-device pair or multiple-device pair. • Single Device-pair. The ...

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Single Channel Mode Device-Pair IDs for Group Members NOTES: 1. All RSL signals must be terminated at the far end from the MCH. 2. The default device ID for an RDRAM device after power up is 1Fh. 5.3.1.2. RDRAM CMOS ...

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R Figure 9. MRH-R Sideband CMOS Signal Configuration on Rambus* Channel A Table 17. Sideband CMOS Signal Description Signal SCK Serial Clock: This signal serves as the clock for SIO and CMD signals. SCK is a clock source used for ...

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SIO Pin Initialization SIO0 and SIO1 pins on Direct RDRAM devices are bi-directional; their direction needs to be initialized. The “SIO Reset” initializes SIO0 and SIO1 pins on all Direct RDRAMs as daisy chain configuration and is performed with SCK ...

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R 5.3.2.1. Row Packet (ROWA/ROWR) The row packet is defined using three RSL signals RQ[7:5]/ROW[2:0]. The row packet is generally the first control packet issued to a device. Major characteristics of a row packet are: • The only way to ...

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Legend Controller drives Controller drives 0 1 ...

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R 5.3.2.2. Column Packet (COLC/COLX) The column packet is defined using five of the RSL signals RQ[4:0]/COL[4:0]. Major characteristics of column are: • the only way to dispatch column operation for read or write • requires the target Direct RDRAM ...

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Table 23. COLX Packet ( Cycle 0 COL4 COL3 COL2 COL1 COL0 DX[4:0] Device ID for Extra operation BX[4:0] Bank Address for Extra operation MA[7:0] Byte Mask (low order) MB[7:0] Byte Mask (high order) XOP[4:0] Opcode for Extra ...

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R 5.3.3. Direct RDRAM Register Programming Software can read and write Direct RDRAM device registers by programming the RDRAM Initialization Control Management (RICM) Register in the MCH. The register data returned by the device will be available in the Device ...

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Standby mode, it can accept only row packets. Once a device receives any row packet, it transitions into active state and then can accept a column packet. Nap State A Direct RDRAM enters into Nap state when ...

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R 5.3.6. Data Integrity The MCH supports an Error Correcting Code (or Error Checking and Correcting) on the main memory interface. The MCH can optionally be configured to generate the ECC code for writes to memory and check the code ...

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MCH via a special bit asserted during their current calibration operations. When the MCH detects an overtemperature condition in any of the memory devices, the RDRAM pools are reinitialized with “safer” values. Finally, the MCH may ...

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R 6. Ballout and Package Information 6.1. MCH Ball List The following two figures show a fooprint of the MCH ballout with the signals indicated for each ball location. Table 28 provides an alphabetical ball list. Datasheet 82840 MCH 147 ...

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Figure 11. MCH Ballout (Top View, Left Side AGPRCOMP AGPREF GAD8 A GAD3 GAD7 GC/BE0# B GAD2 GAD6 VDDQ C GAD1 VSS ADSTB0 D GAD0 GAD5 ADSTB0# E VSS GAD4 VSS F CHA_DQA8 VSS CHA_DQA7 G CHA_DQA6 ...

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R Figure 12. MCH Ballout (Top View, Right Side GREQ# HLBSTB0# HLBSTB0 HLB17 GGNT# VSS HLBPD4 VSS ST0 HLBPD1 HLBPD5 HLB19 ST1 HLBPD2 HLBPD6 HLB16 ST2 VSS HLBPD7 VSS HLBPD0 HLBPD3 HLB18 HLBPD8 Vcc1_8 VSS VCC1_8 ...

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Table 28. MCH Alphabetical Ballout List Signal Ball # ADS# AE26 ADSTB0 D3 ADSTB0# E3 ADSTB1 C9 ADSTB1# D9 AGPRCOMP A1 AGPREF A2 AP0# AF25 AP1# AF26 BERR# P21 BNR# AA21 BPRI# AA22 BREQ0# AF24 CHA_CFM L1 CHA_CFM# L2 CHA_CTM ...

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R Signal Ball # GSERR# F6 GSTOP# D6 GTLREFA A21 GTLREFB AF22 GTRDY# C6 HA3# AA23 HA4# Y23 HA5# W23 HA6# AA24 HA7# Y26 HA8# Y24 HA9# Y21 HA10# W22 HA11# W25 HA12# W26 HA13# V23 HA14# W21 HA15# V26 ...

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Signal Ball # HLBSTB0# A15 HLBSTB1 E18 HLBSTB1# D18 HLOCK# AB25 HREQ0# AA25 HREQ1# AB23 HREQ2# AB26 HREQ3# AC23 HREQ4# AB24 HTRDY# AA26 IERR# A20 NC W6 OVERT# AA6 PIPE# B13 RBF# A13 RCLKOUTA AB1 RCLKOUTB AF5 RP# AD26 RS0# ...

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R Signal Ball # VSS L25 VSS M3 VSS M4 VSS M5 VSS M12 VSS M13 VSS M14 VSS M15 VSS N2 VSS N4 VSS N5 VSS N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS P4 ...

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Package Information This specification outlines the mechanical dimensions for the 82840 MCH. The package is a 544 ball grid array (BGA). Figure 13. 82840 MCH BGA Package Dimensions (Top and Side Views) Pin A1 corner Pin A1 I.D. 45° ...

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R Figure 14. 82840 MCH BGA Package Dimensions (Bottom View Table 29. Package Dimensions Symbol 34.80 D1 29.75 E 34.80 E1 29. NOTES: 1. All dimensions ...

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RSL Nomalized Trace Length Data Expansion Channel A ∆ ∆ ∆ ∆ L Normalized to CHA_DQA8 PKG Signal CHA_CFM CHA_ CFM# CHA_CTM CHA_CTM# CHA_DQA0 CHA_ DQA1 CHA_ DQA2 CHA_ DQA3 CHA_ DQA4 CHA_ DQA5 CHA_ DQA6 CHA_ DQA7 ...

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R These lengths must be considered when matching trace lengths as described in the Intel Design Guide. Note that these lengths are normalized to 0 with the longest trace on the package. They do not represent the actual lengths from ...

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This page is intentionally left blank. Datasheet ...

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R 7. Testability In the MCH, the testability for Automated Test Equipment (ATE) board level testing has been changed from traditional NAND chain to the new XOR chain. An XOR-Tree is a chain of XOR gates, each with one Input ...

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Initialization Sequence Two pins are used to enter the XOR chain test mode as shown in the Figure 16. XOR Chain Test Mode Entering Rules: • TEST# should be driven “Low” for exactly 7 clocks after “RSTIN#” goes “High” ...

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R 7.2. XOR Chains Table 30. XOR Chain #0 Connections Name Ball Chain Element # GC/BE1# D5 GSERR# F6 GAD_15 E5 GC/BE0# B3 GAD_11 D4 GAD_14 F5 GAD_7 B2 GAD_10 E4 GAD_13 G5 GAD_6 C2 ADSTB0 D3 GAD_2 C1 GAD_5 ...

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Table 32. XOR Chain #2 Connections Name Ball Chain Element # HA3# AA23 HLOCK# AB25 HA6# AA24 HREQ2# AB26 HA4# Y23 HREQ0# AA25 HA8# Y24 HTRDY# AA26 HA5# W23 HA17# W24 HA11# W25 HA7# Y26 HA13# V23 HA21# V24 HA12# ...

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R Table 33. XOR Chain #3 Connections Name Ball Chain Element # HD41# F24 HD32# J23 HD24# J22 HD27# J21 HD38# H24 HD36# G24 HD42# E26 HD34# H23 HD46# D26 HD54# D25 HD31# H21 HD48# E24 HD50# D24 HD44# G23 ...

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Table 34. XOR Chain #4 Connections Name Ball Chain Element # GAD_28 D10 GAD_21 B8 GAD_31 F11 GAD_27 E10 ADSTB1# D9 GAD_17 A7 GAD_26 F10 GAD_22 D8 GAD_18 C7 GC/BE2# D7 GAD_19 E8 GAD_23 F9 GAD_16 E7 GAD_20 F8 GFRAME# ...

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R Table 36. XOR Chain #6 Connections Name Ball Chain Element # CHB_RQ1 AE16 CHB_RQ0 AD16 CHB_DQB0 AD17 CHB_DQB1 AF17 CHB_DQB2 AD18 CHB_DQB3 AF18 CHB_DQB4 AD19 CHB_DQB5 AF19 CHB_DQB6 AE18 CHB_DQB7 AF20 CHB_DQB8 AD20 SBA_7 E11 Datasheet Note 20 21 ...

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... Ibaraki-ken 305 Japan Phone: (81) 298 47 8522 South America Intel Semicondutores do Brazil Rua Florida 1703-2 and CJ22 CEP 04565-001 Sao Paulo-SP Brazil Phone: (55) 11 5505 2296 For More Information To learn more about Intel Corporation, visit our site on the World Wide Web at www.intel.com R ...

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