21152AB Intel Corporation, 21152AB Datasheet
21152AB
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PCI-to-PCI Bridge Preliminary Datasheet October 1998 Notice: This document contains information on products in the design phase of development. Do not final- ize a design with this information. Revised information will be published when the product is available. Verify ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners. 21152 PCI-to-PCI Bridge Preliminary Datasheet ...
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Contents 1 Introduction.................................................................................................................................... 1-1 1.1 Features............................................................................................................................ 1-1 1.2 Architecture ..................................................................................................................... 1-4 1.3 Data Path ......................................................................................................................... 1-6 1.3.1 Posted Write Queue .......................................................................................... 1-6 1.3.2 Delayed Transaction Queue .............................................................................. 1-7 1.3.3 Read Data Queue .............................................................................................. 1-7 2 Signal Pins ..................................................................................................................................... 2-1 2.1 ...
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Transaction Termination................................................................................................ 4-21 4.8.1 Master Termination Initiated by the 21152..................................................... 4-22 4.8.2 Master Abort Received by the 21152.............................................................. 4-22 4.8.3 Target Termination Received by the 21152 .................................................... 4-24 4.8.3.1 Delayed Write Target Termination Response .................................. 4-24 4.8.3.2 Posted Write ...
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Bus Parking ....................................................................................................... 9-3 10 Clocks .......................................................................................................................................... 10-1 10.1 Primary and Secondary Clock Inputs ............................................................................ 10-1 10.2 Secondary Clock Outputs .............................................................................................. 10-2 10.2.1 Disabling Unused Secondary Clock Outputs.................................................. 10-2 11 Reset............................................................................................................................................. 11-1 11.1 Primary Interface Reset ................................................................................................. 11-1 11.2 ...
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PPB Support Extensions Registers — Offset E2h ........................................ 13-24 13.1.35 Data Register — Offset E3h.......................................................................... 13-24 13.2 Device-Specific Configuration Registers .................................................................... 13-25 13.2.1 Chip Control Register — Offset 40h............................................................. 13-25 13.2.2 Diagnostic Control Register — Offset 41h ................................................... 13-26 ...
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PCI Signal Timing Measurement Conditions....................................................15-4 16-1 160-Pin PQFP Package ...................................................................................16-1 Tables 1-1 21152 Function Blocks .......................................................................................1-5 2-1 Signal Pin Functional Groups .............................................................................2-1 2-2 Signal Type Abbreviations..................................................................................2-1 2-3 Primary PCI Bus Interface Signals (Sheet .............................................2-2 2-4 Secondary ...
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Introduction The 21152 is a second-generation PCI-to-PCI bridge and is fully compliant with PCI Local Bus Specification, Revision 2.1. The 21152 is pin-to-pin compatible with the 21052, which is fully compliant with PCI Local Bus Specification, Revision 2.0.The 21152 provides ...
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Introduction — A 32-bit memory-mapped I/O address range — A 64-bit prefetchable memory address range — ISA-aware mode for legacy support in the first I/O address range — VGA addressing and VGA palette snooping support • Supports ...
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Option card designers can use the 21152 to implement multiple-device PCI option cards. Without a PCI-to-PCI bridge, PCI loading rules would limit option cards to one device. The PCI Local Bus Specification loading rules limit PCI option cards to a ...
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Introduction 1.2 Architecture The 21152 internal architecture consists of the following major functions: • PCI interface control logic for the primary and secondary PCI interfaces • Data path and data path control logic • Configuration register and configuration control logic ...
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Table 1-1 describes the major functional blocks of the 21152. Table 1-1. 21152 Function Blocks Function Block Primary and Secondary Control Primary-to-Secondary Data Path Secondary-to-Primary Data Path Configuration Registers Secondary Bus Arbiter Control 21152 PCI-to-PCI Bridge Preliminary Datasheet Description PCI ...
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Introduction 1.3 Data Path The data path consists of a primary-to-secondary data path for transactions and data flowing in the downstream direction and a secondary-to-primary data path for transactions and data flowing in the upstream direction. Both data paths have ...
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Delayed Transaction Queue For a delayed write request transaction, the delayed transaction queue contains the address, bus command, 1 Dword of write data, byte enable bits, and parity. When the delayed write transaction is completed on the target bus, ...
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Signal Pins This chapter provides detailed descriptions of the 21152 signal pins, grouped by function. Table 2-1 describes the signal pin functional groups, and the following sections describe the signals in each group. Table 2-1. Signal Pin Functional Groups Function ...
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Signal Pins 2.1 Primary PCI Bus Interface Signals Table 2-3 describes the primary PCI bus interface signals. Table 2-3. Primary PCI Bus Interface Signals (Sheet Signal Name Type p_ad<31:0> TS p_cbe_l<3:0> TS p_par TS p_frame_l STS p_irdy_l ...
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Table 2-3. Primary PCI Bus Interface Signals (Sheet Signal Name Type p_devsel_l STS p_stop_l STS p_lock_l I p_idsel I p_perr_l STS 21152 PCI-to-PCI Bridge Preliminary Datasheet Description Primary PCI interface DEVSEL#. Signal p_devsel_l is asserted by the ...
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Signal Pins Table 2-3. Primary PCI Bus Interface Signals (Sheet Signal Name Type p_serr_l OD p_req_l TS p_gnt_l I 2-4 Description Primary PCI interface SERR#. Signal p_serr_l can be driven low by any device on the primary ...
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Secondary PCI Bus Interface Signals Table 2-4 describes the secondary PCI bus interface signals. Table 2-4. Secondary PCI Bus Interface Signals (Sheet Signal Name Type s_ad<31:0> TS s_cbe_l<3:0> TS s_par TS s_frame_l STS s_irdy_l STS s_trdy_l ...
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Signal Pins Table 2-4. Secondary PCI Bus Interface Signals (Sheet Signal Name Type s_devsel_l STS s_stop_l STS s_lock_l STS s_perr_l STS s_serr_l I 2-6 Description Secondary PCI interface DEVSEL#. Signal s_devsel_l is asserted by the target, indicating ...
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Secondary Bus Arbitration Signals describes the secondary bus arbitration signals. Table 2-5 . Table 2-5. Secondary PCI Bus Arbitration Signals Signal Name Type s_req_l<3:0> I s_gnt_l<3:0> TS s_cfn_l I 2.4 Clock Signals Table 2-6 describes the clock signals. Table ...
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Signal Pins 2.5 Reset Signals describes the reset signals. Table 2-7 Table 2-7. Reset Signals Signal Name Type a bpcc I p_rst_l I s_rst_l O a. 21152–AB and later revisions only. 2.6 Miscellaneous Signals Table 2-8 describes the miscellaneous signals. ...
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Nand Tree Signals Table 2-9 describes the Nand tree signals. Table 2-9. Nand Tree Signals Signal Name Type goz_l I nand_out O 21152 PCI-to-PCI Bridge Preliminary Datasheet Description Diagnostic tristate control. This signal, when asserted, tristates all bidirectional and ...
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Pin Assignment This chapter describes the 21152 pins. It provides numeric and alphanumeric lists of the pins and includes a diagram showing 21152 pin assignment. Figure 3-1 shows the 21152 pins. lists pins by signal names in alphanumeric order. Figure ...
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Pin Assignment 3.1 Pin Location List (Numeric) Table 3-1 provides the signal type abbreviations used in numeric order, showing the location, signal name, and signal type of each pin. Table 3-1. Signal Type Abbreviations Signal Type ...
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Table 3-2. Pin Location List (Numeric) (Sheet PQFP Signal Name Location 47 s_gnt_l<3> 48 s_rst_l 49 s_cfn_l 50 vss 51 s_clk 52 s_vio 53 s_clk_o<0> 54 vss 55 s_clk_o<1> 56 vdd 57 s_clk_o<2> 58 vss 59 s_clk_o<3> ...
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Pin Assignment Table 3-2. Pin Location List (Numeric) (Sheet PQFP Signal Name Location 121 vss 122 p_cbe_l<0> 123 p_ad<7> 124 p_ad<6> 125 vdd 126 p_ad<5> 127 p_ad<4> 128 vss 129 p_ad<3> 130 p_ad<2> 131 vdd 132 p_ad<1> ...
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Pin Signal List (Alphanumeric) Table 3-3 provides the signal type abbreviations used in names in alphanumeric order, showing the signal name, location, and signal type of each pin. Table 3-3. Signal Type Abbreviations Signal Type ...
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Pin Assignment Table 3-4. Pin Signal List (Alphanumeric) (Sheet Pin PQFP Name Location p_par 106 p_perr_l 104 p_req_l 69 p_rst_l 64 p_serr_l 105 p_stop_l 101 p_trdy_l 99 p_vio 67 s_ad<0> 134 s_ad<1> 136 s_ad<2> 137 s_ad<3> 138 ...
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Table 3-4. Pin Signal List (Alphanumeric) (Sheet Pin PQFP Name Location vdd 40 vdd 46 vdd 56 vdd 60 vdd 75 vdd 80 vdd 90 vdd 98 vdd 108 vdd 116 vdd 120 vdd 125 vdd 131 ...
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PCI Bus Operation This chapter presents detailed information about PCI transactions, transaction forwarding across the 21152, and transaction termination. 4.1 Types of Transactions This section provides a summary of PCI transactions performed by the 21152. Table 4-1 lists the command ...
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PCI Bus Operation 4.2 Address Phase The standard PCI transaction consists of one or two address phases, followed by one or more data phases. An address phase always lasts one PCI clock cycle. The first address phase is designated by ...
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Device Select (DEVSEL#) Generation The 21152 always performs positive address decoding when accepting transactions on either the primary or secondary buses. The 21152 never subtractively decodes. Medium DEVSEL# timing is used on both interfaces. 4.4 Data Phase The address ...
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PCI Bus Operation 4.5.1 Posted Write Transactions Posted write forwarding is used for memory write and, for memory write and invalidate transactions. When the 21152 determines that a memory write transaction forwarded across the bridge, the 21152 ...
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Figure 4-1 shows a memory write transaction in flow-through mode, where data is being removed from buffers on the target interface while more data is being transferred into the buffers on the master interface. Figure 4-1. Flow-Through Posted Memory Write ...
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PCI Bus Operation 4.5.2 Memory Write and Invalidate Transactions Posted write forwarding is used for memory write and invalidate transactions. Memory write and invalidate transactions guarantee transfer of entire cache lines. If the write buffer fills before an entire cache ...
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Delayed Write Transactions Delayed write forwarding is used for I/O write transactions and for Type 1 configuration write transactions. A delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the initiating ...
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PCI Bus Operation Figure 4-2 shows a delayed write transaction forwarded downstream across the 21152. Figure 4-2. Downstream Delayed Write Transaction CY0 Cycle < 15ns > p_clk p_ad p_cbe_l p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l ...
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Write Transaction Address Boundaries The 21152 imposes internal address boundaries when accepting write data. The aligned address boundaries are used to prevent the 21152 from continuing a transaction over a device address boundary and to provide an upper limit ...
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PCI Bus Operation 4.5.6 Fast Back-to-Back Write Transactions The 21152 can recognize and post fast back-to-back write transactions. When the 21152 cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. When ...
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Read Transactions Delayed read forwarding is used for all read transactions crossing the 21152. Delayed read transactions are treated as either prefetchable or nonprefetchable. Table 4.4 shows the read behavior, prefetchable or nonprefetchable, for each type of read operation. ...
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PCI Bus Operation 4.6.2 Nonprefetchable Read Transactions A nonprefetchable read transaction is a read transaction where the 21152 requests 1—and only 1—Dword from the target and disconnects the initiator after delivery of the first Dword of read data. Unlike prefetchable ...
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Delayed Read Requests The 21152 treats all read transactions as delayed read transactions, which means that the read request from the initiator is posted into a delayed transaction queue. Read data from the target is placed in the read ...
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PCI Bus Operation 4.6.6 Delayed Read Completion on Initiator Bus When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted ...
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Figure 4-5 shows a prefetchable delayed read transaction. Figure 4-5. Prefetchable Delayed Read Transaction CY0 CY2 Cycle CY1 < 15ns > p_clk p_ad Addr p_cbe_l 6 Byte Enables p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l ...
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PCI Bus Operation Figure 4-6 shows a flow-through prefetchable read transaction. Figure 4-6. Flow-Through Prefetchable Read Transaction CY0 Cycle CY1 <15ns> p_clk p_ad Addr p_cbe_l 6 p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l The ...
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Configuration Transactions Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All 21152 registers are accessible in configuration space only. In addition to accepting configuration transactions ...
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PCI Bus Operation 4.7.1 Type 0 Access to the 21152 The 21152 configuration space is accessed by a Type 0 configuration transaction on the primary interface. The 21152 configuration space cannot be accessed from the secondary bus. The 21152 responds ...
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The 21152 asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the Type 1 address bits ...
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PCI Bus Operation 4.7.3 Type 1 to Type 1 Forwarding Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-to-PCI bridges are used. When the 21152 detects a Type 1 configuration ...
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When the 21152 initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. The address and data are forwarded unchanged. Devices that use special cycles ignore the address and decode only the ...
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PCI Bus Operation 4.8.1 Master Termination Initiated by the 21152 The 21152 initiator, uses normal termination if DEVSEL# is returned by the target within five clock cycles of the 21152’s assertion of FRAME# on the target bus. As ...
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Figure 4.8 shows a delayed write transaction that is terminated with a master abort. Figure 4.8 Delayed Write Transaction Terminated with Master Abort CY0 Cycle CY1 < 15ns > p_clk p_ad Addr p_cbe_l p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad ...
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PCI Bus Operation 4.8.3 Target Termination Received by the 21152 When the 21152 initiates a transaction on the target bus and the target responds with DEVSEL#, the target can end the transaction with one of the following types of termination: ...
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Posted Write Target Termination Response When the 21152 initiates a posted write transaction, the target termination cannot be passed back to the initiator. Table 4.8 shows the 21152 response to each type of target termination that occurs during a ...
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PCI Bus Operation Figure 4.9 shows a delayed read transaction that is terminated with a target abort. Figure 4.9 Delayed Read Transaction Terminated with Target Abort CY0 Cycle < 15ns > p_clk p_ad p_cbe_l p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk ...
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Target Termination Initiated by the 21152 The 21152 can return a target retry, target disconnect, or target abort to an initiator for reasons other than detection of that condition at the target interface. 4.8.4.1 Target Retry The 21152 returns ...
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PCI Bus Operation 4.8.4.2 Target Disconnect The 21152 returns a target disconnect to an initiator when one of the following conditions is met: • The 21152 hits an internal address boundary. • The 21152 cannot accept any more write data. ...
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Address Decoding The 21152 uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the 21152 configuration space. This chapter describes these address ranges, as well as ...
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Address Decoding 5.2.1 I/O Base and Limit Address Registers The 21152 implements one set of I/O base and limit address registers in configuration space that define an I/O address range for downstream forwarding. The 21152 supports 32-bit I/O addressing, which ...
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The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit field at offset 32h. The top 4 bits of the 8-bit field define bits <15:12> of the I/O limit address. The bottom 4 bits ...
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Address Decoding Figure 5-2 illustrates I/O forwarding when the ISA enable bit is set Figure 5-2. I/O Transaction Forwarding in ISA Mode. Primary Interface 5000h - FFFFh 4D00h - 4FFFh 4C00h - 4CFFh 4900h - 4BFFh 4800h - 48FFh 4500h ...
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VGA mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle. 5.3.1 Memory-Mapped I/O Base and Limit Address Registers ...
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Address Decoding Figure 5-3 shows how transactions are forwarded using both the memory-mapped I/O range and the prefetchable memory range. Figure 5-3. Memory Transaction Forwarding Using Base and Limit Registers Primary Interface DAC Prefetchable Memory Limit DAC SAC Prefetchable Memory ...
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Prefetchable Memory Base and Limit Address Registers Locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable memory location must ...
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Address Decoding 5.3.3 Prefetchable Memory 64-Bit Addressing Registers The 21152 supports 64-bit memory address decoding for forwarding of dual-address memory transactions. The dual-address cycle is used to support 64-bit addressing. The first address phase of a dual-address transaction contains the ...
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VGA Support The 21152 provides two modes for VGA support: • VGA mode, supporting VGA-compatible addressing • VGA snoop mode, supporting VGA palette forwarding 5.4.1 VGA Mode When a VGA-compatible device exists downstream from the 21152, set the VGA ...
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Address Decoding Note that these addresses are also forwarded as part of the VGA compatibility mode previously described. Again, address bits <15:10> are not decoded, while address bits <31:16> must be equal to 0, which means that these addresses are ...
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Transaction Ordering To maintain data coherency and consistency, the 21152 complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.1, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction forwarding ...
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Transaction Ordering 6.2 General Ordering Guidelines Independent transactions on the primary and secondary buses have a relationship only when those transactions cross the 21152. The following general ordering guidelines govern transactions crossing the 21152: • The ordering relationship of a ...
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Ordering Rules Table 6-1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow. Table 6-1. Summary of Transaction Ordering Pass Posted write Delayed read request Delayed write request Delayed read ...
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Transaction Ordering 5. Posted write transactions must be given opportunities to pass delayed read and write requests and completions. Otherwise, deadlocks may occur when bridges that support delayed transactions are used in the same system with bridges that do not ...
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Error Handling The 21152 checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, the 21152 always tries to forward the existing parity condition on one bus to the other bus, along with address and ...
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Error Handling 7.2 Data Parity Errors When forwarding transactions, the 21152 attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition. The ...
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For upstream transactions, when the 21152 detects a read data parity error on the primary bus, the following events occur: • The 21152 asserts p_perr_l two cycles following the data transfer, if the primary interface parity error response bit is ...
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Error Handling For downstream transactions, when the 21152 is delivering data to the target on the secondary bus and s_perr_l is asserted by the target, the following events occur: • The 21152 sets the secondary interface data parity detected bit ...
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For upstream transactions, in the case where the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: • The 21152 asserts s_perr_l ...
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Error Handling During upstream write transactions, when a data parity error is reported on the target (primary) bus by the target’s assertion of p_perr_l, the following events occur: • The 21152 sets the data parity detected bit in the status ...
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Data Parity Error Reporting Summary In the previous sections, the 21152’s responses to data parity errors are presented according to the type of transaction in progress. This section organizes the 21152’s responses to data parity errors according to the ...
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Error Handling Table 7-2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when the 21152 detects a parity error on the secondary interface. Table 7-2. Setting the ...
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Table 7-3 shows setting the data parity detected bit in the status register, corresponding to the primary interface. This bit is set under the following conditions: • The 21152 must be a master on the primary bus. • The parity ...
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Error Handling Table 7-4 shows setting the data parity detected bit in the secondary status register, corresponding to the secondary interface. This bit is set under the following conditions: • The 21152 must be a master on the secondary bus. ...
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Table 7-5 shows assertion of p_perr_l. This signal is set under the following conditions: • The 21152 is either the target of a write transaction or the initiator of a read transaction on the primary bus. • The parity error ...
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Error Handling Table 7-6 shows assertion of s_perr_l. This signal is set under the following conditions: • The 21152 is either the target of a write transaction or the initiator of a read transaction on the secondary bus. • The ...
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Table 7-7 shows assertion of p_serr_l. This signal is set under the following conditions: • The 21152 has detected p_perr_l asserted on an upstream posted write transaction or s_perr_l asserted on a downstream posted write transaction. • The 21152 did ...
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Error Handling 7.4 System Error (SERR#) Reporting The 21152 uses the p_serr_l signal to report conditionally a number of system error conditions in addition to the special case parity error conditions described in Whenever the assertion of p_serr_l is discussed ...
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Exclusive Access This chapter describes the use of the LOCK# signal to implement exclusive access to a target for transactions that cross the 21152. 8.1 Concurrent Locks The primary and secondary bus lock mechanisms operate concurrently except when a locked ...
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Exclusive Access When the locked delayed read request transaction moves to the head of the delayed transaction queue, the 21152 initiates the transaction as a locked read transaction by deasserting s_lock_l on the secondary bus during the first address phase, ...
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Ending Exclusive Access After the lock has been acquired on both the primary and secondary buses, the 21152 must maintain the lock on the secondary (target) bus for any subsequent locked transactions until the initiator relinquishes the lock. The ...
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PCI Bus Arbitration The 21152 must arbitrate for use of the primary bus when forwarding upstream transactions, and for use of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to the 21152, typically ...
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PCI Bus Arbitration 9.2.1 Secondary Bus Arbitration Using the Internal Arbiter To use the internal arbiter, the secondary bus arbiter enable pin, s_cfn_l, must be tied low. The 21152 has four secondary bus request input pins, s_req_l<3:0>, and four secondary ...
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PCI clock cycle. When priorities are reevaluated, the highest priority is assigned to the next highest priority master relative to the master that initiated the previous transaction. The master that initiated the last transaction now ...
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Clocks This chapter provides information about the 21152 clocks. 10.1 Primary and Secondary Clock Inputs The 21152 implements a separate clock input for each PCI interface. The primary interface is synchronized to the primary clock input, p_clk, and the secondary ...
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Clocks 10.2 Secondary Clock Outputs The 21152 has five secondary clock outputs, s_clk_o<4:0>, that can be used as clock inputs for up to four external secondary bus devices and for the 21152 secondary clock input. The s_clk_o outputs are derived ...
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Reset This chapter describes the primary interface, secondary interface, and chip reset mechanisms. 11.1 Primary Interface Reset The 21152 has one reset input, p_rst_l. When p_rst_l is asserted, the following events occur: • The 21152 immediately tristates all primary and ...
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Reset 11.3 Chip Reset The chip reset bit in the diagnostic control register can be used to reset the 21152 and secondary bus. When the chip reset bit is set, all registers and chip state are reset and all signals ...
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PCI Power Management The 21152–AB incorporates functionality that complies fully with the Advanced Configuration Power Interface (ACPI) and the PCI Power Management Specification. These features include: • PCI Power Management registers using the enhanced capabilities port (ECP) address mechanism • ...
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Configuration Space Registers This chapter provides a detailed description of the 21152 configuration space registers. The chapter is divided into two sections: registers, and Section 13.2 The 21152 configuration space uses the PCI-to-PCI bridge standard format specified in the PCI-to-PCI ...
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Configuration Space Registers Figure 13-1 shows a summary of configuration space. Figure 13-1. 21152 Configuration Space 31 Reserved Secondary Latency Timer Secondary Status Memory Limit Address Prefetchable Memory Limit Address I/O Limit Address Upper 16 Bits Reserved Reserved Power Management ...
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... Dword address = 00h Byte enable p_cbe_l<3:0> = 00xxb Dword Bit Name 31:16 Device ID 21152 PCI-to-PCI Bridge Preliminary Datasheet R/W Description R Identifies Intel Corporation as the vendor of this device. Internally hardwired to be 1011h. R/W Description R Identifies this device as the 21152. Internally hardwired to be 24h. Configuration Space Registers 13-3 ...
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Configuration Space Registers 13.1.3 Command Register — Offset 04h This section describes the command register. These bits affect the behavior of the 21152 primary interface, except where noted. Some of the bits are repeated in the bridge control register, to ...
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Dword Bit Name 5 VGA snoop enable 6 Parity error response 7 Wait cycle control 8 SERR# enable 9 Fast back-to-back enable 15:10 Reserved 21152 PCI-to-PCI Bridge Preliminary Datasheet R/W Description R/W Controls the 21152’s response to VGA-compatible palette write ...
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Configuration Space Registers 13.1.4 Status Register — Offset 06h This section describes the status register. These bits affect the status of the 21152 primary interface. Bits reflecting the status of the secondary interface are found in the secondary status register. ...
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Revision ID Register — Offset 08h This section describes the revision ID register. Dword address = 08h Byte enable p_cbe_l<3:0> = xxx0b Dword Bit Name 7:0 Revision ID 13.1.6 Programming Interface Register — Offset 09h This section describes the ...
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Configuration Space Registers 13.1.8 Base Class Code Register — Offset 0Bh This section describes the base class code register. Dword address = 08h Byte enable p_cbe_l<3:0> = 0xxxb Dword Bit Name 31:24 Base class code 13.1.9 Cache Line Size Register ...
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Header Type Register — Offset 0Eh This section describes the header type register. Dword address = 0Ch Byte enable p_cbe_l<3:0> = x0xxb Dword Bit Name 23:16 Header type 13.1.12 Primary Bus Number Register — Offset 18h This section describes ...
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Configuration Space Registers 13.1.14 Subordinate Bus Number Register — Offset 1Ah This section describes the subordinate bus number register. This register must be initialized by configuration software. Dword address = 18h Byte enable p_cbe_l<3:0> = x0xxb Dword Bit Name 23:16 ...
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I/O Base Address Register — Offset 1Ch This section describes the I/O base address register. This register must be initialized by configuration software. Dword address = 1Ch Byte enable p_cbe_l<3:0> = xxx0b Dword Bit Name 3:0 32-bit indicator 7:4 ...
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Configuration Space Registers 13.1.18 Secondary Status Register — Offset 1Eh This section describes the secondary status register. These bits reflect the status of the 21152 secondary interface. W1TC indicates that writing 1 to that bit sets the bit to 0. ...
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Memory Base Address Register — Offset 20h This section describes the memory base address register. This register must be initialized by configuration software. Dword address = 20h Byte enable p_cbe_l<3:0> = xx00b Dword Bit Name 3:0 Reserved 15:4 Memory ...
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Configuration Space Registers 13.1.21 Prefetchable Memory Base Address Register — Offset 24h This section describes the prefetchable memory base address register. This register must be initialized by configuration software. Dword address = 24h Byte enable p_cbe_l<3:0> = xx00b Dword Bit ...
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Prefetchable Memory Base Address Upper 32 Bits Register — Offset 28h This section describes the prefetchable memory base address upper 32 bits register. This register must be initialized by configuration software. Dword address = 28h Byte enable p_cbe_l<3:0> = ...
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Configuration Space Registers 13.1.25 I/O Base Address Upper 16 Bits Register — Offset 30h This section describes the I/O base address upper 16 bits register. This register must be initialized by configuration software. Dword address = 30h Byte enable p_cbe_l<3:0> ...
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Capabilities Pointer Register — Offset 34h This section describes the capabilities pointer register. Dword address = 34h Byte enable p_cbe_l<3:0> = 0000b Dword Bit Name 7:0 ECP_PTR 31:8 Reserved 13.1.28 Interrupt Pin — Offset 3Dh This section describes the ...
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Configuration Space Registers 13.1.29 Bridge Control — Offset 3Eh This section describes the bridge control register. This register must be initialized by configuration software. Dword address = 3Eh Byte enable p_cbe_l<3:0> = 00xxb Dword Bit Name 16 Parity error response ...
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Dword Bit Name 19 VGA enable 20 Reserved 21 Master abort mode 22 Secondary bus reset 23 Fast back-to-back enable 24 Primary master time-out 21152 PCI-to-PCI Bridge Preliminary Datasheet R/W Description R/W Modifies the 21152’s response to VGA-compatible addresses. When ...
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Configuration Space Registers Dword Bit Name 25 Secondary master timeout 26 Master timeout status 27 Master timeout SERR# enable 31:28 Reserved 13-20 R/W Description R/W Sets the maximum number of PCI clock cycles that the 21152 waits for an initiator ...
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Capability ID Register — Offset DCh This section describes the capability ID register. (Implemented in the 21152-AB and later revisions only. In the 21152-AA, this register is reserved.) Dword address = DCh Byte enable p_cbe_l<3:0> = xxx0b Dword Bits ...
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Configuration Space Registers 13.1.32 Power Management Capabilities Registers — Offset DEh This section describes the power management capabilities registers. (Implemented in the 21152-AB and later revisions only. In the 21152-AA, this register is reserved.) Dword address = DCh Byte enable ...
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Power Management Control and Status Registers — Offset E0h This section describes the power management control and status registers. (Implemented in the 21152-AB and later revisions only. In the 21152-AA, this register is reserved.) Dword address = E0h Byte ...
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Configuration Space Registers 13.1.34 PPB Support Extensions Registers — Offset E2h This section describes the PPB support extensions registers. (Implemented in the 21152-AB and later revisions only. In the 21152-AA, this register is reserved.) Dword address = E0h Byte enable ...
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Device-Specific Configuration Registers This section provides a detailed description of the 21152 device-specific configuration registers. Each field has a separate description. Fields that have the same configuration address are selectable by turning on (driving low) the appropriate byte enable ...
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Configuration Space Registers 13.2.2 Diagnostic Control Register — Offset 41h This section describes the diagnostic control register. W1TR indicates that writing 1 in this bit position causes a chip reset to occur. Writing 0 has no effect. Dword address = ...
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Event Disable Register -— Offset 64h This section describes the p_serr_l event disable register. Dword address = 64h Byte enable p_cbe_l<3:0> = xxx0b Dword Bit Name 0 Reserved 1 Posted write parity error 2 Posted write nondelivery 3 ...
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Configuration Space Registers 13.2.5 Secondary Clock Control Register — Offset 68h This section describes the secondary clock control register. Dword address = 68h Byte enable p_cbe_l<3:0> = xx00b Dword Bit Name 1:0 Clock 0 disable 3:2 Clock 1 disable 5:4 ...
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Status Register — Offset 6Ah This section describes the p_serr_l status register. This status register indicates the reason for the 21152’s assertion of p_serr_l. Dword address = 68h Byte enable p_cbe_l<3:0> = x0xxb Dword Bit Name 0 Address ...
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Diagnostic Nand Tree The 21152 implements two pins for testing purposes: • The goz_l pin, when asserted, tristates all bidirectional pins. • The nand_out pin is the output of a serial Nand tree connecting all chip inputs except p_clk and ...
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Electrical Specifications This chapter specifies the following electrical behavior of the 21152: • PCI electrical conformance • Absolute maximum ratings • dc specifications • ac timing specifications 15.1 PCI Electrical Specification Conformance The 21152 PCI pins conform to the basic ...
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Electrical Specifications 15.3 DC Specifications Table 15-3 defines the dc parameters met by all 21152 signals under the conditions of the functional operating range. Table 15-3. DC Parameters Symbol Parameter V Supply voltage cc V Low-level input voltage il V ...
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Clock Timing Specifications The ac specifications consist of input requirements and output responses. The input requirements consist of setup and hold times, pulse widths, and high and low times. Output responses are delays from clock to signal. The ac ...
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Electrical Specifications 15.4.2 PCI Signal Timing Specifications Figure 15-2 and Table 15-5 Figure 15-2. PCI Signal Timing Measurement Conditions Table 15-5. PCI Signal Timing Symbol Parameter T CLK to signal valid delay — bused signals val T CLK to signal ...
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Reset Timing Specifications Table 15-6 shows the reset timing specifications for p_rst_l and s_rst_l. Table 15-6. Reset Timing Specifications Symbol Parameter T p_rst_l active time after power stable rst T p_rst_l active time after p_clk stable rst-clk T p_rst_l ...
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Mechanical Specifications The 21152 is contained in an industry-standard 160-pin plastic quad flat pack (PQFP) package, shown in Figure 16-1. Figure 16-1. 160-Pin PQFP Package Pin 1 160-Pin PQFP (A) A2 Detail "A" A1 21152 PCI-to-PCI Bridge Preliminary Datasheet - ...
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Mechanical Specifications Table 16-1 lists the 160-pin package dimensions in millimeters. Table 16-1. 160-Pin PQFP Package Dimensions Symbol Dimension LL Lead length e Lead pitch L Foot length A Package overall height A1 Package standoff height A2 Package thickness b ...
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Configuration Register Values After Reset Table A-1 lists the value of the 21152 configuration registers after reset. Reserved registers are not listed and are always read only as 0. Table A-1. Configuration Register Values After Reset (Sheet ...
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Configuration Register Values After Reset Table A-1. Configuration Register Values After Reset (Sheet Byte Address 40h 41h 42–43h 64h 68–69h 6Ah DCh DDh DE–DFh E0–E1h E2h E3h 1. 21152–AA. 2. 21152–AB and later revisions. 3. Dependent on ...
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Support, Products, and Documentation If you need technical support, a Product Catalog, or help deciding which documentation best meets your needs, visit the Intel World Wide Web Internet site: http://www.intel.com Copies of documents that have an ordering number and are ...
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