CS4331-KSR Cirrus Logic, Inc., CS4331-KSR Datasheet
CS4331-KSR
Related parts for CS4331-KSR
CS4331-KSR Summary of contents
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... D/A conversion and output analog filtering pin package. These devices differ in the serial interface format used to input audio data. The CS4330, CS4331 and CS4333 are based on delta- sigma modulation, where the modulator output controls the reference voltage input to an ultra-linear analog low- pass filter ...
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... 0 250 - - 3.33 3.70 4.07 1. 100 - - IA IA 140 160 - - 0 PSRR - CS4330, CS4331, CS4333 CS4330/31/33-BS VA +3V VA +5V only Typ Max Min Typ Max to 70 - 0.003 - - .003 .008 -85 -80 -88 -86 -79 - -72 -66 - -32 - 0.5 0.5 to 21. 21. 0.1 0 0.05 0.05 26. ...
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... MCLK / LRCK = 384 MCLK / LRCK = 256 MCLK / LRCK = 256 t sclkl t sclkh t sclkw t slrd t slrs t sdlrs t sdh (Note 6) t sclkw t sclkr t sdlrs MCLK / LRCK = 256 or 512 t sdh MCLK / LRCK = 384 t sdh CS4330, CS4331, CS4333 Min Typ Max 1000 15 - 1000 21 ...
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... LRCK SCLK SDATA **INTERNAL SCLK * LRCK for CS4331 ** The SCLK pulses shown are internal to the CS4330/31/33. LRCK MCLK *INTERNAL SCLK SDATA * The SCLK pulses shown are internal to the CS4330/31/33 slrs t slrd t t sdlrs External Serial Mode Input Timing *LRCK t sclkr ...
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... DIGITAL CHARACTERISTICS Parameter High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Notes for CS4331 LRCK is in ABSOLUTE MAXIMUM RATINGS Parameter DC Power Supply: Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature WARNING: Operation at or beyond these limits may result in permanent damage to the device. ...
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... Audio 2 Data DEM/SCLK Processor 3 LRCK 4 External Clock MCLK AOUTL + CS4330 CS4331 CS4333 AOUTR + AGND 6 * Required for AC coupling only ** )(2400 )(Fs)(2) Figure 1. Recommended Connection Diagram CS4330, CS4331, CS4333 +3V/+ 2.4k Left Audio C 56k * ** * 2.4k Right Audio C 56k * ** * 1 Output Output DS136F1 ...
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... GENERAL DESCRIPTION The CS4330, CS4331, and CS4333 are complete stereo digital-to-analog systems including digital interpolation, 128 third-order delta-sigma digi- tal-to-analog conversion, digital de-emphasis and analog filtering, Figure 2. This architecture pro- vides a high tolerance to clock jitter. The primary purpose of using delta-sigma modu- ...
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... Serial Clock (SCLK) clocks audio data into the input data buffer. The CS4330, CS4331 and CS4333 differ in the serial data for- mat as shown in Figures 4-7. The Master Clock (MCLK) is used to operate the digital interpola- tion filter and the delta-sigma modulator ...
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... The digital filter of the CS4330/31/33 is de- signed to compensate for the magnitude and phase response of a single-pole low-pass filter at twice the sample rate. Output filters consisting of a 2.4 kohm resistor and capacitor are recom- CS4330, CS4331, CS4333 9 ...
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... INT SCLK = MCLK/LRCK = 384 Left Channel LRCK SCLK SDATA Figure 5. CS4331 Internal SCLK Data Format ( External SCLK Mode Right Justified, 18-Bit Data Data Valid on Rising Edge of SCLK SCLK must have at least 36 cycles per LRCK Figure 4 ...
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... External SCLK Mode 18-Bit Data Data Valid on Rising Edge of SCLK SCLK must have at least 36 cycles per LRCK Figure 6. CS4331 External SCLK Data Format ( External SCLK Mode Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK must have at least 32 cycles per LRCK Figure 7 ...
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... USER: Apply MCLK and LRCK 256/384/512 MCLK/LRCK Determination Power Supply Determination + Volt mode USER: set SCLK mode SCLK mode internal Normal Operation De-emphasis available not available USER: Apply SDATA CS4330, CS4331, CS4333 USER: Remove Clocks external Analog Output is Generated DS136F1 ...
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... Filter Stopband Rejection Figure 10. CS4330/31/33 Combined Digital and Analog Filter Transition Band DS136F1 CS4330, CS4331, CS4333 Combined Digital and Analog Filter Response The frequency response of the combined analog switched-capacitor filter, digital filter, and off- chip single pole RC-filter at 2 Fs, is shown in Figures 9, 10, 11, and 12 ...
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... Figure 18 shows a 16k FFT kHz -60 dBFs input signal. Figure 19 shows a 16k FFT kHz -90 dBFs input signal. Figure 20 shows the fade-to-noise linearity. The input signal is a dithered 18-bit 500 Hz sine 14 0.1dB Figure 13. Frequency Response Figure 14. THD+N vs. Amplitude Figure 15. 0 dBFs FFT CS4330, CS4331, CS4333 DS136F1 ...
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... This indicates very good low-level linearity, one of the key benefits of delta-sigma digital-to-analog conver- sion. Figure 16. -3 dBFs FFT Figure 17. -20 dBFs FFT DS136F1 CS4330, CS4331, CS4333 Figure 18. -60 dBFs FFT Figure 19. -90 dBFs FFT Figure 20. Fade-to-Noise Linearity 15 ...
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... Configuration Register The CS4330, CS4331, CS4333 support multiple 2’s-complement data/clock formats. The required format is governed by the contents of the Con- figuration Register. The 5-bit register determines which serial data format is acceptable, the fre- quency of the Internal Serial Clock, on which edge of SCLK audio data must be valid, and the number of bits to be loaded into the input buffer ...
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... DEM/SCLK valid to LRCK falling setup time LRCK falling to DEM/SCLK hold time SDATA setup time SDATA hold time DS136F1 Figure 21. Configuration Operation Figure 22. Configuration Timing Symbol t clrs t clrh t setup t hold Table 2. Configuration Timing Characteristics CS4330, CS4331, CS4333 Min Typ Max Units ...
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... Audio Engineering Society, March 1992. 4)"An 18-Bit Stereo D/A Converter With Inte- grated Digital and Analog Filters" by Nav S. Sooch, Jeffrey W. Scott. Paper presented at the 91st Convention of the Audio Engineering Soci- ety, November 1991. 5)CDB4330/31/33 Evaluation board Data Sheet; DS136DB2 MAR’96 18 CS4330, CS4331, CS4333 DS136F1 ...
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... SDATA. SDATA - Audio Serial Data Input, PIN 1. Two’s complement MSB-first serial data is input on this pin. The data is clocked into the CS4330, CS4331, and CS4333 via internal or external SCLK and the channel is determined by LRCK. DEM/SCLK - De-emphasis / External serial clock input , PIN 2. ...
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... Interchannel Gain Mismatch - The gain difference between left and right channels. Units in decibels. Gain Error - The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift - The change in gain value with temperature. Units in ppm CS4330, CS4331, CS4333 DS136F1 ...
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... Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC DIM 8-Pin A SOIC CS4330, CS4331, CS4333 MILLIMETERS INCHES MIN MAX MIN MAX 5.15 5.35 0.203 0.210 1.27 TYP 0.050 TYP 0 0.25 0 0.010 1.77 1.88 0.070 ...
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Notes • ...
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... Evaluation Board for CS4330 / CS4331 / CS4333 Features Demonstrates recommended layout and grounding arrangements CS8412 Receives AES/EBU, S/PDIF, & EIAJ-340 Compatible Digital Audio Digital and Analog Patch Areas Requires only a digital signal source and power supplies for a complete Digital-to-Analog-Converter system Digital ...
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... Figures 4-7 of the CS4330/31/33 datasheet. The default settings for M0-M3 on the evaluation board are given in Tables 2-4. The compatible data formats we have chosen for the CS8412 and CS4330/31/33 are: CS8412 format 6;CS4330 CS8412 format 2;CS4331 (External SCLK only) CS8412 format 5;CS4333 (External SCLK only) DS136DB2 ...
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Analog output filter The recommended single pole filter required for the CS4330/31/33 has been combined with a unity gain output buffer (see Figure 2). The ana- log output filter uses a Motorola MC33202 single supply, dual op-amp. The low pass ...
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CONNECTOR INPUT/OUTPUT +5V +3/+5V GND Digital Input Optical Input MCLK, SCLK, input/output LRCK SDATA input/output AOUTL AOUTR JUMPER PURPOSE selects channel for CSLR/FCK CS8412 channel status information Clock Selects source of Select system clocks and data J22 Selects MCLK as ...
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... M2 M3 SCLK Selects SCLK Mode Selects source of de- DEM_8412 emphasis control * Default setting from factory Note 1. The CS8412 output data format requires the CS4331 be in the External SCLK Mode JUMPER PURPOSE selects channel for CSLR/FCK CS8412 channel status information Clock Selects source of ...
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Digital I/O for Audio Clocks Input and Data Fig 6 Fig 5 MCLK LRCK SCLK SDATA CS8412 Digital Audio Power Interface Down Fig 3 Fig 4 28 MCLK Voltage LRCK Level SCLK Converter SDATA Fig 3 Figure 1. System Block ...
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Figure 2. CS4330/31/33 and Connections ...
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Figure 3. Voltage Level Conversion and Power Down Circuitry 30 CDB4330, CDB4331, CDB4333 DS136DB2 ...
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NOTE: U2 and U5 cannot be installed simultaneously Figure 4. CS8412 Digital Audio Receiver Connections ...
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Optical Toshiba part TORX173 available through Insight Electronics 32 Figure 5. I/O Interface for Clocks and Data Figure 6. Digital Audio Input CDB4330, CDB4331, CDB4333 DS136DB2 ...
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DS136DB2 CDB4330, CDB4331, CDB4333 Figure 7. Power Supply 33 ...
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Figure 8. CDB4330/31/33 Component Side Silkscreen 34 CDB4330, CDB4331, CDB4333 DS136DB2 ...
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DS136DB2 Figure 9. CDB4330/31/33 Component Side (top) CDB4330, CDB4331, CDB4333 35 ...
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Figure 10. CDB4330/31/33 Solder Side (bottom) CDB4330, CDB4331, CDB4333 DS136DB2 ...
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Notes • ...
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... Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions ...