LSI53C040 LSI Computer Systems, Inc., LSI53C040 Datasheet
LSI53C040
Related parts for LSI53C040
LSI53C040 Summary of contents
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... TECHNICAL MANUAL LSI53C040 Enclosure Services Processor Version 2 ® DB14-000125-02 ...
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... Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic officer is prohibited. Document DB14-000125-02, Fourth Edition (June 2002) This document describes the LSI Logic LSI53C040 Enclosure Services Processor and will remain the official reference source for all revisions/releases of this product until rescinded by an update. ...
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... SCSI or Fibre Channel peripheral device enclosures. Organization This document has the following chapters and appendix: Chapter 1, LSI53C040, including an overview of its features and functions. Chapter 2, Functional the chip in more detail, including the major interfaces. Chapter 3, Signal descriptions of each signal. ...
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Chapter 9, Electrical conditions and AC timings for the chip and mechanical drawings. Appendix A, Register Summary Related Publications For background information, please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X ...
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The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Signals that are active LOW end in a “/.” Hexadecimal numbers are indicated by the prefix “0x” —for ...
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Preface ...
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... Contents Chapter 1 Introduction 1.1 LSI53C040 Overview 1.2 SCSI Mode 1.3 SFF-8067 Mode 1.4 Features Summary Chapter 2 Functional Description 2.1 Functional Blocks 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.2 Memory Map 2.3 SCSI Core Operation 2.3.1 2.3.2 2.3.3 2.3.4 2.4 DMA Function 2.5 Microcontroller Operation 2.5.1 2.6 Two-Wire Serial Interface Operation 2.6.1 2.6.2 2.6.3 2.6.4 Contents LSI53C80-Based SCSI Control Logic 80C32 Microcontroller Core Two-Wire Serial Interface SFF-8067 Interface ...
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Power-On Configuration Options 2.7.1 2.7.2 2.7.3 2.7.4 2.8 Resets 2.9 SFF-8067 Mode 2.10 Interrupts 2.10.1 2.10.2 2.10.3 2.10.4 2.10.5 2.10.6 2.10.7 2.11 JTAG Boundary Scan Testing Chapter 3 Signal Descriptions 3.1 Safety Mode Signals 3.1.1 3.1.2 3.1.3 3.1.4 ...
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... Reset Signal External Memory Interface External Data Read Cycle External Data Write Cycle Initiator Asynchronous Send Initiator Asynchronous Receive Target Asynchronous Send Target Asynchronous Receive SCSI/SAF-TE Enclosure Implementation SFF-8067/SES Enclosure Implementation LSI53C040 Block Diagram LSI53C040 Memory Map Initiating Arbitration and Selection/Reselection 9-2 9-3 9-7 9-11 9-11 9-12 9-13 9-13 9-14 ...
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... Serial Write Operation Serial ROM Download Two-Wire Serial Slave Data Transmit and Receive Two-Wire Serial Master Data Transmit and Receive LSI53C040 SFF-8067 Interface Control State Diagram LSI53C040, 160-Pin QFP Option LSI53C040 169-Ball BGA Top View LSI53C040 Functional Pin Description Register Set Overview ...
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... External Pull-up Values for Automatic Branch Generation Serial ROM Chip Addresses Register Bits for Interrupt Handling Interrupt Handling LSI53C040 160-Pin QFP Pin List (Alphabetically by Signal Name) LSI53C040 160-Pin QFP Pin List (Numerically by Pin Number) Miscellaneous Signals SCSI Signals JTAG Signals Power and Grounds Signals ...
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... Bidirectional Signals—MPIO0[7:0], MPIO1[7:0], MPIO2[7:0], MPIO3[3:0] Bidirectional Signals—MPLED0[7:0], MPLED1[7:0], MPLED2[7:0] TolerANT Technology Electrical Characteristics for SE SCSI Signals LSI53C040 Clock Timings Reset Timings External Memory Interface Timings External Data Read Timings External Data Write Timings Multipurpose I/O and LED Timings Two-Wire Serial Interface Timings, Normal Mode ...
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Target Asynchronous Receive Timings A.1 Register Summary by Description A.2 Register Summary by Address Contents 9-23 A-1 A-5 xiii ...
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Contents ...
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... Channel enclosures. It supports the SCSI Accessed Fault-Tolerant Enclosures (SAF-TE) and SCSI-3 Enclosure Services (SES) enclosure specifications. The enclosure monitoring services in the LSI53C040 allow a single chip solution for monitoring disk drives, power supplies, cooling systems, and other system services. Support for standard protocols such as SAF-TE ...
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... SCSI Mode The LSI53C040 uses the SCSI bus to report system information such as enclosure temperature, power supply status, and disk slot status to the host SCSI controller. It also responds to host SCSI controller commands by generating control outputs to enable and disable disk slots, drive indicator displays, or perform other system tasks. The LSI53C040 supports Low Voltage Differential (LVD) access as well as Single-Ended (SE) SCSI access without the need for external transceivers ...
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... SFF-8067 Mode As an alternative to SCSI, the two SFF-8067 interfaces in the LSI53C040 allow it to communicate data between a Fibre Channel enclosure and the Fibre Channel host, using the SFF-8067 physical interface and the SES protocol to monitor the power supply, cooling system, and other alarms or status indicators in the enclosure ...
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... Features Summary The following are the key features of the LSI53C040 as they relate to flexibility, integration, ease of use, reliability, and performance. Supports the SAF-TE protocol in SCSI environments, and the SES protocol in either SCSI or Fibre Channel environments Two SFF-8067 interfaces provided for Fibre Channel Enclosure applications 28 multipurpose I/O pins and 24 multipurpose LED drivers for fl ...
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... Chapter 2 Functional Description This chapter describes the main functional blocks of the LSI53C040. Figure 2 high-level functional overview of the device, followed by a high-level description of each item. The remainder of the chapter describes these functional areas in more detail. Section 2.1, “Functional Blocks” Section 2.2, “Memory Map” ...
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... Figure 2.1 LSI53C040 Block Diagram 16 K SRAM Microcontroller Address/Data Bus External RAM or ROM (Optional) LSI53C80- Based SCSI Control Logic Mux SE or LVD 8-Bit or SCSI Bus 2-2 Functional Description Two-Wire 80C32 Serial Microcontroller Interface DMA Function SFF8067 Mode Control Logic Two SSF8067 Bidirectional Connections ...
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... Following are brief descriptions of the main functional blocks comprising the LSI53C040. 2.1.1 LSI53C80-Based SCSI Control Logic The SCSI core in the LSI53C040 is based on the LSI53C80 SCSI controller. The LSI53C80 is a first generation SCSI protocol controller that provides simple, register-based access to SCSI control and data signals ...
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... SCSI device. Details of the protocol are provided in the SFF-8067 draft specification. 2.1.5 16 Kbytes SRAM The LSI53C040 contains 16 Kbytes of internal static RAM for data and firmware storage. Under microcontroller control, the internal RAM may be loaded with additional firmware from an external parallel ROM, or automatically from a serial EEPROM using the Two-Wire Serial interface ...
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... However, the LSI53C040 contains some additional logic that allows the device to have three SCSI high IDs, in addition to 0–7, so that the LSI53C040 can be given lower priority on a wide SCSI bus. However, the LSI53C040 cannot perform selection or reselection on a wide bus; parity ...
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... This limits the LSI53C040 to only target applications, with no disconnects wide bus. To select a high ID for the LSI53C040, connect any of the SCSI high data lines (8–15) to one of the SHID[2:0] pins. The user can monitor the value of the SHID[2:0] pins by reading the SHID[2:0] bits in the Data High (CSDHI) register allows a bit to be set that corresponds to the device SCSI ID ...
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Figure 2.3 Initiating Arbitration and Selection/Reselection Write ID Bit to Output Data Register (Reg. 0xFC00) Set ARB (0xFC02 Bit 0) Set AS_LVD (0xFC02 Bit 7)*** Reset ARB (0xFC02 Bit 0) Check Arb. In Prog. Bit (0xFC01 Bit ...
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... The LSI Logic LVDlink transceivers operate in LVD and SE modes. The LSI53C040 automatically detects which type of signal is connected, based on voltage detected by the DIFFSENS pin. The RBIAS+ and RBIAS signals are the bias resistors for LVD operation ...
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A Target Send operation begins when the ACD (Assert C_D/), AIO (Assert I_O/), and AMSG (Assert MSG/) bits in the (TC) register are set to the correct state so that a phase match exists. In addition to the phase match ...
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Figure 2.5 Target Receive Set Info. Transfer Phase (0xFC03 Bits [2:0] Target Send Only Target Send Only Target Receive Only 2-10 Functional Description Programmed I/O Target Transfers Target Send Set Info. Transfer Phase (0xFC03 Bits [2:0] Set Transfer Counter in ...
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... SCSI - DMA Transfers In the LSI53C040, DMA handshaking with the SCSI core is handled automatically by the DMA function. In order to initiate a DMA transfer to the SCSI core using the DMA function in the LSI53C040, the following sequence must be performed: 1. The Source/Destination Low (DSDL) (DSDH) 2. The (TIP) position. ...
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Figure 2.6 DMA Target Mode Transfers Write IMR (0xFE0D) to Enable only DMA Interrupts Write Transfer Length to DTL Register (0xFC11) Write Source/ Destination Addresses to 0xFC12, 0xFC13 Set TIP Bit In 0xFC10 Bit 0 Set DM, and TGTM Bits ...
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... DMA Function The LSI53C040 DMA function is designed to automatically handshake with the SCSI core for SCSI send and receive operations. For SCSI send operations, the DMA reads a byte from memory and writes it to the SCSI core when requested. For receive operations, the DMA receives a byte from the SCSI core and writes it to memory ...
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... However, the DMA feature cannot be used when the microcontroller is in ONCE mode. This is because the DMA logic inside the LSI53C040 looks for a signal from the microcontroller to indicate that it is halted before beginning any DMA operation. ONCE mode does not provide this signal to the DMA logic. ...
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... Two-Wire Serial port with full multimaster and slave capability that can communicate with external Two-Wire Serial devices. The Two-Wire Serial interface in the LSI53C040 provides the microcontroller an additional means to gather external system information. The Two-Wire Serial interface supported by the LSI53C040 is compliant with the Inter-Integrated Circuit bus defi ...
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... See register in the Two-Wire Serial register block. 2.6.2 Power-On Serial ROM Download At power-on, the Two-Wire Serial interface in the LSI53C040 attempts to read from a serial EEPROM with slave address 0b1010, and a chip address defined at power-on through the use of external pull-up/pull- down options on signal pins A10, A9, and A8. These options are summarized in skipped if no pull-up resistor is used on signal pin AD5 ...
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Figure 2.10 Serial ROM Download Address High Byte Register 0xFD05 Device ID 0 RAH[7:0] R/W Master Bit Slave ACK On a power-on reset soft-chip reset (watchdog timer expires or the RESET/ pin toggles), the download logic will ...
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... Manually Accessing External Two-Wire Serial Devices The LSI53C040 Two-Wire Serial interface allows the microcontroller core to manually access external two-wire devices such as temperature sensors, A/D converters, memory devices or any other I/O device that adheres to the standard Two-Wire Serial protocol ...
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... R Write? (LSB = Read Byte From Control/Status Register PIN Bit = 0? Yes Stop Detected? (STS = 1?) No Read Data From Data Register Read Last Data Byte From Data Register (set to 1), LSI53C040 goes into slave End Receive receiver mode Slave Receive No Yes 2-19 ...
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Figure 2.12 Two-Wire Serial Master Data Transmit and Receive Set ES0 Bit In Register 0xFD01 Read Status Register (0xFD01) Yes BB_N = 0? (0xFD01 Bit 0) No Write Device ID To Data Register (0xFD00) Set Start Bit In Control Register ...
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... Three address destinations are possible for this initial automatic jump, configurable by external pull-up resistors on the AD0 and AD1 pins. The states of these pins are checked on chip reset. In the LSI53C040, the AD0 and AD1 signal pins have internal pull-down resistors, so these pins power-up deasserted if no external pull-up is used ...
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... AD0 and AD1 can be read in the register (0xFF01) bits 0 and 1, respectively. 2.7.2 External Serial ROM Configuration The LSI53C040 can attempt to download firmware from a serial ROM at power-on, through the Two-Wire Serial interface. The serial ROM download is performed immediately at power-on or after a reset, and the microcontroller will hold off from fetching its fi ...
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... A pull-up resistor on the A11 pin starts the download from Two-Wire Serial port 1, after a reset or at power-on. 2.8 Resets The LSI53C040 can be reset in three different ways: power-on reset, asserting the reset pin, and an internal chip reset forced by expiration of the watchdog timer. A power-on reset initializes all chip registers to their default values and returns the Two-Wire Serial port and the SCSI or SFF-8067 interfaces to idle states ...
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... If the Enable Reset Output bit is also set (0xFF05, bit 7), the RESET/ pin is asserted low (0) to reset external devices. The Watchdog Reboot bit is set (0xFE00, bit 7) to indicate that the LSI53C040 has performed a soft reset due to expiration of the watchdog timer. Not all register values in the LSI53C040 are affected by a soft reset ...
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... Fibre Channel device has written a byte of data to the interface. The microcontroller responds by clearing the interrupt and reading the WDATA register. The LSI53C040 SFF-8067 interface control is illustrated in a state diagram in Port access is terminated when the PARALLEL ESI/ pin is deasserted. If the PARALLEL ESI/ pin of the other port is asserted at that time it will be granted access ...
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... Figure 2.13 LSI53C040 SFF-8067 Interface Control State Diagram RESET/ or PESI/ High Discovery Phase DSK_RD/ & DSK_WR/ Deasserted Signal Name PESI/ (PARALLEL_ESI/) Drive D[3:0] ENCL_ACK/ DSK_RD/ DSK_WR/ *Items marked with an asterisk require action by the firmware. All other activities are part of standard SFF-8067 interface operation. ...
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... The MPIO3_[1:0] pins are used as the external interrupt lines. Refer to these pin descriptions for additional information. The register (0xFE04), allows the LSI53C040 to quickly determine the source of an interrupt. The corresponding interrupts in the ISR to be masked by writing the bit location ...
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Table 2.5 Register Bits for Interrupt Handling Register Bit Register or Bit Location Name 0xFE04 Interrupt Status 0xFE0D Interrupt Mask 0xFE0E Interrupt Destination 0xFC05, bit 7 End of DMA Transfer 0xFC02, bit 4 Enable Parity Interrupt 0xFC02, bit 2 Monitor ...
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Interrupt Mask Register (0xFE0D) Clearing the bits in this register masks the interrupts corresponding to the bits in the 2.10.1.3 Interrupt Destination Register (0xFE0E) This register provides the ability to route an interrupt to either of the two external ...
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... For send operations, the End of DMA bit is set when the DMA finishes its transfer, but the SCSI transfer may still be in progress. If connected as a target, REQ/ and ACK/ should be sampled until both are false. In the LSI53C040 SCSI core, the Last Byte Sent (bit 7 of the Command (TC) byte was transferred. ...
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... RDATA register, which is transferred to the requesting drive. The write interrupt notifies the LSI53C040 that the drive has written a byte of data to the interface. The LSI53C040 microcontroller core should respond by clearing the interrupt and reading the WDATA register. The Port Control/Status (PCST0/PCST1) bits [1:0] indicate whether a read or write interrupt has occurred ...
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... ISR will be set if the interrupting condition occurs. Masking an interrupt prevents it from being seen by the microcontroller core in the LSI53C040. You can allow hardware interrupts either by enabling them in the appropriate register bits masking the interrupts and polling for them. In general recommended to enable as few interrupts as possible and mask/poll for them instead ...
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Interrupt Service Routine When the microcontroller core receives an interrupt, it reads the Status (ISR) Once it determines the source of the interrupt, it reads the appropriate bits for determining the exact cause of the interrupt. This activity is ...
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... CLAMP, HIGH-Z, and IDCODE instructions. The LSI53C040 uses an 8-bit instruction register to support all boundary scan instructions. The data registers included in the device are the Boundary Data register, the IDCODE register, and the Bypass register. ...
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... Chapter 3 Signal Descriptions This chapter presents the LSI53C040 pin configurations and signal definitions using tables and illustrations. are the pin diagrams for all versions of the LSI53C040, Table 3.4 show a alphabetical listing and numerical listing for each version, and Figure 3.3 is the functional signal grouping. The pin defi ...
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... Figure 3.1 LSI53C040, 160-Pin QFP Option 1 VSS_IO A10 4 A11 5 A12 6 A13 7 A14 8 A15 9 PSEN/ 10 ALE 11 VDD_IO 12 AD7 13 AD6 14 AD5 15 AD4 16 AD3 17 AD2 18 AD1 19 AD0 20 VSS_IO 21 SCL0 22 SDA0 23 VDD_IO 24 MPIO0_0 25 MPIO0_1 26 MPIO0_2 27 MPIO0_3 28 MPIO0_4 29 MPIO0_5 30 MPIO0_6 31 MPIO0_7 32 VSS_IO 33 MPLED0_0 34 MPLED0_1 35 MPLED0_2 ...
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... Table 3.1 LSI53C040 160-Pin QFP Pin List (Alphabetically by Signal Name) Signal Pin Signal A10 4 MPIO2_4 A11 5 MPIO2_5 A12 6 MPIO2_6 A13 7 MPIO2_7 A14 8 MPIO3_0 A15 9 MPIO3_1 A8 2 MPIO3_2 A9 3 MPIO3_3 AD0 20 MPLED0_0 AD1 19 MPLED0_1 AD2 18 MPLED0_2 AD3 17 MPLED0_3 AD4 16 MPLED0_4 AD5 15 MPLED0_5 AD6 ...
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... Table 3.2 LSI53C040 160-Pin QFP Pin List (Numerically by Pin Number) Pin Signal Pin 1 VSS_IO A10 44 5 A11 45 6 A12 46 7 A13 47 8 A14 48 9 A15 49 10 PSEN ALE 51 12 VDD_IO 52 13 AD7 53 14 AD6 54 15 AD5 55 16 ...
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... Figure 3.2 LSI53C040 169-Ball BGA Top View RD/ VSS_CORE RESET WR/ VDD_IO A10 NC A8 CLK_SEL A14 A12 A11 VDD_CORE ALE PSEN/ A15 A13 AD5 AD6 AD7 VDD_IO AD1 ...
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Table 3.3 169-Ball BGA List (Alphabetically by Ball Grid Location) Ball # Signal Ball # RD/ C10 A3 VSS_CORE C11 A4 RESET/ C12 A5 SCL1 C13 A6 SD1 SD3 SD4 D3 A9 ...
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Table 3.4 169-Ball BGA List (Alphabetically by Signal Name) Signal Ball # Signal A8 C3 MPIO1_6 A9 E5 MPIO1_7 A10 C1 MPIO2_0 A11 D3 MPIO2_1 A12 D2 MPIO2_2 A13 E4 MPIO2_3 A14 D1 MPIO2_4 A15 E3 MPIO2_5 AD0 G4 MPIO2_6 ...
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... Figure 3.3 LSI53C040 Functional Pin Description SSEL SSEL SBSY SBSY SRST+ SRST SREQ+ SREQ SACK SACK SMSG SMSG SCD LVD/SE SCD SCSI SIO+ Interface SIO SATN+ SATN SDP0 SDP0 SD[7:0] SD[7:0] DIFFSENS SHID[2:0] SHID[2:0] RBIAS RBIAS 3-8 Signal Descriptions MPIO0[7:0] MPIO1[7:0] MPIO2[7:0] MPIO3[3:0] MPLED0[7:0] MPLED1[7:0] ...
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... Low byte of the microcontroller multiplexed address/data bus. An external pull-up on AD[1:0] enables automatic branch generation. For information on the branch values, see Table 2.3. An external pull-up on AD5 causes the LSI53C040 to download firmware from a serial ROM at power on. For more information on these power-up options, see Chapter 2. Signals, SCSI Signals, Signals ...
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Table 3.5 Miscellaneous Signals (Cont.) Pin BGA Ball Name Number Number PSEN WR/ 158 B3 RD/ 160 A2 ALE 11 E1 SCL0 22 G5 SCL1 149 A5 SDA0 23 H2 SDA1 150 B5 MPIO0_ 32, 31, 30, K1, ...
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Table 3.5 Miscellaneous Signals (Cont.) Pin BGA Ball Name Number Number MPIO3_ 87 J10 [3:0] 86 K12 85 K11 84 L13 MPLED 42, 41, 40, J5, L3, 0_ 39, 37, 36, K4, L2, [7:0] 35, 34 K3, L1, J4, K2 ...
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... Active low chip reset input. The LSI53C040 has an internal power-on reset circuit which can be relied upon for initializing the chip. If the LSI53C040 watchdog timer is used and it expires, it can force an internal chip reset and assert the RESET/ pin LOW to reset external devices (if bit 7 in register 0xFF05 is set) ...
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SCSI Signals Table 3.6 Table 3.6 SCSI Signals Pin BGA Ball Name Number Number DIFFSENS 93 H11 SHID2 94 H12 SHID2+ 95 H13 SHID1 96 SHID1+ 97 G11 SHID0 98 G12 SHID0+ 99 G13 Safety Mode Signals describes the ...
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Table 3.6 SCSI Signals (Cont.) Pin BGA Ball Name Number Number SIO 101 G10 SIO+ 102 SREQ 103 F12 SREQ+ 104 F13 SCD 106 F10 SCD+ 107 SSEL 108 E13 SSEL+ 109 E12 SMSG 111 E11 SMSG+ 112 SRST 113 ...
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Table 3.6 SCSI Signals (Cont.) Pin BGA Ball Name Number Number RBIAS 121 C11 RBIAS+ 122 SATN 124 A11 SATN+ 125 C10 SDP0 126 B10 SDP0+ 127 SD7 , 129,130, C9, B9, SD7+, 131,132, A9, D8, SD6 , 134,135, C8, ...
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JTAG Signals Table 3.7 Table 3.7 JTAG Signals Pin BGA Ball Name Number Number TCK 91 TMS 90 TDI 92 TDO 89 TRST/ 151 3-16 Signal Descriptions describes the signals for the JTAG Signals group. Description J13 Test Clock. ...
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Power and Ground Signals Table 3.8 Table 3.8 Power and Grounds Signals Pin BGA Ball Name Number Number VSS_IO 1, 21, 33, F7, G6, 38, 50, 57, G7, G8, 62, 76, 83 VDD_IO 12, 24, 43, B4, F4, 71, ...
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SFF-8067 Mode The SFF-8067 interface is enabled when the DIFFSENS pin is tied The SCSI pin functions are reassigned to SFF-8067 port functions DD as indicated in Table 3.9 Pin Assignments for SFF-8067 Mode Pin/Ball Name ...
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... SEL_5 signal, included for compatibility with SFF-8045. When PARALLEL_ESI/ is asserted, this is an active low control signal sourced by the drive to the LSI53C040 to indicate the device is ready to write data. When PARALLEL_ESI/ is deasserted, this signal is the SEL_6 signal, included for compatibility with SFF-8045. ...
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... SEL_4 signal, included for compatibility with SFF-8045. When PARALLEL_ESI/ is asserted, this is an active low control signal sourced by the drive to the LSI53C040 to indicate the device is ready to read data. When PARALLEL_ESI/ is deasserted, this signal is the SEL_5 signal, included for compatibility with SFF-8045. Pad 8067 Port Confi ...
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... SFF-8067 Mode Description When PARALLEL_ESI/ is asserted, this is an active low control signal sourced by the drive to the LSI53C040 to indicate the device is ready to write data. When PARALLEL_ESI/ is deasserted, this signal is the SEL_6 signal, included for compatibility with SFF-8045. Used to select between the SEL_ID and the bidirectional interface ...
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Table 3.9 Pin Assignments for SFF-8067 Mode (Cont.) Pin/Ball Name No. PA0 112/F8 PA1 111/E11 PA2 109/E12 PA3 108/E13 PA4 107/F9 PA5 106/F10 PA6 104/F13 Tied to V 103/F12 DD Tied to V 102/G9 DD Tied to V 101/G10 DD ...
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... Chapter 4 SCSI and DMA Registers This chapter contains descriptions of the LSI53C040 SCSI and DMA registers. The SFF-8067 registers, Two-Wire Serial registers, Miscellaneous registers, and System registers are described in Chapter 5 through Chapter are programmed to a binary one, while the terms “reset” or “clear” are used to refer to bits that are programmed to binary zero. Any bits marked as reserved should always be written to zero ...
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Table 4.1, the register map, summarizes the SCSI and DMA registers in graphical form. Table 4.1 SCSI and DMA Registers 31 Current SCSI Data (CSD) (Read) Current SCSI Bus Status (CSBS) (Read) Bus and Status (BSR) (Read) Start DMA Target ...
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Register: 0xFC00 Current SCSI Data (CSD) Read Only Current SCSI Data The Current SCSI Data register is a read only register that allows the microcontroller to read the active SCSI data bus. Whenever a 1 ...
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Register: 0xFC01 Initiator Command (ICR) Read/Write 7 ARST 0 ARST AIP LA AACK 4-4 SCSI and DMA Registers AIP LA AACK ABSY Assert SRST Whenever written to this bit, the SRST ...
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... DB0/–DB7/. Parity is also generated and asserted on DBP/. Resetting this bit disables the output data bus. When the LSI53C040 is connected as an Initiator, the outputs are only enabled if the Target Mode bit (Mode register 0xFC02, bit 6) is false, the received SCSI I/O ...
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Register: 0xFC02 Mode (MR) Read/Write 7 AS_LVD 0 AS_LVD TGTM EPC EPI R MB 4-6 SCSI and DMA Registers TGTM EPC EPI Arbitration/Selection LVD This bit must be set to perform arbitration, selection, and ...
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When the interrupt is generated due to loss of BSY/, the lower 6 bits of the (0xFC01) are reset and all signals are removed from the SCSI bus. DM DMA Mode The DMA Mode bit is used to enable a ...
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... C_D/, and MSG/) do not match the phase bits in this register, a phase mismatch interrupt is generated when REQ/ goes active. In order to send data as an initiator, the Assert I_O/, Assert C_D/ and Assert MSG/ bits must match the corresponding bits in the Status (CSBS) meaning when the LSI53C040 is operating as an initiator. LBS R AREQ AMSG ...
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Table 4.2 Bus Phase Data Out Undefined Command Message Out Data In Undefined Status Message In Register: 0xFC04 Current SCSI Bus Status (CSBS) Read Only RST BSY REQ The Current SCSI Bus Status register ...
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SEL DBP Register: 0xFC04 Select Enable (SER) Write Only Register: 0xFC05 Bus and Status (BSR) Read Only 7 EOD 0 The Bus and Status register is a read only register that can be used to monitor the ...
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... The Phase Match bit indicates whether the current SCSI bus phase matches the lower three bits of the Phase Match is continuously updated and is only significant when the LSI53C040 is operating as a bus initiator. A phase match is required for data transfers to occur on the SCSI bus. BERR ...
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Register: 0xFC05 DMA Send (DSR) Write Only This register does not have individual bit definitions. Any write to this register will initiate a DMA send, from the DMA core to the SCSI bus, for either initiator or target role operations. ...
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Register: 0xFC07 Start DMA Initiator Receive (SDIR) Write Only This register does not have individual bit definitions. Any write to this register will initiate a DMA receive from the SCSI bus, for initiator operation only. The DMA Mode bit (register ...
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... DMA Status (DS) Read/Write 7 0 The DMA function in the LSI53C040 provides the capability of transferring up to 256 bytes from memory to the SCSI port or vice versa. The DMA function is designed to handshake automatically with the SCSI core, to offload the microcontroller and increase SCSI throughput. The ...
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R Reserved IEN Interrupt Enable When this bit is set the DMA function will generate an interrupt whenever the TIP bit transitions from This signifies that (1) the transfer completed normally, or ...
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Register: 0xFC12 DMA Source/Destination Low (DSDL) Read/Write 7 0 DSDL Register: 0xFC13 DMA Source/Destination High (DSDH) Read/Write 7 0 DSDH 4-16 SCSI and DMA Registers DSDL DMA Source/Destination Low These register bits store the least significant byte ...
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Register: 0xFC14 DMA Interrupt (DMAI) Read/Write Reserved INT DMA Interrupt This register bit is the interrupt value for the DMA. This interrupt will only be enabled if the IEN bit in the DMA Status register ...
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SCSI and DMA Registers ...
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... Chapter 5 SFF-8067 Registers This chapter contains descriptions of the LSI53C040 SFF-8067 registers. The SCSI/DMA registers, Two-Wire Serial registers, Miscellaneous registers, and System registers are described in Chapter 6 through Chapter are programmed to a binary one, while the terms “reset” or “clear” are used to refer to bits that are programmed to binary zero. Any bits marked as reserved should always be written to zero ...
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The SFF-8067 Interface register set allows observation and control of the two SFF-8067 interface ports which are designated as port 0 and port 1. The registers associated with port 0 occupy addresses 0xFC20 through 0xFC27 and the registers associated with ...
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Register: 0xFC20/0xFC28 Read Data (RDATA0/RDATA1) Read/Write 8067 Read Data The Read Data bits are read/write bits that contain data to be transferred out on the associated 8067 port in response to a read request at ...
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R BSY RRF WRF RINT WINT 5-4 SFF-8067 Registers and the LESI (0xFC24/0xFC2C) register, which is used to read the port pins. Setting this bit disables automatic receive or transmit over the 8067 interface. Reserved (read only) Port Busy Flag ...
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... Reading this active low bit gives the state of the DSK_WR/ signal on the SFF-8067 interface. When this active low bit is cleared, the drive is ready to write data to the LSI53C040. It will be cleared (0) if the PESI/ bit is cleared (0). If PESI this bit reflects the value of the PA6 signal. ...
Page 98
... Reading this active low bit gives the state of the DSK_RD/ signal on the SFF-8067 interface. When this active low bit is cleared, the drive is ready to read data from the LSI53C040. It will be cleared (0) if the PESI/ bit is cleared (0). If PESI this bit reflects the value of the PA5 signal. ...
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... When this active low bit is cleared, the drive is ready to read data from the LSI53C040. ACK/ ENCL_ACK/ Value This active low bit is cleared as an acknowledge signal driven by the LSI53C040 in discovery, read, and write operations. D[3:0] 8067 Interface Data Nibble Bits These bits contain the current data nibble for the D[3:0] signals in read/write operations ...
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SFF-8067 Registers ...
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... Chapter 6 Two-Wire Serial Registers This chapter contains descriptions of the LSI53C040 Two-Wire Serial interface registers. The SCSI/DMA registers, SFF-8067 registers, Miscellaneous registers, and System registers are described in Chapter 5, Chapter 7, and Chapter bits that are programmed to a binary one, while the terms “reset” or “clear” ...
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All registers for the Two-Wire Serial interface 0, other than the Control register, are accessed through Register 0xFD00. All registers for the Two-Wire Serial interface 1, other than the Control register, are accessed through Register 0xFD02. To select one of ...
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Register: 0xFD00/0xFD02 Own Address (ES0, ES1, ES2 = 000) Read/Write Reserved A[6:0] Own Address This register contains the address that is used for slave mode operation. If the first byte of transmission matches ...
Page 104
Examples MHz input clock and a maximum 400 kHz SCL output would require D1* greater than 100. A best fit would be for and The value written ...
Page 105
Each operation will activate the PIN bit located in the Two-Wire Control register [0xFD01/0xFD03 (ES0=1)]. Register: 0xFD01/0xFD03 Control Register Writes Write Only PIN ES0 ES[1: PIN Pending Interrupt Setting this bit ...
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STO ACK Register: 0xFD01/0xFD03 Control Register Reads (ES0 = 0) Read Only 7 PIN 0 PIN ES0 ES[1:2] 6-6 Two-Wire Serial Registers 100] - Data Register) will be sent out on the Two-Wire Serial bus with a start condition as ...
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ENI External Interrupt Enable Setting this bit enables the interrupt output to the microcontroller when the PIN bit (0xFD01/0xFD03, bit 7) is cleared (0). It causes the corresponding bit to be set in the Interrupt Status (ISR) interrupt is not ...
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... This bit is set if the STOP condition is detected when the LSI53C040 is in slave receive mode. Bus Error Detection This bit is set if a bus error is detected by the LSI53C040, (i.e., Misplaced Start or Stop). Setting this bit clears the BB_N bit and resets the PIN bit. ...
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Register: 0xFD04 Miscellaneous Read Only Reserved CKSUM Checksum Error This bit is set if an error was detected when checking the checksum value after download. Register: 0xFD05 UC Control ITF1 Read/Write ...
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Register: 0xFD06 UC Control ITF0 Read/Write SDAI0 SCLI0 SDAO0 SCLO0 CTL0 6-10 Two-Wire Serial Registers SDAI0 SCLI0 Reserved ITF0 SDA Input This bit indicates the current value on the SDA0 pin. ...
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... Chapter 7 Miscellaneous Registers This chapter contains descriptions of the LSI53C040 Miscellaneous registers. The SCSI/DMA registers, SFF-8067 registers, Two-Wire Serial registers, and System registers are described in Chapter 7, and Chapter 8. The term “set” is used to refer to bits that are programmed to a binary one, while the terms “reset” or “clear” are used to refer to bits that are programmed to binary zero. Any bits marked as reserved should always be written to zero ...
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Table 7.2, the register map, summarizes the Miscellaneous registers in graphical form. Table 7.1 Miscellaneous Registers 31 Watchdog Timer Control (WDTC) Watchdog Secondary Chain (WDSC) Watchdog Final Chain (WDFC) Timer 1 Secondary Chain (T1SC) Timer 2 Secondary Chain (T2SC) 7-2 ...
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... Enable Reset Output bit is set (0xFF05, bit 7). If the watchdog timer is used, the LSI53C040 firmware needs to periodically clear the watchdog timer. The watchdog timer reinitializes the LSI53C040 if the firmware does not clear the timer before time-out. The watchdog timer is cleared with any write to the (WDTC) register ...
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Table 7.3 WTHR3 OUT 7-4 Miscellaneous Registers Possible Watchdog Timer Values (40 MHz Internal Clock) WTHR2 WTHR1 ...
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Register: 0xFE01 Watchdog Secondary Chain (WDSC) Read Only The values in this register are not affected by a soft reset. R Reserved WDSC[6:0] Watchdog Secondary Chain These register bits provide the ability to read ...
Page 116
... A value this bit powers down the input LVD transceivers for operation when not in LVD mode. SCSI Isolation When set, this bit 3-states and logically disconnects the LSI53C040 SCSI port from the SCSI bus when in SE mode (DIFFSENS = V ® TolerANT Enable This bit is used in LVD mode only ...
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Register: 0xFE04 Interrupt Status (ISR) Read/Write SCSI_INT TW1_INT TW0_INT DMA_INT TMR2_INT TMR1_INT EXS1_INT EXS0_INT The individual bits of this register may be written to force an interrupt on the corresponding bit. Clearing these bits ...
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... Read/Write 7 T1EXP 0 The LSI53C040 includes two built-in timers that run independently of the microcontroller core. Each timer can be programmed to generate one of the two possible interrupts to the microcontroller core, as long as these interrupts are not masked in the operation will also be suspended if either timer expires and generates an interrupt to the microcontroller ...
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T1CLR Timer 1 Clear A value the T1CLR bit clears the timer. A value of 0 allows the timer to advance beyond the clear state. T1PS Timer 1 Prescaler A value the T1PS bit ...
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Register: 0xFE07 Timer 1 Secondary Chain (T1SC) Read Only T1SC[6:0] Register: 0xFE08 Timer 1 Final Chain (T1FC) Read Only 7 0 T1FC 7-10 Miscellaneous Registers 6 T1SC[6: Reserved Timer 1 Secondary Chain ...
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Register: 0xFE09 Timer 2 Control (T2C) Read/Write T2EXP T2RUN T2CLR T2EXP Timer 2 Expired (read only) A value the T2EXP bit indicates that the timer has expired and an interrupt has ...
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Register: 0xFE0A Timer 2 Threshold (T2T) Read/Write 7 0 T2TH Register: 0xFE0B Timer 2 Secondary Chain (T2SC) Read Only T2SC[6:0] 7-12 Miscellaneous Registers T2TH Timer 2 Threshold These register bits select the time-out ...
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Register: 0xFE0C Timer 2 Final Chain (T2FC) Read Only T2FC Timer 2 Final Chain These register bits provide the ability to read the final timer 2 divider chain. The expiration condition for this timer is when ...
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IMR4 IMR3 IMR2 IMR1 IMR0 7-14 Miscellaneous Registers DMA Interrupt Clearing this bit masks this interrupt. Setting this bit enables the interrupt. Timer 2 Interrupt Clearing this bit masks this interrupt. Setting this bit enables the interrupt. Timer 1 Interrupt ...
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Register: 0xFE0E Interrupt Destination (IDR) Read/Write IDR7 IDR6 IDR5 These register bits provide the ability to route the corresponding interrupts of the Interrupt Status (ISR) two external interrupt inputs of the microcontroller core. A ...
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Miscellaneous Registers ...
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... Chapter 8 System Registers This chapter contains descriptions of the LSI53C040 System registers. The SCSI/DMA registers, SFF-8067 registers, Two-Wire Serial registers, and Miscellaneous registers are described in Chapter 7. The term set is used to refer to bits that are programmed to a binary one, while the term reset or clear is used to refer to bits that are programmed to binary zero. Any bits marked as reserved should always be written to zero ...
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Table 8.1, the register map, summarizes the System registers in graphical form. Table 8.1 System Registers 31 Power-On Configuration Zero (POC0) Power-On Configuration One (POC1) Multipurpose I/O Bank 0 Output (MPO0) Multipurpose I/O Bank 0 Enable (MPE0) Multipurpose I/O Bank ...
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Table 8.1 System Registers (Cont.) Multipurpose I/O Bank 3 Latch Mask (MPLM3) Multipurpose I/O Bank 3 Latch (MPL3) Multipurpose I/O Bank 3 Pull-down Enable (MPPE3) Multipurpose LED Bank 0L Output (MLO0L) Multipurpose LED Bank 0H Output (MLO0H) Multipurpose LED Bank ...
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... The reset value of this bit matches the TTL voltage level on the AD6 pin at reset. Download Serial ROM When this bit is set, the LSI53C040 attempts to download from a serial ROM at power-on or after reset. When cleared, the LSI53C040 will skip the serial ROM download. The reset value of this bit matches the TTL voltage level on the AD5 pin at reset. The AD5 pin has an internal pull-down resistor ...
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... LSI53C040 address decode logic will automatically provide the first branch instruction to the microcontroller whenever it fetches from address 0x0000 through 0x0002. The values in bits 0 and 1 define the destination address for this branch instruction, according to Table 8.2. For more information on automatic branch addressing, see Table 8 ...
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POC1_4 DLSEL DLADR[2:0] Register: 0xFF04 LED Blink Rate (LBR) Read/Write 7 0 Each of the LED output pins, controlled by the LED registers defined later in this register block, can be programmed to be constantly on, constantly off ...
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R Reserved FBR[1:0] Fast Blink Rate These bits define the fast blink rate for the LED output pins, as shown in Table 8.3 FBR1 FBR0 Reserved SBR[1:0] Slow Blink Rate These ...
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R LVD SPEN EIEN Register: 0xFF08 Multipurpose I/O Bank 0 Output (MPO0) Read/Write 7 0 MPO0_ 8-8 System Registers Reserved SCSI LVD Mode (read only) This read only bit is set when the SCSI interface is in LVD mode. Serial ...
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Register: 0xFF09 Multipurpose I/O Bank 0 Enable (MPE0) Read/Write MPE0_ Multipurpose I/O Bank 0 Enable These bits control the output enables on the I/O pins MPIO0_0, MPIO0_1, MPIO0_2, MPIO0_3, MPIO0_4, MPIO0_5, MPIO0_6, and MPIO0_7. A value ...
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Register: 0xFF0B Multipurpose I/O Bank 0 Latch Mask (MPLM0) Read/Write 7 1 MPLM0_ Register: 0xFF0C Multipurpose I/O Bank 0 Latch (MPL0) Read/Write 7 x MPL0_ 8-10 System Registers MPLM0_ Multipurpose I/O Bank 0 Latch Mask These read/write ...
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Register: 0xFF0D Multipurpose I/O Bank 0 Pull-down Enable (MPPE0) Read/Write MPPE0_ Multipurpose I/O Bank 0 Pull-down Enable These read/write register bits determine if pull-downs are active on the I/O pins MPIO0_0, MPIO0_1, MPIO0_2, MPIO0_3, MPIO0_4, MPIO0_5, ...
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Register: 0xFF11 Multipurpose I/O Bank 1 Enable (MPE1) Read/Write 7 0 MPE1_ Register: 0xFF12 Multipurpose I/O Bank 1 Input (MPI1) Read Only 7 0 MPI1_ 8-12 System Registers MPE1_ Multipurpose I/O Bank 1 Enable These bits ...
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Register: 0xFF13 Multipurpose I/O Bank 1 Latch Mask (MPLM1) Read/Write MPLM1_ Multipurpose I/O Bank 1 Latch Mask These read/write register bits define the write mask for the Multipurpose I/O Bank 1 Latch (MPL1) (0xFF14). A value ...
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Register: 0xFF15 Multipurpose I/O Bank 1 Pull-down Enable (MPPE1) Read/Write 7 1 MPPE1_ Register: 0xFF18 Multipurpose I/O Bank 2 Output (MPO2) Read/Write 7 0 MPO2_ 8-14 System Registers MPPE1_ Multipurpose I/O Bank 1 Pull-down Enable These read/write ...
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Register: 0xFF19 Multipurpose I/O Bank 2 Enable (MPE2) Read/Write MPE2_ Multipurpose I/O Bank 2 Enable These bits control the output enables on the I/O pins MPIO2_0, MPIO2_1, MPIO2_2, MPIO2_3, MPIO2_4, MPIO2_5, MPIO2_6, and MPIO2_7. A value ...
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Register: 0xFF1B Multipurpose I/O Bank 2 Latch Mask (MPLM2) Read/Write 7 1 MPLM2_ Register: 0xFF1C Multipurpose I/O Bank 2 Latch (MPL2) Read/Write 7 x MPL2_ 8-16 System Registers MPLM2_ Multipurpose I/O Bank 2 Latch Mask These read/write ...
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Register: 0xFF1D Multipurpose I/O Bank 2 Pull-down Enable (MPPE2) Read/Write MPPE2_ Multipurpose I/O Bank 2 Pull-down Enable These read/write register bits determine if pull-downs are active on the I/O pins MPIO2_0, MPIO2_1, MPIO2_2, MPIO2_3, MPIO2_4, MPIO2_5, ...
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Register: 0xFF21 Multipurpose I/O Bank 3 Enable (MPE3) Read/Write MPE3_[3:0] 8-18 System Registers Reserved Multipurpose I/O Bank 3 Enable These bits control the output enables on the I/O pins MPIO3_0, MPIO3_1, MPIO3_2, ...
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Register: 0xFF22 Multipurpose I/O Bank 3 Input (MPI3) Read Only Reserved MPI3_[3:0] Multipurpose I/O Bank 3 Input These read only bits read the live input values on the I/O pins MPIO3_0, MPIO3_1, MPIO3_2, and ...
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Register: 0xFF24 Multipurpose I/O Bank 3 Latch (MPL3) Read/Write MPL3_[3:0] Register: 0xFF25 Multipurpose I/O Bank 3 Pull-down Enable (MPPE3) Read/Write MPPE3_[3:0] Multipurpose I/O Bank 3 Pull-down Enable 8-20 System Registers ...
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Register: 0xFF30 Multipurpose LED Bank 0L Output (MLO0L) Read/Write MLO0_3A MLO0_3B MLO0_2A MLO0_2B MLO0_1A MLO0_1B MLO0_0A MLO0_0B MLO0_[3A:0A], [3B:0B] Multipurpose LED Bank 0L Output The bits in this register control the Multipurpose LED Bank ...
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Register: 0xFF31 Multipurpose LED Bank 0H Output (MLO0H) Read/Write 7 MLO0_7A MLO0_7B MLO0_6A MLO0_6B MLO0_5A MLO0_5B MLO0_4A MLO0_4B 0 MLO0_[7A:4A], [7B:4B] Register: 0xFF32 Multipurpose LED Bank 0L Input (MLI0L) Read Only MLL0_[3:0] 8-22 System Registers 6 ...
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Register: 0xFF33 Multipurpose LED Bank 0H Input (MLI0H) Read Only MLL0_7 Reserved MLL0_[7:4] Multipurpose LED Bank 0H Input The bits in this read only register read the live input value on ...
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Register: 0xFF35 Multipurpose LED Bank 0H Latch Mask (MLLM0H) Read/Write MLLM0_[7:4] Multipurpose LED Bank 0H Latch Mask Register: 0xFF36 Multipurpose LED Bank 0L Latch (MLL0L) Read/Write MLL0_[3:0] 8-24 System Registers 6 5 ...
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Register: 0xFF37 Multipurpose LED Bank 0H Latch (MLL0H) Read/Write MLL0_7 Reserved MLL0_[7:4] Multipurpose LED Bank 0H Latch The bits in this read/write register store the power-on value of the I/O pins ...
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Register: 0xFF39 Multipurpose LED Bank 1H Output (MLO1H) Read/Write 7 MLO1_7A MLO1_7B MLO1_6A MLO1_6B MLO1_5A MLO1_5B MLO1_4A MLO1_4B 0 MLO1_[7A:4A], [7B:4B] 8-26 System Registers The slow blink and fast blink rates are defined in the Blink Rate (LBR) register (0xFF04). ...
Page 153
Register: 0xFF3A Multipurpose LED Bank 1L Input (MLI1L) Read Only MLI1_3 Reserved MLI1_[3:0] Multipurpose LED Bank 1L Input The bits in this read only register read the live input value on ...
Page 154
Register: 0xFF3C Multipurpose LED Bank 1L Latch Mask (MLLM1L) Read/Write MLLM1_[3:0] Multipurpose LED Bank 1L Latch Mask Register: 0xFF3D Multipurpose LED Bank 1H Latch Mask (MLLM1H) Read/Write MLLM1_[7:4] Multipurpose LED Bank 1H ...
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Register: 0xFF3E Multipurpose LED Bank 1L Latch (MLL1L) Read/Write MLL1_3 Reserved MLL1_[3:0] Multipurpose LED Bank 1L Latch Mask The bits in these read/write registers store the power-on value of the I/O ...
Page 156
Register: 0xFF40 Multipurpose LED Bank 2L Output (MLO2L) Read/Write 7 MLO2_3A MLO2_3B MLO2_2A MLO2_2B MLO2_1A MLO2_1B ML02_0A MLO2_0B 0 MLO2_[3A:0A], [3B:0B] 8-30 System Registers Default Multipurpose LED Bank 2L Output These bits ...
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Register: 0xFF41 Multipurpose LED Bank 2H Output (MLO2H) Read/Write ML02_7A MLO2_7B MLO2_6A MLO2_6B MLO2_5A MLO2_5B ML02_4A MLO2_4B MLO2_[7A:4A], [7B:4B] Multipurpose LED Bank 2H Output These bits control the Multipurpose LED Bank 2 pins MPLED2_4, ...
Page 158
Register: 0xFF43 Multipurpose LED Bank 2H Input (MLI2H) Read Only MLI2_[7:4] Register: 0xFF44 Multipurpose LED Bank 2L Latch Mask (MLLM2L) Read/Write MLLM2_[3:0] Multipurpose LED Bank 2L Latch Mask 8-32 System Registers 6 ...
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Register: 0xFF45 Multipurpose LED Bank 2H Latch Mask (MLLM2H) Read/Write MLLM2_7 Reserved MLLM2_[7:4] Multipurpose LED Bank 2H Latch Mask The bits in this read/write register define the write mask for the ...
Page 160
Register: 0xFF47 Multipurpose LED Bank 2H Latch (MLL2H) Read/Write MLL2_[7:4] 8-34 System Registers MLL2_7 R MLL2_6 Defaults Reserved Multipurpose LED Bank 2H Latch These read/write register bits store the power-on ...
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... Electrical Characteristics This chapter presents the DC characteristics and AC specifications for the LSI53C040, using tables and timing diagrams. Timings for Two-Wire Serial and SFF-8067 operation are compliant with current published standards, and are only discussed briefly in this technical manual. Please refer to the appropriate standards documentation for the latest information ...
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Operating Requirements Table 9.1 Absolute Maximum Stress Ratings 1 Symbol Parameter T Storage temperature stg V Supply voltage dd V Input voltage in V Input voltage (5 V tolerant pins) in5V 2 I Latch-up current lp 3 ESD Electrostatic ...
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Volt DC Specifications Table 9.3 LVD Driver SCSI Signals—SD[7:0]+ SD[7:0] , SDP0+, SDP0 , SREQ+, SREQ , SACK/+, SACK/ , SHID[2:0]+, SHID[2:0] , SMSG/+, SMSG/ , SIO/+, SIO/ , SCD/+, SCD/ , SATN/+, SATN/ , SBSY/+, SBSY/ , ...
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Table 9.4 LVD Receiver SCSI Signals—SD[7:0]+, SD[7:0] , SDP0+, SDP0 , SREQ/+, SREQ/ , SACK/+, SACK/ , SMSG/+, SMSG/ , SIO/+, SIO/ , SCD/+, SCD/ , SATN/+, SATN/ , SBSY/+, SBSY/ , SSEL/+, SSEL/ , SRST/+, SRST/ , SHID[2:0]+, SHID[2:0] ...
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Table 9.6 SCSI Signals—DIFFSENS Symbol Parameter V High differential sense voltage ih (indicates SFF-8067 mode) V Low differential sense voltage il (indicates SE SCSI operation) V Mid-level differential sense voltage im (indicates LVD mode) I Input leakage in Table 9.7 ...
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Table 9.9 Bidirectional Signals—RESET/, TESTOUT, CL0, SDA0, SCL1, SDA1 Symbol Parameter V Input high voltage ih V Input low voltage il V Output high voltage oh V Output low voltage ol I 3-state leakage oz Table 9.10 Bidirectional Signals—MPIO0[7:0], MPIO1[7:0], ...
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... TolerANT Technology Electrical Characteristics The LSI53C040 features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Active negation actively drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather than allowing them to be passively pulled up by terminators. ...
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Table 9.12 TolerANT Technology Electrical Characteristics for SE SCSI Signals Symbol Parameter C Capacitance per pin Rise time, 10 Fall time, 90 /dt Slew rate, low to high H ...
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Figure 9.3 Figure 9.4 SCSI Input Filtering REQ/ or ACK/ Input Note the input filtering period. 1 Figure 9 TolerANT Technology Electrical Characteristics Rise and Fall Time Test Condition 2 ...
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Figure 9.6 +40 + Figure 9.7 Output Current as a Function of Output Voltage 0 200 400 600 800 Output Voltage (Volts) 9-10 Electrical Characteristics Input Current as a Function of Input Voltage ...
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... CLK/SCLK Table 9.13 LSI53C040 Clock Timings Symbol Parameter t CLK clock period 1 t CLK low time 2 t CLK high time 3 t CLK slew rate 4 1. Duty cycle not to exceed 60/40. AC Characteristics LSI53C040 Clock Waveforms Min Max Units DC ns – ...
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Reset Signal Figure 9.9 CLK RESET/ Table 9.14 Reset Timings Symbol t Reset Input Pulse Width 1 t Reset Output Pulse Width 1 t Reset deasserted setup to CLK high 2 9-12 Electrical Characteristics Reset Waveforms ...
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... Microcontroller Interface Timings This section provides timing information for the microcontroller interface. The AC characteristics described in this section apply over the entire range of operating conditions for the LSI53C040. 9.5.1 External Memory Interface Figure 9.10 External Memory Interface Waveforms t 1 ALE t PSEN/ ADDR ADDR ...
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External Data Read Cycle Figure 9.11 External Data Read Waveforms ALE PSEN/ RD/ AD[7:0] ADDR A[7:0] ADDR t 7 A[15:8] ADDR t 6 Table 9.16 External Data Read Timings Symbol Parameter t ALE to RD/ = Minimum delay from ...
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External Data Write Cycle Figure 9.12 External Data Write Waveforms ALE PSEN WR/ AD[7:0] ADDR A[7:0] ADDR t 7 A[15:8] ADDR t 6 Table 9.17 External Data Write Timings Symbol Parameter t ALE to WR/ = Minimum ...
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Multipurpose Register Access The timings in and MPLED pins. Please refer to specifying the operation of these pins. Table 9.18 Parameter Shared input setup Shared input hold CLK to output valid 9-16 Electrical Characteristics Table 9.18 apply to register ...
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... Two-Wire Serial Timings The LSI53C040 Two-Wire Serial interface timings comply with the Inter-Integrated Circuit specification. Please refer to the specification for more information. Figure 9.13 Two-Wire Serial Bus Timings SCL SDA t 1 Address, Data Start or Acknowledge Condition Table 9.19 Two-Wire Serial Interface Timings, Normal Mode (100 KHz Clock) ...
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... SCL low period 4 t SCL high period 5 9.8 SFF-8067 Interface Timings Figure 9.14 SFF-8067 Discovery Phase Waveforms PESI/ Driven By Drive DSK_RD/ Driven By Drive DSK_WR/ Driven By Drive ENCL_ACL Driven By LSI53C040 D[3:0] SEL[3:0] Driven By LSI53C040 9-18 Electrical Characteristics Min 0.6 0 100 1.3 0 SEL[3:0 Max Units – s 0.9 s – ...
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... Driven By Drive DSK_WR/ Driven By Drive ENCL_ACK Driven By LSI53C040 D[3:0] High Nibble Driven By Drive t 3 Figure 9.16 SFF-8067 Read Waveforms PESI/ Driven By Drive DSK_RD/ Driven By Drive DSK_WR/ Driven By Drive ENCL_ACL Driven By LSI53C040 D[3:0] Driven By LSI53C040 SFF-8067 Interface Timings High Nibble t 4 Low Nibble Low Nibble 9-19 ...
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Table 9.21 SFF-8067 Interface Timings Parameter Description t PESI/ LOW to ENCL_ACK/ LOW 1 t Data hold from PESI/ LOW 2 t Data setup to DSK_WR/ LOW 3 t Data setup to ENCL_ACK/ LOW 4 9.9 SCSI Timings 9.9.1 Initiator ...
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Initiator Asynchronous Receive Figure 9.18 Initiator Asynchronous Receive Waveforms SREQ/ SACK SD[15:0], SDP1/, SDP0/ Table 9.23 Initiator Asynchronous Receive Timings Symbol Description t 1 ACK asserted from REQ deasserted t 2 ACK deasserted from REQ deasserted t ...
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Target Asynchronous Send Figure 9.19 Target Asynchronous Send Waveforms SREQ/ SACK SD[15:0], SDP1/, SDP0/ Table 9.24 Target Asynchronous Send Timings Symbol Description t 1 REQ deasserted from REACKQ asserted t 2 REQ asserted from ACK deasserted t ...
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Target Asynchronous Receive Figure 9.20 Target Asynchronous Receive Waveforms SREQ/ SACK SD[15:0], SDP1/, SDP0/ Table 9.25 Target Asynchronous Receive Timings Symbol Description t REQ deasserted from ACK asserted 1 t REQ asserted from ACK deasserted 2 t ...
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... IPC-SM-782, Surface Mount Design and Land Pattern Standard is an established method of designing land patterns. Feature size and tolerances are industry standards based on IPC assumptions. All package dimensions are in millimeters. are the mechanical drawings of the two package options for the LSI53C040. 9-24 Electrical Characteristics Figure 9.21 and ...
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Figure 9.21 160-Lead PQFP (P3) Mechanical Drawing (Sheet Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the ...
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Figure 9.21 160-Lead PQFP (P3) Mechanical Drawing (Sheet Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the ...
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Figure 9.22 169-Pin PBGA (GV) Mechanical Drawing Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package ...
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Electrical Characteristics ...
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... DMA Source/Destination Low (DSDL) DMA Status (DS) DMA Transfer Length (DTL) Initiator Command (ICR) Interrupt Destination (IDR) Interrupt Mask (IMR) Interrupt Status (ISR) LED Blink Rate (LBR) LSI53C040 Enclosure Services Processor Technical Manual Address R/W 0xFC05 Read Only 0xFD00/0xFD02 Read/Write 6-3 0xFD01/0xFD03 Read Only ...
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Table A.1 Register Summary by Description (Cont.) Description Live ESI (LESI0/LESI1) Manual Data Output (MDATA0/MDATA1) Miscellaneous Miscellaneous Control (MCR) Mode (MR) Multipurpose I/O Bank 0 Enable (MPE0) Multipurpose I/O Bank 0 Input (MPI0) Multipurpose I/O Bank 0 Latch (MPL0) Multipurpose ...
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Table A.1 Register Summary by Description (Cont.) Description Multipurpose I/O Bank 3 Latch (MPL3) Multipurpose I/O Bank 3 Latch Mask (MPLM3) Multipurpose I/O Bank 3 Output (MPO3) Multipurpose I/O Bank 3 Pull-down Enable (MPPE3) 0xFF25 Multipurpose LED Bank 0H Input ...
Page 192
Table A.1 Register Summary by Description (Cont.) Description Multipurpose LED Bank 2L Latch (MLL2L) Multipurpose LED Bank 2L Latch Mask (MLLM2L) Multipurpose LED Bank 2L Output (MLO2L) Output Data (ODR) Own Address (ES0, ES1, ES2 = 000) Physical Address (PHAD0/PHAD1) ...
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Table A.1 Register Summary by Description (Cont.) Description Timer 2 Threshold (T2T) UC Control ITF0 UC Control ITF1 Watchdog Final Chain (WDFC) Watchdog Secondary Chain (WDSC) Watchdog Timer Control (WDTC) Write Data (WDATA0/WDATA1) Table A.2 Register Summary by Address Address ...
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Table A.2 Register Summary by Address (Cont.) Address Description 0xFC11 DMA Transfer Length (DTL) 0xFC12 DMA Source/Destination Low (DSDL) 0xFC13 DMA Source/Destination High (DSDH) 0xFC14 DMA Interrupt (DMAI) 0xFC20/0xFC28 Read Data (RDATA0/RDATA1) 0xFC21/0xFC29 Write Data (WDATA0/WDATA1) 0xFC22/0xFC2A Port Control/Status (PCST0/PCST1) ...
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Table A.2 Register Summary by Address (Cont.) Address Description 0xFE06 Timer 1 Threshold (T1TH) 0xFE07 Timer 1 Secondary Chain (T1SC) 0xFE08 Timer 1 Final Chain (T1FC) 0xFE09 Timer 2 Control (T2C) 0xFE0A Timer 2 Threshold (T2T) 0xFE0B Timer 2 Secondary ...
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Table A.2 Register Summary by Address (Cont.) Address Description 0xFF18 Multipurpose I/O Bank 2 Output (MPO2) 0xFF19 Multipurpose I/O Bank 2 Enable (MPE2) 0xFF1A Multipurpose I/O Bank 2 Input (MPI2) 0xFF1B Multipurpose I/O Bank 2 Latch Mask (MPLM2) 0xFF1C Multipurpose ...
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Table A.2 Register Summary by Address (Cont.) Address Description 0xFF3D Multipurpose LED Bank 1H Latch Mask (MLLM1H) 0xFF3E Multipurpose LED Bank 1L Latch (MLL1L) 0xFF3F Multipurpose LED Bank 1H Latch (MLL1H) 0xFF40 Multipurpose LED Bank 2L Output (MLO2L) 0xFF41 Multipurpose ...
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A-10 Register Summary ...
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... LVD bit 4-6 AREQ bit 4-8 ARST bit 4-4 AS_LVD bit 4-6 ASEL bit 4-5 ASF bit 6-3 LSI53C040 Enclosure Services Processor Technical Manual assert ACK/ bit 2-9, 4-4 assert ATN/ bit 4-5 assert BSY/ bit 4-5 assert C_D/ bit 2-9, 4-8 assert data bus bit 4-5 assert I_O/ bit 4-8 7-15 ...
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D D[3:0] bits 5-6, 5-7 D[7:0] 6-4 data bits 6-4 data bus parity bit 4-10 data memory 2-3 data register 6-4 data transfer length bits 4-15 DB[7:0] bits 4-3, 5-3 DBP bit 4-10 DC specifications 9-3 DIFFSENS 2-8, 2-24 DLADR[2:0] ...