MT4LC4M4E8DJ-5

Manufacturer Part NumberMT4LC4M4E8DJ-5
Description4Meg x 4 banks, EDO DRAM, 3.3V, standard refresh, 50ns
ManufacturerMicron Semiconductor Products
MT4LC4M4E8DJ-5 datasheet
 
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TECHNOLOGY, INC.
DRAM
FEATURES
• Industry-standard x4 pinout, timing, functions and
packages
• State-of-the-art, high-performance, low-power CMOS
silicon-gate process
• Single power supply (+3.3V 0.3V or +5V 10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-
BEFORE-RAS# (CBR)
• Optional Self Refresh (S) for low-power data retention
• 11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
• Extended Data-Out (EDO) PAGE MODE access cycle
• 5V-tolerant inputs and I/Os on 3.3V devices
OPTIONS
• Voltages
3.3V
5V
• Refresh Addressing
2,048 (i.e. 2K) Rows
4,096 (i.e. 4K) Rows
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
• Part Number Example: MT4LC4M4E8DJ-6
Note: The 4 Meg x 4 EDO DRAM base number differentiates the offerings in
two places - MT4LC4M4E8. The third field distinguishes the low voltage
offering: LC designates V
= 3.3V and C designates V
CC
distinguishes various options: E8 designates a 2K refresh and E9 designates a
4K refresh for EDO DRAMs.
KEY TIMING PARAMETERS
t
t
t
SPEED
RC
RAC
PC
-5
84ns
50ns
20ns
-6
104ns
60ns
25ns
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
MT4LC4M4E8, MT4C4M4E8
MT4LC4M4E9, MT4C4M4E9
V
DQ1
DQ2
WE#
RAS#
*NC/A11
A10
V
MARKING
* NC on 2K refresh and A11 on 4K refresh options.
Note: The “#” symbol indicates signal is active LOW.
LC
C
4 MEG x 4 EDO DRAM PART NUMBERS
E8
PART NUMBER
E9
MT4LC4M4E8DJ
MT4LC4M4E8DJS
DJ
MT4LC4M4E8TG
TG
MT4LC4M4E8TGS
MT4LC4M4E9DJ
-5
MT4LC4M4E9DJS
-6
MT4LC4M4E9TG
MT4LC4M4E9TGS
None
MT4C4M4E8DJ
S
MT4C4M4E8DJS
MT4C4M4E8TG
MT4C4M4E8TGS
MT4C4M4E9DJ
= 5V. The fifth field
CC
MT4C4M4E9DJS
MT4C4M4E9TG
MT4C4M4E9TGS
GENERAL DESCRIPTION
t
t
t
AA
CAC
CAS
The 4 Meg x 4 DRAM is a randomly accessed, solid-state
25ns
13ns
8ns
memory containing 16,777,216 bits organized in a x4 con-
30ns
15ns
10ns
figuration. RAS# is used to latch the row address (first 11
bits for 2K and first 12 bits for 4K). Once the page has been
opened by RAS#, CAS# is used to latch the column address
1
PIN ASSIGNMENT (Top View)
24/26-Pin SOJ
24/26-Pin TSOP
(DA-2)
V
1
1
26
V
CC
CC
SS
DQ1
2
2
25
DQ4
DQ2
3
3
24
DQ3
WE#
4
4
23
CAS#
RAS#
5
5
22
OE#
*NC/A11
6
6
21
A9
A10
8
8
19
A8
A0
9
A0
9
18
A7
A1
10
A1
10
17
A6
A2
11
A3
12
A2
11
16
A5
V
13
A3
12
15
A4
CC
13
14
V
CC
SS
Vcc
REFRESH
PACKAGE
3.3V
2K
3.3V
2K
3.3V
2K
3.3V
2K
3.3V
4K
3.3V
4K
3.3V
4K
3.3V
4K
5V
2K
5V
2K
5V
2K
5V
2K
5V
4K
5V
4K
5V
4K
5V
4K
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4 MEG x 4
EDO DRAM
(DB-2)
26
V
SS
25
DQ4
24
DQ3
23
CAS#
22
OE#
21
A9
19
A8
18
A7
17
A6
16
A5
15
A4
14
V
SS
REFRESH
SOJ
Standard
SOJ
Self
TSOP
Standard
TSOP
Self
SOJ
Standard
SOJ
Self
TSOP
Standard
TSOP
Self
SOJ
Standard
SOJ
Self
TSOP
Standard
TSOP
Self
SOJ
Standard
SOJ
Self
TSOP
Standard
TSOP
Self
1997, Micron Technology, Inc.

MT4LC4M4E8DJ-5 Summary of contents