MT4C1M16E5DJ-6 Micron Semiconductor Products, MT4C1M16E5DJ-6 Datasheet

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MT4C1M16E5DJ-6

Manufacturer Part Number
MT4C1M16E5DJ-6
Description
1Meg x 16, 3.3V EDO DRAM
Manufacturer
Micron Semiconductor Products
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT4C1M16E5DJ-6
Manufacturer:
MIC
Quantity:
700
Part Number:
MT4C1M16E5DJ-6
Manufacturer:
MIC
Quantity:
700
EDO DRAM
FEATURES
• JEDEC- and industry-standard x16 timing,
• High-performance CMOS silicon-gate process
• Single power supply (+3.3V ±0.3V or 5V ±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
• BYTE WRITE access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• Extended Data-Out (EDO) PAGE MODE access
• 5V-tolerant inputs and I/Os on 3.3V devices
OPTIONS
• Voltages
• Refresh Addressing
• Packages
• Timing
• Refresh Rates
• Operating Temperature Range
NOTE: 1. The third field distinguishes the low voltage offering: LC desig-
KEY TIMING PARAMETERS
1 Meg x 16 EDO DRAM
D52_B.p65 – Rev. B; Pub. 3/01
SPEED
functions, pinouts, and packages
(CBR), HIDDEN; optional self refresh (S)
3.3V
5V
1,024 (1K) rows
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
50ns access
60ns access
Standard Refresh (16ms period)
Self Refresh (128ms period)
Commercial (0
Extended (-20
-5
-6
2. Available only on MT4LC1M16E5 (3.3V)
nates Vcc = 3.3V and C designates Vcc = 5V.
104ns
84ns
t
RC
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
MT4LC1M16E5TG-6
o
o
t
C to +80
50ns
60ns
RAC
C to +70
Part Number Example:
20ns
25ns
t
o
PC
o
C)
C)
25ns
30ns
t
AA
t
15ns
17ns
MARKING
CAC
None
None
TG
LC
ET
E5
DJ
S
-5
-6
C
2
t
10ns
CAS
8ns
1
MT4C1M16E5 – 1 Meg x 16, 5V
MT4LC1M16E5 – 1 Meg x 16, 3.3V
For the latest data sheet, please refer to the Micron Web
site:
1 MEG x 16 EDO DRAM PART NUMBERS
NOTE: “-x” indicates speed grade marking under timing
GENERAL DESCRIPTION
memory containing 16,777,216 bits organized in a x16
configuration. The 1 Meg x 16 has both BYTE WRITE
and WORD WRITE access cycles via two CAS# pins
(CASL# and CASH#). These function like a single CAS#
found on other DRAMs in that either CASL# or CASH#
will generate an internal CAS#.
the first CAS# (CASL# or CASH#) to transition LOW and
the last CAS# to transition back HIGH. Using only one
RAS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
WE#
V
V
V
NOTE: The "#" symbol indicates signal is active LOW.
PART NUMBER
MT4LC1M16E5DJ-x
MT4LC1M16E5DJ-x S
MT4LC1M16E5TG-x
MT4LC1M16E5TG-x S
MT4C1M16E5DJ-x
MT4C1M16E5TG-x
NC
NC
NC
NC
NC
A0
A1
A2
A3
CC
CC
CC
The 1 Meg x 16 is a randomly accessed, solid-state
The CAS# function and timing are determined by
44/50-Pin TSOP
www.micron.com/products/datasheets/sdramds.html
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
options.
PIN ASSIGNMENT (Top View)
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
3.3V
3.3V
3.3V
3.3V
Vcc REFRESH PACKAGE REFRESH
5V
5V
V
DQ15
DQ14
DQ13
DQ12
V
DQ11
DQ10
DQ9
DQ8
NC
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
V
16Mb: 1 MEG x16
SS
SS
SS
RAS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
WE#
1K
1K
1K
1K
1K
1K
V
V
V
NC
NC
NC
NC
A0
A1
A2
A3
CC
CC
CC
42-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
EDO DRAM
400-TSOP Standard
400-TSOP
400-TSOP Standard
400-SOJ
400-SOJ
400-SOJ
©2001, Micron Technology, Inc
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Standard
Standard
V
DQ15
DQ14
DQ13
DQ12
V
DQ11
DQ10
DQ9
DQ8
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
V
Self
Self
SS
SS
SS

Related parts for MT4C1M16E5DJ-6

MT4C1M16E5DJ-6 Summary of contents

Page 1

... MEG x 16 EDO DRAM PART NUMBERS TG PART NUMBER -5 MT4LC1M16E5DJ-x -6 MT4LC1M16E5DJ-x S MT4LC1M16E5TG-x MT4LC1M16E5TG-x S None MT4C1M16E5DJ MT4C1M16E5TG-x None NOTE: “-x” indicates speed grade marking under timing ET options. GENERAL DESCRIPTION The 1 Meg randomly accessed, solid-state memory containing 16,777,216 bits organized in a x16 configuration ...

Page 2

GENERAL DESCRIPTION (continued) of the two signals results in a BYTE WRITE cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW se- lects an access cycle for the upper byte (DQ8-DQ15). Each ...

Page 3

PAGE ACCESS Page operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a row- address-defined page boundary. The page cycle is al- ways initiated with a row address strobed in by RAS#, followed by a column address strobed in ...

Page 4

However, an EARLY WRITE on one byte and a LATE WRITE on the other byte, after a CAS# precharge has been satisfied, are permissible. DRAM REFRESH Preserve correct memory cell data by maintaining power and executing any RAS# cycle (READ, ...

Page 5

WE# CASL# CAS# CASH# NO. 2 CLOCK GENERATOR COLUMN- ADDRESS 10 BUFFER A0 REFRESH A1 CONTROLLER REFRESH A5 COUNTER ROW- A9 ADDRESS 10 BUFFERS (10) NO. 1 CLOCK RAS# GENERATOR 1 Meg x ...

Page 6

ABSOLUTE MAXIMUM RATINGS* Voltage on V Pin Relative 3.3V ......................................................... -1V to +4.6V 5V ............................................................... -1V to +7V Voltage on NC, Inputs or I/O Pins Relative to Vss: 3.3V ......................................................... -1V to +5.5V 5V ............................................................... -1V ...

Page 7

I OPERATING CONDITIONS AND MAXIMUM LIMITS CC (Notes notes appear on pages 10-11); (V PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS STANDBY CURRENT: CMOS (non-“S” version only) (RAS# = CAS# = ...

Page 8

CAPACITANCE (Notes notes appear on pages 10-11) PARAMETER Input Capacitance: Addresses Input Capacitance: RAS#, CASL#,CASH#, WE#, OE# Input/Output Capacitance ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12; notes appear on pages 10-11); ...

Page 9

AC ELECTRICAL CHARACTERISTICS (continued) (Notes 10, 11, 12; notes appear on pages 10-11 CHARACTERISTICS PARAMETER OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access ...

Page 10

NOTES 1. All voltages referenced The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0ºC commercial) and (-20º ensured initial pause ...

Page 11

NOTES (continued) 26.Each CAS#x must meet minimum pulse width. 27.The last CAS#x edge to transition HIGH. 28.Last falling CAS#x edge to first rising CAS#x edge. 29.Last rising CAS#x edge to first falling CAS#x edge. 30.Last rising CAS#x edge to next ...

Page 12

V IH RAS CRP V IH CASL#/CASH ASR V IH ADDR WE OE TIMING PARAMETERS -5 SYMBOL MIN MAX ...

Page 13

V IH RAS CRP CASL#/CASH ASR V IH ADDR ROW IOH DQ V IOL TIMING PARAMETERS -5 SYMBOL MIN ...

Page 14

WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CASL#/CASH ASR V IH ADDR ROW WE IOH DQ V IOL ...

Page 15

V IH RAS CSH t CRP V CASL#/CASH RAD t RAD t ASR t RAH V IH ADDR V ROW OPEN ...

Page 16

V IH RAS CSH t CRP V IH CASL#/CASH RAD t ASR t RAH V IH ADDR V ROW WE IOH DQ V IOL V IH OE# V ...

Page 17

WRITE and READ-MODIFY-WRITE cycles RAS CRP CASL#/CASH RAD t ASR t RAH V IH ADDR ROW IOH DQ V ...

Page 18

EDO-PAGE-MODE READ EARLY WRITE CYCLE V IH RAS CRP V IH CASL#/CASH RAD t ASR t RAH V IH ADDR ROW WE IOH DQ OPEN V IOL ...

Page 19

V IH RAS CRP V IH CASL#/CASH ASR V IH ADDR WE OE TIMING PARAMETERS -5 SYMBOL MIN MAX ...

Page 20

V IH RAS CRP V IH CASL#/CASH ASR V IH ADDR RAS RPC CASL#/CASH ...

Page 21

V IH RAS CRP V IH CASL#/CASH ASR t RAH V IH ADDR ROW IOH DQx V IOL TIMING PARAMETERS -5 SYMBOL MIN MAX t AA ...

Page 22

RAS RPC CSR V IH CASL CASH WRP TIMING PARAMETERS -5 SYMBOL MIN MAX t CHD 15 ...

Page 23

PIN #1 INDEX .031 (0.80) TYP NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per ...

Page 24

PIN #1 INDEX SEATING PLANE NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" ...

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