MT4LC1M16C3TG-5 Micron Semiconductor Products, MT4LC1M16C3TG-5 Datasheet

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MT4LC1M16C3TG-5

Manufacturer Part Number
MT4LC1M16C3TG-5
Description
Manufacturer
Micron Semiconductor Products
Datasheet
FPM DRAM
FEATURES
• JEDEC- and industry-standard x16 timing,
• High-performance, low-power CMOS silicon-gate
• Single power supply (+3.3V ±0.3V or 5V ±0.5V)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
• Optional self refresh (S) for low-power data
• BYTE WRITE and BYTE READ access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• FAST-PAGE-MODE (FPM) access
OPTIONS
• Voltage
• Packages
• Timing
• Refresh Rates
• Operating Temperature Range
NOTE: 1. The third field distinguishes the low voltage offering:
KEY TIMING PARAMETERS
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
SPEED
functions, pinouts, and packages
process
(CBR) and HIDDEN
retention
3.3V
5V
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
50ns access
60ns access
Standard Refresh (16ms period)
Self Refresh (128ms period)
Commercial (0
Extended (-20
-5
-6
2. Contact factory for availability.
3. Available only on MT4C1M16C3 (5V)
LC designates V
110ns
84ns
t
1
RC
MT4LC1M16C3DJ-5
o
o
t
C to +80
50ns
60ns
RAC
C to +70
Part Number Example:
CC
= 3.3V and C designates V
20ns
35ns
t
PC
o
o
C)
C)
25ns
30ns
t
AA
MARKING
t
15ns
15ns
CAC
CC
= 5V.
None
None
ET
LC
TG
DJ
S
-5
-6
C
2
3
30ns
40ns
t
RP
1
MT4C1M16C3, MT4LC1M16C3
For the latest data sheet revisions, please refer to the Micron
Web site:
1 MEG x 16 FPM DRAM PART NUMBERS
GENERAL DESCRIPTION
state memory containing 16,777,216 bits organized in
a x16 configuration. The 1 Meg x 16 DRAM has both
BYTE WRITE and WORD WRITE access cycles via two
CAS# pins (CASL# and CASH#). These function identi-
cally to a single CAS# on other DRAMs in that either
CASL# or CASH# will generate an internal CAS#.
the first CAS# (CASL# or CASH#) to transition LOW and
PART NUMBER
MT4LC1M16C3DJ-6
MT4LC1M16C3DJ-6 S
MT4LC1M16C3TG-6
MT4LC1M16C3TG-6 S
MT4C1M16C3DJ-6
MT4C1M16C3TG-6
RAS#
WE#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
NOTE: The # symbol indicates signal is active LOW.
V
V
V
NC
NC
NC
NC
A0
A1
A2
A3
The 1 Meg x 16 DRAM is a randomly accessed, solid-
The CAS# function and timing are determined by
CC
CC
CC
42-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
www.micron.com/datasheets
PIN ASSIGNMENT (Top View)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
DQ15
DQ14
DQ13
DQ12
V
DQ11
DQ10
DQ9
DQ8
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
V
SS
SS
SS
SUPPLY PACKAGE REFRESH
RAS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
WE#
V
V
V
NC
NC
NC
NC
NC
A0
A1
A2
A3
3.3V
3.3V
3.3V
3.3V
CC
CC
CC
5V
5V
44/50-Pin TSOP
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
1 MEG x 16
FPM DRAM
TSOP
TSOP
TSOP
SOJ
SOJ
SOJ
©2001, Micron Technology, Inc.
OBSOLETE
Standard
Standard
Standard
Standard
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
Self
Self
V
DQ15
DQ14
DQ13
DQ12
V
DQ11
DQ10
DQ9
DQ8
NC
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
V
SS
SS
SS

Related parts for MT4LC1M16C3TG-5

MT4LC1M16C3TG-5 Summary of contents

Page 1

... TG 1 MEG x 16 FPM DRAM PART NUMBERS -5 -6 PART NUMBER MT4LC1M16C3DJ-6 None MT4LC1M16C3DJ MT4LC1M16C3TG-6 MT4LC1M16C3TG-6 S MT4C1M16C3DJ-6 None MT4C1M16C3TG GENERAL DESCRIPTION The 1 Meg x 16 DRAM is a randomly accessed, solid- state memory containing 16,777,216 bits organized x16 configuration. The 1 Meg x 16 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#) ...

Page 2

GENERAL DESCRIPTION (continued) the last CAS# to transition back HIGH. Use of only one of the two results in a BYTE access cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW se- ...

Page 3

FAST PAGE MODE ACCESS (continued) The MT4LC1M16C3 must be refreshed periodically in order to retain stored data. FAST PAGE MODE ACCESS FAST-PAGE-MODE operations allow faster data op- erations (READ, WRITE or READ-MODIFY-WRITE) within a row-address-defined (A0-A9) page boundary. The FAST-PAGE-MODE ...

Page 4

Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For ex- ample, an EARLY ...

Page 5

ABSOLUTE MAXIMUM RATINGS* Voltage on V Pin Relative 3.3V ..................................................... -1V to +4.6V 5V ........................................................... -1V Voltage on NC, Inputs or I/O Pins Relative to V 3.3V ..................................................... -1V to +5.5V 5V ........................................................... -1V Operating Temperature T ...

Page 6

I OPERATING CONDITIONS AND MAXIMUM LIMITS CC (Notes notes can be found on page 9); V PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS STANDBY CURRENT: CMOS (non-“S” version only) (RAS# = ...

Page 7

AC ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12; notes can be found on page 9 CHARACTERISTICS PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time ...

Page 8

AC ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12; notes can be found on page 9 CHARACTERISTICS PARAMETER RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE ...

Page 9

NOTES 1. All voltages referenced This parameter is sampled MHz dependent on output loading. Specified CC values are obtained with minimum cycle time and the output open. 4. Enables ...

Page 10

NOTES (continued) 32. Last rising CASx edge to first falling CASx edge. 33. First DQs controlled by the first CASx to go LOW. 34. Last DQs controlled by the last CASx to go HIGH. 35. Each CASx must meet minimum ...

Page 11

V IH RAS CRP CASL#/CASH ASR V IH ROW ADDR IOH DQ V IOL TIMING PARAMETERS -5 SYMBOL MIN ...

Page 12

V IH RAS CRP CASL#/CASH ASR V IH ADDR ROW IOH DQ V IOL TIMING PARAMETERS -5 SYMBOL MIN ...

Page 13

WRITE and READ-MODIFY-WRITE cycles RAS CRP CASL#/CASH ASR V IH ADDR ROW WE IOH DQ V IOL ...

Page 14

V IH RAS CSH t CRP V CASL#/CASH RAD t ASR t RAH V IH ADDR V ROW IL WE IOH DQ OPEN V IOL V IH OE# ...

Page 15

FAST-PAGE-MODE EARLY WRITE CYCLE V IH RAS CSH t CRP V CASL#/CASH RAD t ASR t RAH V IH ADDR ROW IOH DQ V IOL ...

Page 16

WRITE and READ-MODIFY-WRITE cycles RAS CRP CASL#/CASH RAD t ASR t RAH V IH ADDR ROW IOH DQ V ...

Page 17

FAST-PAGE-MODE READ EARLY WRITE CYCLE V IH RAS CRP V IH CASL#/CASH ASR V IH ADDR V ROW WE OE ...

Page 18

V IH RAS CRP V IH CASL#/CASH ASR V IH ADDR RAS RPC CSR V IH CASL#/CASH# ...

Page 19

TIMING PARAMETERS -5 SYMBOL MIN MAX MIN ASC 0 t ASR 0 t CAC 15 t CAH 8 t CHR 8 t CLZ 0 t CRP NOTE: 1. ...

Page 20

RAS RPC CSR V IH CAS WRP TIMING PARAMETERS -5 SYMBOL MIN MAX MIN t CHD 15 ...

Page 21

PIN #1 INDEX SEATING PLANE 1. All dimensions in inches (millimeters) MAX or typical where noted. NOTE: 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" ...

Page 22

PIN #1 INDEX .031 (0.80) TYP 1. All dimensions in inches (millimeters) MAX or typical where noted. NOTE: 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per ...

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